DE4038903A1 - ARRANGEMENT FOR PROCESSING SIGNALS IN THE MODULATION WAY TO A TRANSMITTER - Google Patents

Description

The invention relates to an arrangement for processing Signals in the modulation path to a transmitter according to the generic term of claim 1.

The modulation signal to a transmitter does not contain today only the actual program signals, such as. B. a radio broadcasting program, but more and more additional signals that perform different tasks. Since the bandwidth of the Modulation signals is limited, these additional signals usually placed close together in the frequency spectrum.

If you want to separate the individual signal components again, this is usually very difficult to achieve analogously and with quality losses. An example here is the VHF multiplex spectrum (VHF = ultra-short-wave radio), which also has, inter alia, a signal component for the RDS data (RDS = radio data system) (cf. FIG. 1). This is 57 KHz ± 2.4 KHz.

In the RDS ball reception z. B. it is now a question of removing the old RDS data from an FM multiplex signal and then replacing it with new RDS data. For this purpose, it has already been proposed to demultiplex the multiplex signal with a stereo decoder in order to then completely re-encode the signal with the new RDS data. To re-encode, the left and right NF bands must be filtered with a 15 KHz low pass. For the stereo decoder using a newly generated MPX signal (MPX = Multiplex), however, all frequency ranges above 53 KHz (such. As RDS and SCA signal (SCA = S ubsidiary- C ommunications- uthorization A) and other auxiliary carrier missing , where the SCA signal generally has the function of an additional signal), which must then be added. This complex route can be avoided if it is possible to implement a filter that only removes the RDS signal from the MPX signal. The differential signal up to 53 KHz and the SCA channel starting from 61 KHz must not be affected by the filtering.

This means that in this example a bandstop filter must be realized, which up to 53 KHz and from 61 KHz a pass band and one of 54.6 KHz 59.5 KHz Has restricted area. Furthermore, the filter function be linear phase, so that when demultiplexing the  FM MPX signals the two stereo channels of the program can be separated well.

The object of the invention is therefore an arrangement of the type mentioned to create the most possible broadband not only signals from the audio frequency range, but also process from higher frequency ranges can, which is linear and with which, if necessary within the bandwidth of the signal to be processed individual frequency bands which are narrow in comparison to the bandwidth of the signal spectrum with its own filter functions can be applied without the other frequency components the signal in amplitude and / or Phase can be influenced.

The inventive solution to this problem is in claim 1 described. The remaining claims included advantageous training and further developments of the invention.

The achievement of the object is that that in the arrangement for processing signals in the modulation path a digital filter for a transmitter Filter is.

A digital filter offers u. a. Advantages in terms of its accuracy, reproducibility and flexibility. In a further development of the invention, the digital works Filters therefore with a filter function that is variable in type is that of several previously defined transfer functions one of these transfer functions as Filter function is selected and at a later date possibly to another of these transfer functions  can be switched as a new filter function can, possibly followed by further switching to the original transfer function or to others of these functions. With this possibility you can do different For example, different times Frequency bands differ within the signal spectrum are processed. The individual frequency components can individually change in amplitude be relaxed, subdued or strengthened.

Especially with regard to the exchange of RDS data is provided in an advantageous embodiment of the invention, that the digital filter has a transfer function as a filter function, according to which the filter is digital Band reject filter one or more frequency band limited Additional signals (such as the RDS signal) within of the signal spectrum in the modulation path to the transmitter in your Dampens amplitude so far that in the resulting "gap" or the resulting "gaps" in the frequency spectrum of the processing signal then new frequency band limited Additional signals (such as the new RDS signal) inserted can be without the remaining Residual signal disturbing the new additional signal.

An advantageous especially with regard to the required linear-phase version of the digital filter of the inventive arrangement is known per se transversal filter which is also known under the name of FIR filters (FIR = F Destinite-Duration, I mpulse- R esponse) (see. see, for example, Meinke, Gundlach: "Taschenbuch der Hochfrequenztechnik", Volume 1: Fundamentals; 4th edition (Springer, Berlin, 1986), pages F4-F6).

The filter works according to a method in which, in the steady state, a temporal sequence of digital output signals a _{i is} formed, each of which is the sum of N products, which in turn are the result of a multiplication of a digital signal of the first type with a digital signal of the second type are. More precisely, in this method, digital input signals e _i , e _{i + 1,.} . . e _{i + N-1} (as signals of the first type) during a clock interval ΔT _i with predetermined digital filter coefficients c₁. . . c _N multiplied and then the products thus obtained summed up to the corresponding digital output signal a _i according to the regulation:

In the next clock interval ΔT _{i + 1} , the next digital output signal a _{i + 1 is} formed in accordance with this regulation:

and in the following clock interval ΔT _{i + 2} the digital output signal a _{i + 2} :

etc.

The sequence of digital input signals e _i results here ia by sampling an analog signal with the sampling rate f₁ = 1 / ΔT, so that synchronously with each sampling, ie with each generation of a digital input signal e _i in the corresponding clock interval ΔT _i also a digital output signal a _{i is} generated.

The performance, d. H. the computing capacity of the filters, with which these methods for digital signal processing is generally performed by this measured how large the bandwidth of the to be processed analog signal and after what function and with what accuracy this signal must be processed.

On the basis of the bandwidth, one can according to the sampling theorem Specify the minimum sampling frequency. Generally, digital Signal processing systems their computing algorithm have performed within a sampling interval, d. H. ever the higher the bandwidth, the shorter the available standing time.

One way to build digital signal processing systems consists of discrete multiples adder / adder modules (MACs). You can one or more multiplication units and one or have multiple addition units on one block. They only perform the basic functions of multiplication and addition but faster than those available today Signal processors.

The construction of a digital filter with discrete MACs enables due to the high processing speed the MACs the processing of high bandwidth input signals. Furthermore, the computational effort is also determined by the degree the accuracy of machining. Within a  Such a MAC must have a certain number of sampling intervals of multiplications and additions to form a digital Complete the output signal one after the other.

In some cases, however, it is within a sampling interval not enough time for everyone to form a digital Output signal required multiplications or To be able to perform additions, so that even when used of MACs instead of monolithic signal processors such systems or processes in processing broadband signals can reach their performance limits.

To avoid these difficulties, i. h to a digital Transversal filter even at higher sampling rates and / or with a larger number from within a sampling interval multiplications or additions to be carried out Being able to operate reliably is one Further development of the invention a modification of the mode of operation and, associated with it, the construction of the transversal filter intended.

In the modification of the mode of operation according to the invention, the N multiplications (N2) of the digital signals of the first type (here the signals to be processed) to be carried out to form the individual digital output signals a _i (i = 1, 2...) Are made second with the digital signals Type (here the digital filter coefficient) in M groups G₁. . . G _M (M2) split. The individual groups G _m (m = 1,.... M) of multiplications are now no longer all carried out in the same clock interval ΔT to form the corresponding output signal, but separated from one another in time intervals M in successive clock intervals ΔT₁. . . ΔT _M.

The products of the m-th group G _m of multiplications formed in the m-th cycle interval ΔT _m (m = 2,... M) are, according to the invention, formed in the previous (m-1) -th cycle interval ΔT _m-1 and stored subtotal Z _m-1 of the respective (m-1) previous clock intervals ΔT₁. . . ΔT _m-1 formed products of the (m-1) groups G₁. . . G _m-1 added. Then the total value formed in this way is ΔT 1 in m clock intervals. . . ΔT _m formed products of the m groups G₁. . . G _m of multiplications for m = 2,. . . M-1 is stored as a new subtotal Z _m for the summation in the subsequent (m + 1) th clock interval ΔT _{m + 1} and is output for m = M as the digital output signal belonging to these N multiplications.

Since only a portion of the multiplications and additions required for the formation of a digital output signal a _{i are} always carried out in the individual clock intervals ΔT _i (i = 1, 2...), The method of operation according to the invention is used to optimally utilize the available computing capacity or MACs each output in each clock intervals .DELTA.T _i parallel and independently of each other first, the i-th digital output signal a _i and this i-th digital output signal a _i respectively following (M-1) digital output signals to the other for a _{i + m} (m = 1,... M-1) in each case the (Mm) th subtotal Z _{Mm is} formed and stored.

The digital signals of the first type to be processed and the second type each consist of one or more Bits. With how many bits the amplitude of the digital signals displayed depends on how accurate the amplitude should be shown or quantized. Takes if you only have one bit, you can only make the statement, amplitude available or not available, 16 bits are used, so the amplitude can be resolved in 65 536 steps. The advantage of this method is that it for any word width (= number of bits) of the digital signals first and second type can be used, wherein the number of bits i. a. for all signals first and second Kind is the same. The word widths can also be used different from the signals of the first and second kind be (i.e., it is also a (e.g.) 14-bit by 16 Bit multiplication possible).

In an advantageous embodiment, in the event that N / M = K is a natural number, all M groups G 1. . . G _M each have the same number K (K = 1, 2, 3...) Of multiplications. In the event that N / M is not a natural number, only (M-1) of the M groups have G₁. . . G _M each have the same number K '= (NL) / (M-1) of multiplications, while one of the M groups G₁. . . G _{M has} a number L of multiplications different from K ', K' and L preferably being chosen such that L <K '. The first or the last group G 1 or G _M is expediently chosen as the group with the L multiplications.

Do the digital signals of the first type consist here of a temporal sequence of digital input signals e _i (i = 1, 2...) And the digital signals of the second type z. B. from N predetermined digital filter factors c₁. . . c _N , so that the individual digital output signals a _{i are formed in} accordance with the rule given in equation (1), it is advantageous that the two temporal sequences of the digital input signals e _i and digital output signals a _i (i = 1, 2. ..) are synchronized in time with a clock frequency f _e = f _a = f 1 = 1 / ΔT which is the same for both sequences a _i and e _i , so that in the steady state with each new, e.g. B. by sampling an analog signal obtained digital input signal e _i , a digital output signal a _{i is} output.

In the event that the clock frequency f _d of digital input signals to be processed d _j (j = 1, 2...) For the digital transversal filter according to the invention is too high or the clock frequency f 1 of the generated digital output signals a _i for downstream arrangements is too low, in an advantageous development of the invention use is made of the known decimating or interpolating methods (cf. in this regard: RW Schafer, LR Rabiner: "A Digital Signal Processing Approach to Interpolation", in: Proceedings of the IEEE , Vol. 61, No. 6, June 1973, pp. 692-702) by decimating the temporal sequence of the digital input signals e _i (i = 1, 2...) That are to be with the digital filter the temporal sequence of the digital input signals d _j (j = 1, 2...) with the clock frequency f _d = p · f _e = p · f₁ (p = 2, 3...) is formed, or the temporal sequence the digital output signals a _i (i = 1, 2...) by interpolating into a temporal F digital output signals b _l (l = 1, 2. . .) with a clock frequency f _b = q · f _a = q · f₁ (q = 2, 3...) is converted.

Conveniently, the two time sequences are in this case the digital input signals d _j and digital output signals b _l synchronized in time with a d for both sequences _j and b _l matched clock frequency f _b = f _d = f = n · f₁ (n = 2, 3...).

When digitally filtering an analog signal in the Modulation path to a transmitter is this down and Increasing the sampling frequency is often necessary because on the one hand to simplify an upstream analog Anti-aliasing filter or a downstream one Reconstruction filter the sampling rate as high as possible to choose. On the other hand, this is in conflict on the condition of choosing a small sampling rate to choose between as much computing time as possible for the individual input values to have more complicated transfer functions to realize.

The solution, as described above, is the sampling rate to select high at the analog input and then select it for the actual calculation of the desired transfer function in the calculator. In order to this can be done without aliasing effects before the actual digital filter be a filter what which prevents aliasing effects. So you can do this Filters what is in the digital signal chain after the Ana log / digital conversion, but before the actual digital Filter comes to be called digital anti-aliasing filter. In summary, go into this digital anti-aliasing filter  Input values with the real sampling frequency but the initial values come with the reduced one Guess out.

With the help of a downstream of the actual digital filter digital interpolation or reconstruction filter it is possible to get the output rate back up to set the actual sampling frequency. That’s it Spectrum with the (higher) sampling frequency periodically, see above that the subsequent analog reconstruction filter easier can be designed.

The transversal filter, which has been modified accordingly, that processes the signals in this way exists from an N-stage transversal filter, which in the usual Way (see the paperback mentioned above high-frequency technology) with an input line for digital signals of the first kind, one or an output line containing discrete adders for the digital output signals as well as with total N each connecting the input line to the output line discrete multipliers and a total of N-1 buffers is provided and according to the invention in M complete and cascaded in series Transversal sub-filter is divided by connecting to M-1 Positions both in the input line and in the output line one additional buffer each is inserted.

In an advantageous embodiment of the invention Modification of the transversal filter has all M Transversal sub-filters each have the same number  K = N / M from multipliers, provided that N / M is a natural one Number is.

In the event that N / M is not a natural number, in another advantageous embodiment, only M-1 the M transversal sub-filter has the same number K ′ = (N-L) / (M-1) from multipliers to the remaining one a transversal sub-filter one of K 'different Number L of multipliers with preferably L <K '. Conveniently becomes either the first or the last Transversal sub-filter of the filter cascade, but preferably the last transversal sub-filter with L multipliers fitted.

The cascading technology according to the invention is based on an example of a six-stage FIR filter explained in more detail.

If, due to the limited computing time, only three-stage FIR Filters would be used, you would have a six-stage Implement FIR filters from two three-stage FIR filters. For example, if you start from the one in Figure 8 on page F6 of Volume 1 of the above-mentioned pocket book of radio frequency technology specified FIR filter structure with an input line for the digital input signals to be processed, an output line containing the adder (s), the N (here: N = 6 or 3) each the input line multipliers connecting to the output line and the N-1 (here: N = 5 or 2) buffers or Delay levels in the input line off, detects one that the chain of buffers or Delay stages would have to continue, i. H. that the Output of the second delay stage of the first three-stage  FIR filter via an additional buffer connected to the input of the second three-stage FIR filter should be.

On the other hand, the two partial sums of the two partial filters would have to be added at the end of the calculation process. This would cost additional time in the sampling interval so that in the end fewer stages could be realized on the other hand, you would have an additional adder module need, on which two z. B. 35-bit summands can invest so that the final sum is available. The Enter a 35-bit wide word, for example MAC already described without destroying the previous one The contents of the adder would not be possible.

Both can be done with the cascading technology according to the invention avoid the partial result of the previous one FIR sub-filter in the adder of the subsequent FIR sub-filter preloads delayed by a clock interval.

In this example, the first three-stage FIR filter calculates the first part of the transfer function of the digital filter, ie in this example the sum of the first three products. This partial sum is then preloaded into the adder of the second three-stage FIR filter, which then adds its partial sum of the last three products in the next clock interval. At the end of the second clock interval, the result is finished and can be output as a digital output signal a _i . During the second clock interval, of course, the first FIR filter calculates on the first partial sum of the subsequent digital output signal a _{i + 1} , ie both structures use the full computing time, only they calculate on different sums during a clock interval.

Since the individual sub-filters are not at the same time Calculate the same sum, but from sub-filter to sub-filter offset by one clock period, the chain of delayed and stored input signals during the transition in the next sub-filter by an additional clock interval be delayed. The first subtotal is therefore passed on only in the next cycle interval.

The multiplier / adder modules allow precharging of the entire n-bit wide (for example, the 35-bit wide) Adder word to, d. H. no rounding is required, which also leads to inaccuracies in the transfer function would lead.

An essential feature of this cascading technique is that the filter has a larger dead time by M · ΔT if you cascaded the FIR filter out of M in this way Sub-filters.

When implementing this procedure one can look for the additional Delay levels additional storage elements use or this method in the algorithm for the Integrate control of one or more memory modules.

In the following, the invention will be explained in more detail with reference to the figures explained. It shows

Fig. 1 shows the frequency spectrum of the FM multiplex signal already mentioned at the beginning

Fig. 2 shows the circuit diagram of a first advantageous embodiment of the digital filter of the arrangement according to the invention

Fig. 3 shows the circuit diagram of a second advantageous embodiment of the digital filter of the arrangement according to the invention

Fig. 4 shows the circuit diagram of an advantageous embodiment of the arrangement according to the invention for the exchange of RDS data in a transmitter with ball reception

Fig. 5 is a diagram of an advantageous embodiment of the RDS band stop filter in the inventive arrangement of FIG. 4

Fig. 6 typical transfer functions of individual filters of the RDS band-stop filter according to Fig. 5

Fig. 2 shows an inventive modified transversal filter 1 , in which a total of M complete transverse sub-filter T₁, T₂,. . . T _M are cascaded in series.

Each of these M sub-filters T₁, T₂,. . . T _M consists of an input line E₁, E₂,. . . E _M for the digital input signals e _i and an adder S₁, S₂. . . S _M , the output line A₁, A₂,. . . A _M for the individual subtotals Z _Mm for the corresponding digital output signals a _{i + m} (m = 1, 2,... M-1), which temporally follow the respective digital output signal a _i output at output A.

Input and output line of the respective sub-filter T₁, T₂. . . T _M are each by (for example) N = 3 multipliers M₁-M₃; M₄-M₆,. . ., M _N-2 -M _N connected together. The individual multipliers M₁-M _N are each with their first input to the input line E₁-E _M and with their output to the adder S₁-S _{M of} the corresponding sub-filter T₁, T₂. . . T _M connected. At the second input of the individual multipliers M₁M _N is one of the N predetermined digital filter coefficients c _N -c₁.

In this case, the first and second inputs and outputs of the individual multipliers M 1-M _N , which are only symbolically drawn in the figure, in reality generally consist of one or more inputs and outputs, the number of each of which corresponds to the number of bits of the digital input signals to be processed or corresponds to the digital filter coefficients (for input signals with a bit length of 35 bits e.g. 35 first and 35 second inputs and 35 outputs per multiplier).

Between the first inputs of adjacent multipliers M₁, M₂ or M₂, M₃ or M₄, M₅ or M₅, M₆ or M _N-2 , M _N-1 or M _N-1 , M _{N of} the individual sub-filters T₁, T₂ ,. . . T _M a buffer τ₁-τ _{N-1 is} inserted. Both the input lines E₁-E _M and the output lines A₁-A _M adjacent sub-filter T₁, T₂. . . T _M are each connected to one another by an additional buffer store τ _e1 , τ _a1 or τ _e2 , τ _a2 or τ _{e (M-1)} , τ _{a (M-1)} .

The digital input signals e _i are at the input E via the additional buffers τ _e1 , τ _e2 . . . τ _{e (M-1)} series-connected input lines E₁-E _M on. The output signals a _i formed in the digital filter become at the output A via the additional buffers τ _a1 , τ _a2 . . . τ _{a (M-1)} series-connected output lines A₁-A _M output.

The arrangement of FIG. 3 differs from the arrangement of FIG. 2 only in that, on the one hand, the buffer τ₁-τ _N-1 now alternating with the adders S₁-S _N-1, the output lines A₁-A _{M of} the individual transversal -Teilfilter T₁ ', T₂'. . . T _M 'form and that on the other hand the first inputs of the individual multipliers M₁-M _{M in} parallel at the input E for the digital input signals to be processed e _i (M₁-M₃) or at the output of the upstream additional buffer τ _e1 (M₄-M₆ ). . . τ _{e (M-1)} (M _N-2 -M _N ).

In addition, the order of the digital filter coefficients c₁-c _N at the second inputs of the individual multipliers M₁-M _{N has} been exchanged with respect to the arrangement according to FIG. 1, so that both in the arrangement according to FIG. 2 and in the arrangement according to FIG. 3 the individual digital output signals a _{i are formed} according to the regulation in accordance with equation (1).

The arrangement according to the invention according to FIG. 2 works as follows:

At the input E, the digital input signals to be processed appear successively in time f 1 = 1 / ΔT. . . e _i-2 , e _i-1 , e _i , e _{i + 1} , e _{i + 2,.} . . etc., which may have been formed, for example, by sampling an analog signal with the sampling frequency f 1 or by decimating from a sequence of second digital signals d _j with the clock frequency f _d = p * f 1 (p = 2, 3...).

Via the buffer τ₁-τ _N-1 or the additional buffer τ _e1 , τ _e2 . . . τ _{e (M-1)} , the individual digital input signals e _i clock by clock successively by the individual sub-filters T₁, T₂,. . . T _M pushed and in the i-th cycle with c _N , in the (i + 1) -th cycle with c _N-1 , in the (i + 2) -th cycle with c _N-2 etc. and finally in (i + N-1) -th measure multiplied by c₁. The respective in the additional buffers τ _e1 , τ _e2 . . . However, τ _{e (M-1)} stored signals are only multiplied by one of the N filter coefficients in the subsequent clock interval.

In the additional memories τ _{a (M-1)} ,. . ., τ _a2 , τ _a1 (in this order) the respective subtotals Z _{Mm of} the individual digital output signals a _{i + m to} be formed (m = 1, 2,... M-1) are stored for each clock interval ΔT _i , while the i-th digital output signal a _{i is} output at output A.

Taking into account the processing instructions for the digital input signals according to equation (1), the following occurs in the i-th clock interval ΔT _i :

• - at output A is the i-th digital output signal spent;
• - The _subtotal is in each of the additional buffers τ _{a (Mm)} stored for the (i + m) th digital output signal a _{i + m} following the i-th digital output signal a _i at intervals of m clock intervals ΔT;
• - the individual extra caching τ _{e (mm),} respectively, the (i + m ((N / M) +1) -1) th digital input signal e _{i + m ((N / M) +1) -1} ( 6) (m = 1, 2,... M-1) saved.

In the subsequent (i + 1) th clock interval ΔT _{i + 1} , the individual digital input signals e _{i are} each one buffer τ₁-τ _N-1 or τ _e1 , τ _e2 . . . τ _{e (M-1)} pushed on:
if in the i-th cycle interval ΔT _i z. B. the signal e _i in the buffer τ _N-1 , the signal e _{i + 1} in the buffer τ _N-2 , the signal e _{i + 2} in the additional buffer τ _{e (M-1)} , etc. were stored in the (i + 1) th clock interval ΔT _{i + 1} in the buffer τ _N-1 now the signal e _{i + 1} , in the buffer τ _N-2 now the signal e _{i + 2} and in the additional buffer τ _{e (M-1)} now the signal e _{i + 3} etc. stored.

Taking into account the processing instructions for the digital input signals according to equation (1), the following then occurs in the (i + 1) th clock interval ΔT _{i + 1} :

• - at output A is the (i + 1) th digital output signal spent;
• - The _subtotal is in each of the additional buffers τ _{a (Mm)} stored for the (i + 1) -th digital output signal a _{i + 1} at a time interval of m clock intervals ΔT (i + 1 + m) -th digital output signal a _{i + 1 + m} ;
• - The (i + 1 + m ((N / M) +1) -1) th digital input signal e _{i + 1 + m ((N / M) +1} is in each case in the individual additional buffers τ _{e (Mm) ) -1} (9) (m = 1, 2... M-1) saved.

In general, the (i + j) th cycle interval ΔT _{i + j} (i, j = 1, 2...) Presents the following situation:

• - at output A is the (i + j) th digital output signal spent;
• - The _subtotal is in each of the additional buffers τ _{a (Mm)} stored for the (i + j) th digital output signal a _{i + j} following (i + j + m) th digital output signal a _{i + j + m} at intervals of m clock intervals ΔT;
• - The (i + j + m ((N / M) +1) -th digital input signal e _{i + j + m ((N / M) +1) -1} is in each case in the individual additional buffers τ _{e (Mm)} (12) (m = 1, 2, ... M-1) saved.

The arrangement according to the invention according to FIG. 3 functions in a similar manner.

The following generally occurs there in the kth cycle interval ΔT _k :

• - at output A is the kth digital output signal spent;
• - The _subtotal is in each of the additional buffers τ _{a (Mm)} stored for the (k + m) th digital output signal a _{k + m} following the k-th digital output signal a _k at intervals of m clock intervals ΔT;
• the (k + 2m-1) th digital input signal e _{k + 2m-1} (15) (m = 1, 2,...) is stored in the individual additional intermediate memories τ _{e (Mm)} ,

where k compared to the previous functional description of the arrangement of FIG. 1 z. B. k = i, i + 1 or generally i + j (i, j = 1, 2...).

The configuration selected in the two arrangements according to FIG. 2 or FIG. 3 with M partial filters with three multipliers each is only to be understood as an example.

In the event that N / M is a natural number, it is generally advantageous if all M transversal sub-filters T₁, T₂,. . . T _M or T₁ ', T₂'. . . T _M 'each have the same number K = N / M of multipliers.

In the event that N / M is not a natural number, it is Generally advantageous if at least (M-1) the M Transversal sub-filters each have the same number K ′ = (N-L) / (M-1) of multipliers and that remaining one of the M sub-filters (especially the first or the last, but preferably the last sub-filter) has a different number L from multipliers L ' with preferably L <K '.  

The factors required for multiplication must be the individual Multiplier / adder modules (MACs) from the outside Tobe offered. These factors are expedient in a storage unit with several storage locations. Addresses must be created on this storage unit so that a storage location and thus a date for the multiplication to be performed can be selected.

It is therefore particularly advantageous to also use the individual buffers τ ₁ -τ _N-1 and / or additional buffers τ _e1 , τ _e2 . . . τ _{e (M-1)} or τ _a1 , τ _a1 . . . τ _{a (M-1)} each to be realized by an addressable and / or controllable memory unit and to connect these memory units via their addressing and / or control inputs to an addressing and / or control unit containing one or more address generators.

For a simple FIR filter structure, for example, is sufficient a counter for address generation.

Signal input values, factors, partial results and signal output values are offered by such a storage unit or taken over. This logical storage unit can made up of several discrete memory modules be.

The storage unit can also serve several MACs. The Storage unit in turn gets its addresses from that Control unit that contains the address generators. Further this control unit also generates control signals for the storage unit and for the MACs. By the way like the control signals or according to which algorithm the addresses  generated depends on the type of actual digital Signal processing.

The respective addresses and control signals for the storage units can advantageously by or generated several programmable digital logic modules be, so the actual type of signal processing from the algorithm of address generation, d. H. of these Logic modules depends. Under programmable logic Building blocks are discrete digital circuits, which the output signals by logically combining Generate input signals and output signals, where the type of link depends on how these building blocks were programmed.

Depending on the control signals on these logic modules can address the algorithm of address generation change so the signal in a different way can be edited. This has the consequence and the invention Advantage that the type of signal processing or the algorithm of programming these modules is dependent. Furthermore, depending on the Input signals for these blocks the processing of the actual signals can be changed. In the application The arrangement can be used as a digital filter in this way get a different filter structure and filter length. Further the filter structure can be divided into several sub-filters be, so that a chain from a digital filter of digital filters connected in series in the signal path becomes.  

It follows that the actual type of signal processing depends on the algorithm according to which these addresses for one or more memory chips to be generated.

According to the invention, it is advantageous to use this algorithm to make the address generation variable in order to create a discrete multiplier / adder modules (MACs) Signal processing system to be able to create what is variable in the type of signal processing.

As already described, this control unit is advantageous through one or more programmable digital logic modules realized. This gives you flexibility in the type of digital signal processing, d. H. which tasks the signal processing systems met. You can on the one hand by reprogramming the logical modules can achieve on the other hand through control signals for this logical building blocks are determined, like the actual one Signal to be processed. That way digital filtering can be varied, and here in particular the filter structure, the filter length and / or the Division of the overall filter into several Tiel filters different throughput rates, so that decimating and Interpolating are possible. You can also use this Filter arrangement but also methods for digital modulation and / or digital signal generation and / or links realized by these three types of processing will.

Furthermore, options for Self-test and monitoring of the circuit can be installed.  

The digital filter according to the invention has the following advantages on:

• - It is linear phase.
• - It can be used not only in the NF area, but also in frequency ranges beyond that.
• - Filter parameters such as filter order, sampling rate are adjustable. Optionally, a but digital integrated into the system Filter structure the throughput rate f 1 of the input values Arithmetic unit to the value f₁ = f / n (n = 2, 3...) (f = sampling frequency) can be reduced. This setting can also be done without hardware modification and is determined by a digital control word. By this option can use the computing power more effectively because more computing power is available stands. Alternatively (in reverse) by a Downstream, but integrated into the system, digital filter structure the output rate f the Output values at the output of the digital system on the Value f = n · f₁ (f₁ = throughput rate in the arithmetic unit) increased will. This setting can also be done without a Hardware modification is done and is done by a digital Control unit determines. Through a data interface it is possible to transmit characteristic values to the system, whereby e.g. B. the transfer function, the degree of filtering, the filter structure and / or the sampling frequency changed can be.  
• - With the system according to the invention can in particular
  • - signals whose bandwidth is greater than 80 kHz,
  • - unmodulated signals,
  • - Signals that consist of several frequency bands (multiplex band).
  • - signals of a multiplex band in the area of broadcasting,
  • - Signals of a multiplex band in the area of FM radio
• processed in an efficient manner.
• - The cascading technique according to the invention can, for. B. by inserting hardware elements (such as Buffer or arithmetic components) realized , but it can also be done by a special Algorithm implemented in the address generators, will be realized. Combinations of hardware Elements and software possible.
• - It can not only FIR filter structure (FIR = F inite- Duration, I mpulse- R esponse) can be realized, but also the IIR filter structures (IIR = I nfinite-Duration, I m Pulse R esponse).
• - Even with high computing power and a resulting one high processing speed is one fast synchronous data management possible.

With the arrangement according to the invention, a signal processing and / or generation system can now be created which can process bandwidths of at least 80 kHz, is linear in phase and processes the input signal in such a way that frequency bands of the input signal, the spacing of which is around (7 * 10 ^-3 ) -fold the bandwidth, can be applied with its own filter functions. The frequency bands used after the processing are only slightly changed in amplitude and phase. The method according to the invention is about a factor of ten faster than comparable conventional systems which are constructed with monolithic signal processors.

In practice (e.g. at RDS ball reception) this is usually the case Task, certain signal components (e.g. the old RDS data) to replace. To do this, the old signal components are filtered out of the signal spectrum and the new ones are added using a summation point.

In the arrangement shown in FIG. 4 for processing the VHF multiplex signal (cf. FIG. 1) in the modulation path to an VHF transmitter for the purpose of exchanging the RDS signal, the RDS coder which is to generate the new RDS signal requires one 19 kHz pilot tone, which is in a phase-locked relationship with the 19 kHz pilot tone, which is in the multiplex signal to be supplemented with the RDS signal. The RDS coder receives the old RDS data from an RDS decoder, which is connected on the input side to the ball receiver (not shown in FIG. 4) and from there receives the VHF multiplex signal, which is also fed into an RDS band-stop filter by first filtering out the old RDS signal component from the spectrum and then inserting the new RDS data generated by the RDS coder into the spectrum. The FM multiplex signal provided with the new RDS data is then forwarded to the FM transmitter (also not shown in FIG. 4).

FIG. 5 shows an advantageous embodiment of the RDS band-stop filter in the arrangement according to the invention for exchanging RDS data during ball reception according to FIG. 4.

The bandstop filter has a symmetrical input 10 , to which an analog anti-aliasing pre-filter 4 , an A / D converter 2 (with a sample and hold element, not shown and connected between pre-filter 4 and converter 2 ), the digital filter 1 , a D / A converter 3 and an analog reconstruction post-filter 5 . The output of the analog reconstruction post-filter 5 is connected to the first input 12 of a summing element 6 , which is connected on the output side via a switch 19 to the unbalanced output 11 of the RDS ban filter. The second input 13 of the summing element 6 is provided for feeding in the new RDS data (generated by the RDS coder (see FIG. 4)). The input 10 of the bandstop filter can be connected directly to the output 11 via a bypass line 17 which can be switched on by the switch 19 , the filter chain 1-5 with the summing element 6 connected at the output of the summing element 6 being separated from the output 11 of the bandstop filter when the bypass line 17 is switched on .

The output of the analog reconstruction filter 5 is also connected to a phase lock loop arrangement 9 for the 19 kHz pilot tone, the output 14 of which supplies the 19 kHz pilot tone for the RDS coder (cf. FIG. 4). The control inputs of A / D converter 2 , digital filter 1 , D / A converter 3 , switch 19 and phase lock loop arrangement 9 are connected to a microprocessor 7 , which is also connected to a control panel 15 (e.g. for the purpose of reprogramming or manual calling of the stored transfer function for the digital filter 1 ) and which can be coupled to further computers or microprocessors via a V.24 interface 16 and a connecting terminal 20 .

The digital filter 1 is preferably implemented in one of the two embodiments according to FIG. 2 or 3 with discrete MACs and addressable and controllable buffers or additional buffers and can be structured by the microprocessor in its transfer function if necessary so that, for. B. a first part of the filter 1 on the side of the A / D converter 2 as a digital anti-aliasing filter and a second part of the filter 1 on the side of the D / A converter 3 as a digital interpolating or digital reconstruction -Filter and the remaining middle part of filter 1 between these two filter parts work as an actual digital RDS bandstop filter.

In Fig. 6 are examples of typical transfer functions of such a filter chain with analog anti-aliasing pre-filter (Fig. 6a), a digital anti-aliasing filter (Fig. 6b), a digital band-stop filter (Fig. 6c), digital reconstruction filter (Fig. 6d ) and analog reconstruction post-filter ( Fig. 6e) shown, in the event that an input-side sampling frequency of exemplary f = 340 KHz by the digital anti-aliasing filter to a bandstop filter input frequency f₁ = f / 2 = 170 KHz reduced and then increased again to the original value by the digital reconstruction filter.

As can easily be seen from these frequency responses, the two analog pre- and post-filters only have moderately steep edges in the frequency response due to the very steep edges in the frequency response of the two digital pre- and post-filters, which considerably simplifies the structure of these filters. In Fig. 6 it can also be seen that with a digital bandstop filter because of the achievable large edge steepness in the frequency response, frequency-limited blocking areas can be realized, which are dimensioned such that the FM multiplex signal reaching up to 72 KHz (see Fig. 1) only the (old) RDS signal component is filtered out without the other signal components of the multiplex signal (in particular the stereo difference signal reaching up to 53 KHz and the SCA channel starting from 61 KHz) being noticeably influenced.

The RDS bandstop filter according to FIG. 5 works as follows:

The VHF multiplex signal present at the input 10 and originating from the ball receiver with the old RDS data is initially subjected to a first band limitation by the analog anti-aliasing pre-filter 4 (cf. also FIG. 6a). The band-limited signal is then converted by the sample and hold element (not shown) and the A / D converter 2 into a chronological sequence of digital input signals with the clock frequency f, which may be in the first part of the digital filter 1 on the input side, which is called digital Anti-aliasing filter is programmed to be subjected to a further band limitation by decimating (cf. FIG. 6b), which is associated with a corresponding reduction in the clock frequency to a value f 1 = f / n (n = 2, 3...) .

Subsequently, the digital input signals (or by further decimating band-limited digital input signals) in the digital filter 1 (or in its central part) are subjected to the actual digital filtering in the manner described above, the filter coefficients c₁-c _N being chosen in this way that only the RDS signal component is filtered out, while the other signal components of the multiplex spectrum remain more or less unchanged (cf. FIG. 6c). The temporal sequence of the digital output signals of the digital bandstop filter, which therefore no longer contain an RDS signal component, are subsequently optionally increased in the output-side second part of the digital filter 1 by an interpolating procedure in their clock frequency to the original value f = n · f 1 (cf. Fig. 6d) before they are converted to an analog signal in the D / a converter 3, the analog in the subsequent reconstruction filter 5 is subjected to a further band limitation (see. Fig. 6e). The freed in this way from the old RDS data FM multiplex signal is then supplied to the summing circuit 6 via the input 12 is supplied to the phase-locked to said multiplex signal is also still on the input 13 of the new RDS data (from the RDS coder) will. The two signals combined in the summing element 6 to form the complete VHF multiplex signal are then passed via the switch 19 , which normally connects the output of the summing element 6 to the output 11 of the RDS band-stop filter, to the output 11 of the band-stop filter and from there to the VHF Sender sent. The phase-locked relationship between the output signals of the filter chain 1 , 3 , 5 and the new RDS data required for the synchronous insertion of the new RDS data is determined using the phase lock loop arrangement (PLL) 9 for the 19 kHz pilot tone realized. For this purpose, a 19 KHz reference signal is generated by means of the output signal of the filter chain in the PLL 9 , which is fed via the output 14 to the RDS coder (see FIG. 4) as a reference signal, so that the new RDS data is phase locked Can generate output signal of the filter chain.

The microprocessor 7 is provided as a central control for the A / D or D / A conversion as well as the digital filtering and the PLL.

The modulation signal must not fail due to interference on the filter. If the digital filter is therefore not working properly, a bypass circuit 17 , 18 , 19 can still be used to route a (then unprocessed) modulation signal to the transmitter so that the program does not fail. The bypass circuit can be activated by a command from outside, but also with internal error detection. The input 10 of the RDS band-stop filter is connected directly to the output 11 of the band-stop filter via the bypass line 17 and the switch 19 and at the same time the output of the summing element 6 is decoupled from the output 11 . The switch 19 is controlled via the control line 18 by the microprocessor 7 .

Nowadays, the invention enables the construction of a signal processing system which can process signal bandwidths of at least 80 KHz without further ado, is linear in phase and which can process the input signal in such a way that frequency bands of the input signal, the spacing of which from one another is around (7 * 10 ^-3 ) times that Signal bandwidth is, can be applied with its own filter functions, the frequency bands used after the processing are only slightly changed in amplitude and phase.

The filter according to the invention is used in the modulation path to an FM transmitter for the purpose of processing one Multiplex signal (e.g. for the purpose of exchanging RDS data), so high demands are placed on the filter function Phase linearity set, d. H. the phase must be in the frequency domain run so linearly that in the later Demultiplex the multiplex signal the individual channels can be separated without major loss of quality.

The filter has a transfer function in the Kind that one or more additional signals such. B. the old ones RDS data are attenuated in the amplitude so far that new and updated gaps in the resulting gap or gaps Additional signals such as B. the new RDS data  can be inserted without the remaining Residual signal disturbing the new signal.

The filter function is expediently of the type variable that from several previously defined Transfer functions switched to a filter function can be so that the treatment of individual signals is variable in the multiplex spectrum.

Claims (24)

1. Arrangement for processing signals in the modulation path to a transmitter, which arrangement contains a filter, characterized in that the filter is a digital filter ( 1 ). 2. Arrangement according to claim 1, characterized in that the digital filter ( 1 ) is inserted in the modulation path to an FM transmitter, in particular an FM transmitter, and is provided for processing multiplex signals, in particular for exchanging RDS signals. 3. Arrangement according to one of claims 1 to 2, characterized in that the digital filter ( 1 ) operates according to a filter function which is variable in the manner that one of these transfer functions selected from several previously defined transfer functions as a filter function and at least one later If necessary, the time can be switched to another of these transfer functions as a new filter function. 4. Arrangement according to claim 3, characterized in that the digital filter ( 1 ) has a transfer function as a filter function, according to which the filter as a digital bandstop filter attenuates one or more frequency-limited additional signals, in particular RDS signals, in the modulation path to the transmitter in their amplitude that new frequency-limited additional signals, in particular new RDS signals, can then be inserted into the resulting gap or gaps in the frequency spectrum without the remaining signal interfering with the new additional signal. 5. Arrangement according to one of claims 1 to 4, characterized in that the digital filter ( 1 ) is designed as a transversal filter with an input line (E, E₁-E _M ) for the digital signals of the first type (e _i ), with one several discrete adders (S₁-S _M or S₁-S _N-1 ) containing output line (A₁-A _M , A) for the digital output signals (a _i ) and with a total of N each the input line (E, E₁-E _M ) with the output line (A₁-A _M , A) connecting discrete multipliers (M₁-M _N ) and a total of N-1 buffers (τ₁-τ _N-1 ). 6. Arrangement according to claim 5, characterized in that the transversal filter is divided into M complete and cascaded transversal sub-filters (T₁, T₂ ... T _M or T₁ ', T₂' ... T _M '), by at M-1 locations in both the input line (E, E₁-E _M ) and in the output line (A₁-A _M ; A) an additional buffer (τ _e1 , τ _a1 ; τ _e2 , τ _a2;. . τ _{e (M-1)} , τ _{a (M-1)} ) is inserted. 7. Arrangement according to claim 6, characterized in that all M transversal partial filters (T₁, T₂ ... T _M or T₁ ', T₂'... T _M ' ) each have the same number K = N / M of multipliers (M₁-M₃; M₄-M₆;...; M _N-2 -M _N ). 8. Arrangement according to claim 6, characterized in that (M-1) the M transversal sub-filters each have the same number K ′ = (N-L) / (M-1) of multipliers and the remaining one of the M transversal sub-filters, in particular the first or the M-th transversal sub-filter, preferably the M-th transversal sub-filter, one of K ′ has different number L of multipliers with preferably L <K '. 9. Arrangement according to one of claims 5 to 8, characterized in that the transverse filter ( 1 ) or the transverse partial filter (T₁, T₂,... T _M or T₁, ', T₂',... T _M ′ ) with discrete multipliers (M₁-M _N ) and adders (S₁-S _M or S₁-S _N-1 ) is constructed. 10. Arrangement according to one of claims 5 to 9, characterized in that the N-1 buffer (τ₁-τ _N-1 ) either in the input line (E, E₁-E _M ) or in the output line (A₁-A _M , A) are arranged. 11. The arrangement according to claim 10, characterized in that the individual buffers (τ₁-τ _N-1 ) within the transversal filter or the individual transversal sub-filter (T₁, T₂ ... T _M or T₁ ', T₂'. . T _M ′ ) are each arranged between two successive multipliers (M₁, M₂; M₂, M₃; M₃, M₄;...; M _N-1 , M _N ). 12. Arrangement according to one of claims 5 to 11, characterized in that the buffer (τ₁-τ _N-1 ) and / or the additional buffer (τ _e1 -τ _{e (M-1)} ), τ _a1 -τ _{a ( M-1)} ) each realized by addressable and / or controllable memory units and that these memory units are connected via their addressing and / or control inputs to an addressing and / or control unit containing one or more address generators. 13. Arrangement according to claim 12, characterized in that a counter is provided as an address generator. 14. Arrangement according to claim 12, characterized in that the addressing and / or control unit with one or more programmable digital logic modules is. 15. The arrangement according to claim 14, characterized in that the logic module or logic modules via their control inputs are connected to a computer. 16. Arrangement according to one of claims 1 to 15, characterized in that the digital filter ( 1 ) on the input side is followed by a digital anti-aliasing filter upstream and / or on the output side a digital reconstruction filter. 17. The arrangement according to claim 16, characterized in that the digital anti-aliasing filter and / or the digital reconstruction filter from the structure (each) of the same filter type (are) as the digital filter ( 1 ) and together with the digital filter ( 1 ) forms a digital overall filter, which is preferably connected to the addressing and / or control unit. 18. Arrangement according to one of claims 1 to 17, characterized in that the digital filter ( 1 ) or digital overall filter on the input side an A / D converter ( 2 ) upstream and / or on the output side a D / A converter ( 3 ) is connected downstream. 19. The arrangement according to claim 18, characterized in that the A / D converter ( 2 ) on the input side an analog anti-aliasing filter ( 4 ) and / or the D / A converter ( 3 ) on the output side an analog reconstruction Filter ( 5 ) is connected downstream. 20. Arrangement according to one of claims 1 to 19, characterized in that the digital filter ( 1 ) (or the digital overall filter or the analog reconstruction filter ( 5 ) as the last filter of the series-connected filter ( 1 , 3 , 5 )) on the output side a summing element ( 6 ) with at least two inputs ( 12 , 13 ) is connected downstream, and that the one input ( 12 ) of these at least two inputs ( 12 , 13 ) of the summing element ( 6 ) with the output of the digital filter ( 1 ) (or of digital overall filter or the analog reconstruction filter ( 5 )) and each further input ( 13 ) of these at least two inputs ( 12 , 13 ) is provided for feeding in each case an external frequency-limited additional signal, which is connected to the upstream filter ( 1 , 3 , 5 ) fills the gap (s) created in the frequency spectrum. 21. Arrangement according to one of claims 1 to 20, characterized in that a further output ( 14 ) is provided for using a phase lock loop arrangement ( 9 ) from the output signal of the digital filter ( 1 ) or digital Overall filter (or the series-connected filter ( 1 , 3 , 5 )) obtained pilot signal, in particular a 19 kHz pilot signal for multiplex signals for an FM transmitter. 22. Arrangement according to one of claims 1 to 21, characterized in that a switchable via a switch ( 19 ) and directly connecting the input ( 10 ) of the arrangement with its output ( 11 ) and the output signal of the filter or filters ( 1 , 3 , 5 ) or the summing element ( 6 ) from the outlet ( 11 ) of the arrangement separating bypass line ( 17 ) is provided. 23. Arrangement according to one of claims 1 to 22, characterized in that for driving the digital filter ( 1 ) or digital overall filter and / or the A / D converter ( 2 ) and / or the D / A converter ( 3rd ) and / or the switch ( 19 ) and / or the phase lock loop arrangement ( 9 ) a microprocessor ( 7 ) is provided. 24. Arrangement according to one of claims 2 to 23, for the RDS ball reception, characterized in that

• - That an RDS coder is connected on the output side to one of the further inputs ( 13 ) of the summing element ( 6 ) and on the reference input side to the further output ( 14 ) for the 19 kHz pilot signal;
• - That the RDS encoder has a first and a second input and that the first input of the RDS encoder for feeding the old RDS data received by the ball receiver is connected to the output of an RDS decoder and the second input of the RDS encoder for Feeding of the new RDS data is provided;
• - That the RDS decoder is connected on the input side to the ball receiver.