DE4035087A1 - Switch system data processor coupled to bus - has interface controlling coded inputs to bus according to position of switch - Google Patents

Abstract

A data processing system (1) is coupled to a data bus (2) and a control bus (3) via a switching circuit (4) based upon electronically coded switches (5), a bus drive stage (6') and a signal generator (6"). A chip select (E3) is received by the drive stage to gate the inputs from the switches. The signal generator is based around EXCLUSIVE-OR logic (10, 12, 1,4,15) and generates an output to a controller (7) that signals the bus system. ADVANTAGE - Simplifies comunication with data bus.

Description

The invention relates to a switch arrangement for coded Signals.

With data processing systems, it is often desirable to Issue commands with a simple switch operation to be able to. This applies, for example, to switch-on commands or the like. With which data processing is carried out on a data bus connected subsystems activated or inactive to be fourth.

So far, however, no switch arrangements have been offered, which can easily be found in the data processing bus have systems integrated.

It is therefore an object of the invention to provide an appropriate arrangement to create solutions.  

This object is achieved in that a manually operated switch on the output side with inputs an assigned interface is connected, the output on the data bus of a data processing system can be connected to the data processing address bus system can be connected to the selection input and only if you receive one via the selection input callable data according to the respective position of the switch to the data bus.

The invention is based on the general idea of a arbitrarily operated switch with a cut deliver gate to the data processing system provided which is independent of the switch actuation is controllable by the data processing system and the signals generated by switch actuation in a for the data processing system adapted form only a corresponding call into the data bus.

The switch arrangement according to the invention can thus be used directly be integrated into the data processing system.

To the electronic effort for the interface as possible keeping it low is in accordance with an expedient embodiment the invention provided that the switch as a coded Switch is formed and accordingly at the outputs a coded signal can be tapped directly from the switch which is fundamentally from the data processing system can be processed without prior implementation.

Finally, the interface can add one more Have an exit at which an - preferably for a limited time tes - signal can be tapped as soon as the switch is actuated  has been. This output of the interface can be used with the entrance of a controller system of data processing connect the plant, which then ensures that the interface of the arbitrarily operated switch receives a call, the signals generated by the switch feed into the data bus.

Otherwise, with regard to preferred features Claims and the following description of an advantage stick embodiment referred to the drawing is explained.

The only figure shows a section of data processing system to which the circuit according to the invention arrangement is connected.

A data processing system 1 shown only in sections has a data bus 2 and an address bus 3 . Via the data bus 2 , data between processing systems 1 of the data processing system 1 , for example between transmitters and receivers, are exchanged in a generally known manner. The address bus 3 is used for control commands with which the systems of the data processing system are activated for the delivery or reception of data. In this way it is ensured that the data delivered by a system actually reach the desired system via the data bus 2 .

On the data bus 2 , the switch arrangement 4 according to the invention is connected, which essentially consists of a contact-based or electronically coded switch 5 , which can be actuated arbitrarily, and an interface 6 , which in turn essentially consists of a bus driver 6 'and optionally also an additional one Signal generator 6 '' exists.

The bus driver 6 'with the outputs of the switch 5 has inputs connected to E ₅ and an address bus connected to the input E 3. ₃ On the output side, the bus driver 6 'is connected to the data bus 2 via outputs A ₂ .

As soon as the bus driver 6 'receives a corresponding call command ("chip select") via the address bus 3 or the input E ₃ connected to it, it routes the signals present at its inputs E ₅ - possibly after a signal conversion to adapt to the data processing system 1 - to the data bus 2 . As long as there is no such call command, the inputs E _{5 of} the bus driver 6 'are separated from its outputs A _{2 with} high impedance.

The call command can be generated at regular time intervals by an operating control system (not shown) of the data processing system. In this way, the position of the switch 5 is queried regularly. Switch 5 is also queried here if it has not been switched over in the meantime.

To ensure optionally a demand query of the switch 5, ie, in order to achieve that the switch 5 is interrogated only after an actuation, the interface 6 may be the signal generator 6 '' comprise, which in Illustrated below in each case a short signal ( "Strobe") emits when the switch 5 has been operated. This signal is the signal generator 6 '' a controller system 7 of the data processing system 1 is supplied from the output of A _7, both data from the data bus 2 has received and can be fed into the data bus 2 and on the one hand via the address bus 3 call instructions obtained and on the other hand Call commands for other system parts can be sent via the address bus 3 .

As soon as the controller system 7 has been "informed" that the switch 5 has been actuated, it will - if necessary after data exchange with other systems - issue a call command to the bus driver 6 'via the address bus 3 , so that this data feeds into data bus 2 in accordance with the signals generated by switch 5 .

The signal generator 6 'is connected on the input side to a switch-side output, which actuation with each switch either to a first voltage level, for. B. "High" is switched on or off.

The input line 8 of the signal generator 6 '' is constantly connected via a first resistor 9 to a connection for a second voltage level, in the case shown for the "zero" level. Otherwise, the input line 8 is connected directly to the one input of an exclusive OR gate 10 and via a further resistor 11 to the one input of a further exclusive OR gate 12 , the latter input having a capacitor 13 with a relatively large capacitance the second voltage level (in the example shown the "zero" level) leading connection is connected. The other input of exclusive-OR gate 12 is constantly the second voltage level is applied, while the other input of exclusive-OR gate 10 is from the first voltage level, respectively, in Darge presented example, the "High" level applied.

The outputs of the exclusive OR gates 10 and 12 lead to the inputs of a further exclusive OR gate 14 , which is connected on the output side to the one input of an exclusive OR gate 15 , the other input of which via a switch 16 either with one or the other other voltage level is applied. The output of the last-mentioned exclusive OR gate 15 forms the output A _{7 of} the signal generator 6 ''.

If the switch 5 has not been operated for a long time, the inputs of the exclusive OR elements 10 and 12 connected to the input line 8 always have the same voltage level, e.g. B. the "zero" level or the "high" level. The result of this is that the outputs of the two exclusive OR gates 10 and 12 have different levels, ie one output is at the "zero" level and the other output is at the "high" level. As soon as the switch 5 is actuated, the level in the input line 8 changes , the changed level on the exclusive OR gate 10 being present immediately, while the change in the level in the line branch 8 'occurs with a delay because first the capacitor 13 via the Resistor 11 must be reloaded. As a result, the outputs of the exclusive OR gates 10 and 12 have the same level during the delay time.

Accordingly, a pulse-shaped (time-limited) level change occurs in the output line A ₇ during the delay time, which level change is evaluated by the controller system 7 as a signal for actuation of the switch 5 .

The exclusive OR gate 15 , together with the changeover switch 16, only serves to adapt the signal passed via the output line A ₇ to the controller system 7 . Depending on the setting of the switch 16 , the signal sent during the delay time leads to one or the other level.

In the example shown in the drawing, the interface 6 works as a parallel interface with parallel outputs A ₂ , because the data processing system 1 is suitable for a corresponding de parallel processing of signals.

Basically, the invention can also be used in data processing systems with serial data processing or data transmission. In this case, the interface 6 must work in series. This means that the interface 6 must usually also include a memory, which initially receives the signals generated by the switch 5 for later serial transmission.

Claims (5)

1. Switch arrangement for coded signals, characterized in that a manually operable switch ( 5 ) is connected on the output side to inputs (E ₅ ) of an associated interface ( 6 ) which can be connected on the output side to the data bus ( 2 ) of a data processing system ( 1 ) , approximately input a connectable to the address bus (3) the data processing system (1) Selektie (e ₃₎ has, only on receipt of a zuleitbaren over the Selektierungseingang (e ₃₎ call data corresponding to the respective position of the switch (5) to the data bus (2 ). 2. Switch arrangement according to claim 1, characterized in that the switch ( 5 ) is designed as a coded switch. 3. Switch arrangement according to one of claims 1 or 2, characterized in that the interface ( 6 ) essentially works as a bus driver ( 6 '), which blocks the coded signals of the switch ( 5 ) with respect to the data bus ( 2 ) with high impedance, up to the selection input (E ₃ ) is called for data transfer. 4. Switch arrangement according to one of claims 1 to 3, characterized in that the interface ( 6 ) has an output (A ₇ ) which with an input of a data bus ( 2 ) and the address bus ( 3 ) assigned controller system ( 7th ) is connectable and emits a signal - preferably for a limited time - when the switch ( 5 ) is actuated. 5. Switch arrangement according to one of claims 1 to 4, characterized in that the switch ( 5 ) and the interface ( 6 ) together form a prefabricated module or a prefabricated unit.