DE4025295C2 - Computer for playing video data on a monitor - Google Patents

Description

The invention relates to a computer system a CPU, a RAM and a monitor drive circuit the preamble of claim 1.

Today's personal computers (PCs) based on microprocessors are widely used in the fields of education, science, business and home. Increased with the proliferation of personal computers the need for faster and more flexible video Features. Accordingly, computer manufacturers are on the Find ways to increase performance and attractiveness fit of video display systems with reduction the cost to the consumer.

Generally, the internal architecture of the personal computer ters organized in such a way that the central processing unit (CPU) a printed circuit board, which is also arranged system memory and supporting logic devices holds. This card is commonly called the "mother card" or "Motherboard" called. If the user in previous Time video graphics features he had more needed wise to buy a separate video or graphics card that into a with the mother card via a connecting businter face plugged slot had to be inserted. This Card contains dual port video random access memory (VRAMs), which are used to store video display data which are connected to the data display device (i.e. a moni gate) will be issued at a later date. The Vi deokarte also has its video timing circuit, the is configured for a specific type of monitor. This be indicates that the card can only be used with the monitor type, and no other, for which it is configured has been. This earlier solution was for machines like the original original Macintosh II computer typical and finds too still widely used today. The use of a sepa guessing video card has some major drawbacks,  perhaps the most important of which is that the Be either use a different video card for each type of Da Visual display or monitor to which the computer is connected is needed or the system in any way at a Monitor change must be reconfigured (e.g. by Um switch different selection switches). So needed at for example, a computer that is used to generate an image a 15-inch portrait color monitor is used, a kind of video card while one with a 9 inch black and white Screen coupled computer needs another card. the accordingly, different monitors are used adapted video cards required, which ultimately the flexibility of the overall arrangement ent for the user decrease by a large margin.

EP 0 303 138 A2 describes a method and a device device for connecting several monitors to one adapter scarf tion of a computer known. Ver different monitor types can be coupled. However, this is the manual setting provided on the adapter board necessary switches.

From the publication EP 0 326 275 A2 is a Compu tersystem known, to which various monitor types are coupled can be pelt. The computer system has a built-in display adapter, which is only for a Moni door type is configured. In addition, the system can have another display adapter that for another Mo can be configured. When asked to do this System the built-in adapter to determine whether the is of the EGA type. If this is the case, the in internal adapter operated in EGA mode. If not the If so, the internal adapter is operated in CGA mode and the type of the optional adapter is queried. No the control devices or adapters used can be however configure for multiple monitor types.

From German published patent application DE 37 22 169 a method and a circuit arrangement for adapting a  Multi-mode monitor to a PC known. These described monitor control circuit is configurable, while in the company simply on another Personalcom computer can be switched. This is possible because of the Control circuit from the computer interface evaluates outgoing horizontal and vertical synchronizing signals and the monitor in one of these coming from the computer Controlled signals compatible way.

The object of the invention is to provide a computer system To provide, to which a monitor can be coupled can be one of a group of different moni gate type selected monitor type, so that various whose monitor types are used with the same computer can, without it being an operator Position or reconfiguration of the monitor control circuit of the computer.

This task is accomplished according to the invention by a computer system stem solved with the features of claim 1.

The invention provides a preferred embodiment the use of a self-configuring monitor control circuit first, the type of monitor used identified and then according to the Moni used door type one of a plurality of parameter sets elects. These parameters are then the rest of the display circuit provided. The invention enables therefore the connection of different monitors without the Vi deo circuit must be replaced in whole or in part. For the This makes it much easier for users to handle since it no exchanging cards, pressing switches or that Computer system needs to reconfigure when monitors ge be changed.

The computer according to the invention has a self-configuration rende video circuit, the connection of different Moni Gate types allowed. The computer automatically detects the one sent to it connected monitor type and then configures its internal  Circuit to send compatible video signals to the monitor to deliver.

In one embodiment of the invention, the Computer a central processing unit (CPU), which a Videoda program for playback on the monitor performs. The data stored in the computer is stored in a random access memory (RAM). The display delivers an identification signal to the video circuit, which then both the correct video clock signals as also generated the video data for display on the monitor. The identification signal is used to configure the Vi deo switching according to the requirements of the monitor.

Advantageous embodiments of the invention are in the Subclaims marked. The following is the inven dung based on a schematically shown in the drawing Embodiment explained in more detail. Zei in the drawing gene:

Figure 1 is a generalized block diagram of the computer system according to the invention.

Fig. 2 is a more detailed block diagram of a preferred embodiment of the invention;

Fig. 3 different timing video signals and their associated to video timing parameters;

Fig. 4 shows the video timing waveforms for a memory cycle in which video data is transferred from system RAM to the video circuit FIFO of the video circuit;

5a shows a bit order (bit order) of the video data in the shift register and the taps for one-bit-per-pixel video.

Fig 5b, the bit order of video data in Schieberegi art and the taps, which are used in two-bit-per-pixel video.

Figure 5c shows the bit order of video data in the shift register and the taps used for four bit per pixel video;

Figure 5d shows the bit order of video data in the shift register and the taps used for eight bit per pixel video; and

Fig. 6 shows the time relationship between the video timing signals and the video reset signal, which initiates the start of a live video frame.

A computer is described with a self-configuring one Video circuit for connecting different video display moni Gates. The following description describes numerous specific ones Details such as clock frequencies, register sizes, bit names tion etc. specified to make the invention easier to understand do. However, it will be apparent to those skilled in the art that the invention can also be realized without these special details. In other cases, known circuits are only in the form of Circuit blocks specified to describe the invention not burdened with unnecessary details.  

Although the invention is based on its preferred Embodiment described in the Macintosh IIci computer it will be clear to those skilled in the art that the invention also can be realized in other computers and that numerous Modifications are possible within the scope of the inventive concept.

Referring now to Fig. 1, there is shown a generalized block diagram of the preferred embodiment of the invention. The computer system 10 has a RAM base video unit (RBV) 14 , which generates video display signals for various display monitors. RBV 14 contains two basic components: a video component that provides sync signals and data for different monitor types (in the example described, the RBV circuit supports four different monitor types), and a part that emulates a multiple interface adapter (VIA).

The VIA section contains a variety of 8-bit registers for controlling mixed inputs and outputs, video control, RBV chip test operations and interrupt processing. The CPU 13 is connected to these registers via an 8-bit bidirectional data bus which is separate from the 32-bit RAM data bus used by the video part. This enables access to the registers that is independent of the activity of the video part on the separate RAM data bus. For the most part, the VIA part of the RBV is irrelevant for understanding the present invention. Therefore, the explanation of the VIA part is limited to those elements which are useful for explaining the present invention.

The RBV unit 14 is preferably manufactured as an integrated circuit (IC) using the MOS method. In particular, CMOS technology is used.

RBV 14 works with a memory decoding unit (MDU) 12 and a random access memory (RAM) 11 . MDU 12 acts as a memory control device and decides on access to RAM 11 from RBV 14 . MDU 12 is designed to provide a compatible interface between CPU 13 , RAM 11 , ROM 47 and I / O devices (input / output devices) 45 (see Fig. 2). In the preferred embodiment, the CPU 13 is an MC68030 microprocessor from Motorola Corporation.

RAM 11 has at least one dynamic memory bank (DRAM) and is coupled to RBV 14 via a 32-bit bus line 21 . Before RAM 11 preferably has two separate RAM banks, which are controlled directly by the MDU 12 . MDU 12 is coupled to RAM 11 via a control line 52 . RBV 14 and MDU 12 are connected via lines 22-25 . As will be discussed further below, the initial access to video data stored in RAM 11 is five CPU clocks, followed by a two clock burst access. Internally, the MDU 12 includes a state machine and an address multiplexer associated with the control of bank A of the RAM 11 in connection with video request signals provided by the RBV 14 .

The frequency for the point clock generation is supplied by three separate frequency sources 18-20 . Each of these sources represents a quartz oscillator circuit which operates at a characteristic frequency. The frequency sources 18-20 are coupled to the RAM base video unit 14 via lines 37-39 . The use of multifrequency reference inputs is a way in which the computer according to the invention adapts the different types of monitors. Although three frequency sources are shown, much more can be used within the scope of the inventive concept. Alternatively, a single programmable or adjustable clock source can be used instead of separate frequency sources 18-20 .

RBV 14 provides video data to a video digital to analog converter (VDAC) 26 via a bus 29 . VDAC 26 has a color look-up table (CLUT) and a DAC which, in the exemplary embodiment described, is designed as a Bt478 device from Brooktree Corporation. VDAC 26 also receives point clock, composite dark control (CBLANK) and composite video sync (CSYNC) signals from RBV 14 over lines 30 , 31 and 33 , respectively. These signals change according to the type of monitor used and are used to organize the video timing of the data on the screen. VDAC 26 supplies analog red, green and blue (RGB) color video signals to monitor 27 via line 36 . Monitor 27 may also receive horizontal sync (HSYNC) and vertical sync (VSYNC) video timing signals, or a composite sync (CSYNC) signal from RBV 14 . A monitor identification (ID) signal is applied to the RBV 14 by the monitor 27 via a line 35 .

As mentioned above, four different display monitor types are supported by the described embodiment of the invention. One of these monitors is controlled directly by the RBV 14 , while the others are controlled or driven via VDAC 26 . Each type of monitor identifies itself by putting certain pins on the RBV to ground. As a result, the correct pixel clock and sync timing parameters are automatically selected. The four monitor types that are supported by the described embodiment of the invention are a 9 "Macintosh SE (Mac SE), a modified Apple II-GS monitor, a Macintosh II 12 " B / W and 13 "RGB monitor a 15 "portrait monitor (B / W or RGB).

Table 1 summarizes the monitors selected via the 3-bit monitor ID pins on line 35 . It should be noted that a separate pin is provided on the RBV chip (not shown in FIG. 1) which drives or drives a built-in 9-inch SE monitor.

TABLE 1

In the following reference is made to FIG. 2, in which a detailed block diagram of the RBV chip 14 together with the connections to the computer mother card 40 is shown. The CPU 13 is coupled to various devices such as a ROM 47 , I / O devices 45 , NUBUS 46 and VDAC 26 via a CPU data bus 50 and CPU address bus 65 . System memory is shown as two RAM banks, Bank A ( 43 ) and Bank B ( 42 ). Bank B RAM ( 42 ) is directly coupled to the CPU data bus 50 , while a bus buffer 44 separates the CPU data bus 50 from the Bank A RAM data bus 21 . In the described embodiment, bus buffer 44 is a commercially available 74F245 bus buffer.

RBV 14 is functionally equivalent to a separate video card, but is integrated as an integrated circuit in the mother card or main board. In order to achieve this function, bank A of the system RAM can be selectively decoupled from the CPU data bus 50 by means of the bus buffer 44 . This enables sole access to bank A by RBV 14 via bank A RAM bus 21 . Data stored in bank 43 of the system RAM is used by the RBV to apply a constant video data stream to the display monitor 27 during the running (live) video section of each horizontal scan line. RBV 14 asks MDU 12 for data while it is needed; MDU 12 responds by disconnecting bus 21 from CPU data bus 50 and performing an 8-long word page mode burst read operation from RAM bank A 43 into FIFO 54 located within RBV 14 . Banks 43 and 42 are controlled by the MDU 12 via the RAM control bus 52 .

When a video burst occurs, CPU access to bank 43 is delayed, effectively slowing CPU 13 . This effect changes depending on the monitor size and the number of bits per pixel. It should be noted that only access to RAM bank A is affected by video. RAM bank B connects the CPU data bus 50 directly, so that CPU 13 has unlimited access to this bank as well as to ROM 47 and I / O devices 45 at all times. It will be appreciated that the invention can be implemented without bank 42 or with additional RAM banks on either side of bus buffer 44 . Although the invention would work properly without bank 42 , the inclusion of bank 42 contributes to the overall efficiency and performance of the computer system by providing part of the memory available to CPU 13 .

The video part of RBV 14 contains a 16 × 32 bit FIFO (silo) storage unit 54 , which also has a logic that keeps the FIFO filled with RAM data and logic that serves for data arrangement and output. RBV 14 also includes a latch 53 , which is used to hide data on bus 21 into FIFO 54 via a load pointer line 55 . Video data is unloaded from a FIFO 54 via a line 46 coupled to a bit sequence folder 57 . The folder 57 is in turn coupled to a shift register 59 via a line 58 . The shift register 59 shifts the video data arranged by the bit sequence folder 57 onto the video data bus 29 . A tap selector 60 connecting register 59 to bus 29 is described below.

Video FIFO 54 is divided into two halves, each containing eight 32-bit words. When the last data has been used in a FIFO half (or three long words beforehand for a 13 inch monitor at eight bits per pixel or for a 15 inch monitor at four bits per pixel), RBV 14 lowers its data request output line 24 (VID.REQ). This video request line instructs MDU 12 to separate Bank A RAM data bus 21 from CPU data bus 50 by activating bus buffer 44 . It also initiates a page mode burst read operation of RAM data on bus 21 as soon as possible. MDU 12 then hides valid RAM data in RBV 14 using the video data load input line 23 (VID.LD) of the RBV. The video load input line 23 controls latch 53 .

Each trailing edge of a VID.LD pulse stores a 32-bit long word of RAM data in latch 53 , stores the buffered data in FIFO 54 and advances the input pointer to the next position in the FIFO. Data is input into the video FIFO 54 via a line 55 starting from the control latch 53 . After the trailing edge of the sixth VID.LD pulse, the RBV raises its video data request line (VID.REQ) 24 . If VID.REQ is high before the trailing edge of the seventeenth VID.LD pulse, MDU 12 ends the burst after reading one or more long words (the eighth) and fades it out to the RBV. This fills the previously empty half of the FIFO.

Meanwhile, the other eight long words of data in the other half of the FIFO (which were loaded during the previous burst read operation) can be loaded into shift register 59 via bus 58 in 16-bit groups. After loading the eight long words from the second half of FIFO 54 (ie the second half is empty), the next eight long words from the first half of the FIFO (which has previously been loaded with video data) are shifted into shift register 59 loaded. During this time, the second half of FIFO 54 (emptied during the last load sequence) now receives updated video data from RAM bank A. The second half is filled, as described above, and the whole process repeats itself - the two halves of FIFO 54 alternately receive data from RAM 43 and load data into shift register 59 .

Shift register 59 has eight output taps coupled to tap selector 60 . The data is shifted bit by bit by the shift register 59 from the point clock signal appearing on line 30 . The eight output taps are arranged along the shift register at alternating bits (ie every other bit). By using one, two, four or all eight taps, the data can each be bit-by-bit (one-bit video), two bits simultaneously (two-bit video), four bits simultaneously (four-bit video ) or eight bits appear at the same time (eight-bit video).

In order for the data to appear at the output taps in the correct order, the sixteen bits must have been loaded into the shift register 59 in the correct order for the number of bits per selected pixel. This function is performed by the bit order folder 57 , which receives the words from the FIFO 54 via the line 56 and also the bit-per-pixel information via the line 89 . For one-bit-per-pixel video, only the last output tap is used, and all sixteen bits in the shift register appear on that tap after sixteen on consecutive dot clocks.

Conversely, for eight bit video, all eight taps are used and the sixteen bits are sent to the eight output lines of the video data bus 29 after only two dot clocks. In any event, the next sixteen bits are loaded into the shift register 59 from the FIFO 54 , and the FIFO's output pointer is advanced when all sixteen bits have been output to the video data bus 29 . This may empty half of the FIFO. The empty half of the FIFO 54 must then be filled with another 8-long word burst of RAM data in the manner described above.

In the following reference is made to FIGS . 5a to 5d, in which bit orders or orders within the shift register 59 are shown for one bit, two bits, four bits and eight bits per pixel. As can be clearly seen, the bit order for one-bit-per-pixel video begins at 0 and continues sequentially to bit 15 , which is located at tap 0. Therefore, in the case of one-bit video, the data on one of the eight lines in the output data bus 29 are sequentially loaded or advanced. The other seven lines on the bus are driven high.

In two-bit video, the odd bits are in the left half of the shift register (ie, odd bits 1-15 ), ending at handle 1 (arranged), while the evenly numbered bits (ie even bits 0-14) are in the right Half of the shift register, ending at tap 0, are loaded. Here too, the output data bus lines, which are connected to the unused tap, are driven to a high level.

With four-bit video, the bit order is even more involved. As shown, the bit order is such that bits 12, 8, 4 and 0 on tap 0, bits 14 , 10 , 6 and 2 on tap 2 , bits 13 , 9 , 5 and 1 on tap 1 and bits 15 , 11 , 7 and 3 are pushed out in this order on tap 3 .

For eight bit video, all eight taps are used in the following manner: tap 0 shifts bits 8 and 0, tap 1 bits 9 and 1 , tap 2 bits 10 and 2 , tap 3 bits 11 and 3 , tap 4 bits 12 and 4 , tap 5 bits 13 and 5 , tap 6 bits 14 and 6 and tap 7 shift bits 15 and 7 in this order. With eight-bit video, all sixteen bits are shifted out after two dot clock periods.

Each of the taps shown in Figures 5a to 5d is coupled to the data output bus 29 (e.g. VID.OUT) via the tap selector 60 such that the most significant bit VID.OUT7 and the least significant bit VID.OUT0 speaks accordingly. For example, for eight-bit video, each long word is shifted in such a way that bit 31 on VID.OUT7 appears at the same time as bit 30 on VID.OUT 6 , bit 29 on VID.OUT5, bit 28 on VID.OUT4, Bit 27 on VID.OUT3, bit 26 on VID.OUT2, bit 25 on VID.OUT1 and bit 24 on VID.OUT0 etc. One-bit video appears high on the output pin VID.OUT0 during pins VID.OUT1-7 be held (they appear as ones). Each long word from RAM is shifted to VID-OUT0, starting with bit 31 and continuing directly with bit 0, while the monitor beam runs from left to right.

As shown in FIG. 2, tap selector 60 is connected to line 89 and receives the number of bits per pixel to be output on video data bus 29 . Once on each video frame (at the end of the vertical synchronization pulse, RBG 40 lowers its video reset (VID.RES) output line 25 to reset the MDU's video address counter. Then the RBV gives two 8-long- immediately before the first line of live video. Word requests so that they start fully with video FIFO 54. The process then continues in the manner described above - with words being pushed out at the same time that new data words are inserted.

RBV 14 lowers the potential on its VID.REC line 24 when it is ready to receive eight long words of input data from RAM 43 . From then on, it waits for the memory controller 12 to hide data entry. Data is faded in by the memory controller 12 using the VID.LD line 23 . The RBV waits for an undefined time for the video data to arrive (although it may start pushing old data out of the FIFO if it has to wait long enough). It records any number of long words, although this data may begin to overwrite data that has not yet been pushed out if too many long words are displayed.

After the sixth VID.LD strobe, RBV 14 lifts VID.REQ line 24 . This takes place even if the next request after eight long words is already pending. If the VID.REQ line 24 has been raised before the end of the seventh VID.LD strobe, the MDU 12 fades out another long word (the eighth) into the RBV unit and then waits for the next VID.REQ - Signal (which can occur at any time after the end of the seventh VID.LD strobe).

The RBV unit 14 contains no information regarding the screen image or video addresses. It simply assumes that it receives the correct data, usually in 8-long-word groups (8-long-word groups) on request from the memory control unit. At the end of each vertical synchronization pulse, the RBV 14 lowers its VID.RES line 25 for the period between two horizontal synchronization pulses. Controller 12 uses this signal to reset its video address counter back to the beginning of the frame buffer.

Similarly, memory controller 12 knows nothing about the video circuit or its parameters. If it detects that the VID.REQ line is dropping, it waits for a running bank A RAM cycle to complete. It then instructs the RAM bus buffers to go into tri-state mode, thereby disconnecting bus 21 from CPU data bus 50 . Next, a page mode burst read operation of the RAM begins.

It should be noted that only three wires (VID.REQ, VID.LD and VID.RES) are required for the interaction between MDU 12 and RBV 14 . RBV 14 does not need to store any information regarding the memory or the MDU. Similarly, MDU 12 does not need to know anything about video. Each unit simply communicates with the other according to the 3-wire handshaking (receipt) scheme described above. This considerably simplifies the system design and the internal architecture of both the MDU and the RBV unit. System flexibility is also improved. The RBV could be replaced with another video or DMA-out-of-RAM device without affecting the MDU, or the memory addresses and organizations could be changed without affecting the RBV as long as the handshaking or acknowledgment scheme is maintained.

MDU 12 signals each long word of the burst read operation by lowering its VID.LD line via a CPU clock period. It continues the page mode burst indefinitely - only stops a read operation upon detection of the return of VID.REQ line 24 to a high state. The addresses provided by the MDU 12 for the video burst read operations begin with address $ 0000 0000 and increment by one long word for each VID.LD. This continues indefinitely (using a 24-bit counter within the memory controller) until MDU 12 detects a drop on VID.RES line 25 . When VID.RES (video reset) is pulled low, the counter within MDU 12 is reset to $ 0000 0000.

Referring now to Fig. 4, there is shown a timing diagram showing the interaction between the RBV unit and the MDU RAM controller. The transition 101 on the VID.REQ line begins the process of video data transfer from RAM 43 to FIFO 54 . If RAM 43 is engaged in a current RAM cycle with CPU 13 , MDU 12 waits for that RAM cycle to complete before instructing bus buffer 44 to tri-state.

A new CPU-RAM cycle begins in the exemplary embodiment shown at time 102 . However, since the VID.REQ line 24 has changed to the low state, the CPU cycle is prevented from the 8-long word video burst by over twenty clocks. The start of the video reading cycle begins at time 103 . A minimum of five clocks after the falling transition of the VID.REQ line begins to display the video data stored in RAM bank A in FIFO 54 . The first long word of video data is loaded on the rising edge 104 of the VID.LD signal. If the VID.REQ transitions are high at 105, the next positive transition from VID.LD will alert the MDU to provide another video data word. The last video data word is loaded at transition 106 in the example shown.

The end of the video burst read cycle occurs at time 107 . Thereafter, the retained CPU RAM cycle begins at time 106 . It should be noted that a new video request can be initiated immediately after MDU 12 determines that VID.REQ has been brought up by VID.LD on the next positive transition. This is shown in FIG. 4 by the dashed transition 109 .

As stated above, video shift register 59 is sixteen bits long and is tapped every two bit positions. All taps are used for eight bit video and each of the sixteen data bits appears on one tap after two pixel clocks. If no new data is loaded, fourteen additional pixel clocks are necessary before ones are pushed out from the last tap. (Ones are inserted in replacement of the old, shifted out data bits).

At the beginning of the horizontal blanking, the video shift register has completed a shift operation so that all sixteen data bits on one of the taps used are in the form of sixteen 1-bit pixels, eight 2-bit pixels, four 4-bit pixels or two 8-bit pixels appear. Horizontal blanking prevents new data from being loaded into the shift register. The shift register, which is clocked by the point clock and therefore always carries out shift operations, continues to shift out old data until it is completely filled with ones. RBV 14 continues to transmit old data on fourteen pixel clocks in 8-bit operation, twelve pixel clocks in 4-bit operation, eight pixel clocks in 2-bit operation or zero pixel clocks in 1-bit operation. Afterwards, the slide register shifts all ones until it is loaded again with new data. Since the Macintosh SE uses only one-bit video, there is no old data to push out after blanking begins. On other computers, the composite blanking signal (CBLANK) provided on line 61 ( FIG. 2) and input to VDAC 26 prevents old data from appearing on the screen.

A vertical blanking takes place after the beginning of the horizontal blanking and after loading the FIFO 54 with a further 8-long word burst of data from the bank 43 . These 8-length words are never loaded into the shift register 59 , which (after the old data still in it is shifted out) continues to shift ones during vertical blanking. Quite early in the vertical blanking sequence, all pointers are reset and VID.RES is lowered, which resets the MDU's video address counter. Thereafter, approximately two lines before the end of vertical blanking FIFO 54 is loaded with sixteen long words of new data which replace preloaded data in preparation for the start of live video.

The video synchronization signals (including HSYNC, VSYNC, CSYNC and CBLANK) are generated by the video counter unit 69 . The video counter unit 69 has a series of programmable counters of a type known in the art in connection with the use for generating video timing signals. The video counters of unit 69 are self-configuring in the sense that the video counter unit 69 can provide the correct timing signals for the associated display or monitor once it has been provided with the monitor type and the bits per pixel requirements.

Referring now to Fig. 3, horizontal and vertical timing waveforms are shown showing the relationship between horizontal blanking, live video, horizontal synchronization, vertical blanking, lines of vertical live video, and vertical synchronization signals. As is well known, each of the parameters associated with horizontal and vertical timing depends on the type of display or monitor being used.

Monitors supported by this video system provide the identification (ID) of their type via a digital code that is present on a set of external lines or pins. In the described embodiment, the ID pins of a monitor 27 are coupled to a monitor parameter register 71 via a 3-bit line 35 . The monitor type is transmitted via a line 87 to the video counter unit 69 and to a MUX 88 . Bit-per-pixel information is applied via a line 89 from register 71 to unit 89 and folder 57 .

Software can read the monitor type in register 71 and can also read or write the number of bits per pixel in the same register. Decoding the 3-bit monitor ID type selects one of four fixed parameter sets, one set for each supported monitor. These parameter sets are "hard-wired" on the chip and deliver signals HSYNC, VSYNC etc. The only programmable parameter is the parameter for bits-per-pixel.

In an alternative embodiment, register 71 or its equivalent may be fully programmable. This would give the system the ability to set a large number of display parameters, the only limitation being the size of register 71 's internal storage volume. In this case, the monitor ID bits would be decoded by software, which would then write into register 71 , namely with the delivery of all correct parameters for the associated display.

The following table summarizes the relevant timing parameters provided by the RDV (shown in Fig. 3) for the four types of nitor that are supported by the described exemplary embodiment of the invention.

TABLE 2

Referring to Fig. 6 shows the relative timing of the various synchronization signals is shown together with the VID.RES- reset signal. As seen in FIG. 6, video counter unit 69 lowers VID.RES line 25 to reset the address counter of memory controller 12 between the last two horizontal sync pulse periods in VSYNC. This takes place at transition 110 in FIG. 6. VID.RES is reset to a high value simultaneously with the low-to-high transition of the VSYNC signal. Then, just before the first line of live video RBV 14, there are two 8-long word requests so that it can start the frame with a full FIFO.

As stated above, the monitor 27 provides a 3-bit identification code to the monitor parameter register 71 via the bus line 35 . RBV 14 then selects the correct video timing and synchronization parameters for the video counter unit 69 . Bit-per-pixel information is also provided on line 89 to bit folder 57 and video counter unit 69 . The unit 69 has a plurality of polynomial counters of a type known in the prior art. Using the de-coded monitor type, the RBV sets these counters so that they generate video timing signals according to Table 2 for the associated monitor.

Monitor type information is applied on line 87 to multiplexer 88 . Depending on the type of monitor connected to the computer system, multiplexer 88 selects one of the three point clocks, which are derived either from oscillator 18 , 19 or, after being divided in two, from the clock of oscillator 20 (corresponding to frequencies 30.2400; 57.2832 and 15 respectively , 6672 MHz). The halved clock from the oscillator 20 is applied to the multiplexer 88 via a line 41 .

If the monitor identification code identifies the monitor 27 as a modified Apple II-GS RGB display, for example, MUX 88 selects the corresponding clock signal on line 41 (ie 15.6672 MHz) as the point clock, which is on line 30 to the VDAC 26 Shift register 59 and the video counter unit 69 should be created. (Clock generator 66 is used to halve the reference frequency 20 that appears on line 39 , to generate the correct point clock frequency on line 41. Clock generator 66 also provides the input / output (I / O) clock output for I / O devices 45. )

On the other hand, if the display identification indicates that the display is a 12-inch B / W or 13-inch RGB MAC II, the frequency reference block 18 (ie 30.2400 MHz) on line 37 is selected by the MUX 88 . If the 15-inch portrait monitor were used, MUX 88 would select frequency reference 19 (ie 57.2832 MHz) on line 38 .

Table 3 summarizes the video signals for the various monitors together.  

TABLE 3

It should be noted that a larger number of monitors is simple by expanding the number of frequency sources and / or The size of the associated registers and lines can be adjusted.  

Various modifications are within the scope of the inventive concept possible. For example, as an alternative to Hardwiring a number of each parameter set barer registers are used, the use of software for setting each of the parameters assigned to each monitor type enable.

Claims (7)

1. Computer system ( 10 ) with a CPU ( 13 ), a RAM ( 11 ) and a monitor control circuit ( 14 , 26 ),
wherein a monitor ( 27 ) for displaying video data can be coupled to the monitor drive circuit ( 14 , 26 ), the monitor ( 27 ) belonging to a group of monitors of different monitor types, each monitor type being assigned a set of monitor display parameters, the set of monitor display parameters specifies the type of control of the coupled monitor ( 27 ) by the monitor control circuit ( 14 , 26 ),
wherein the monitor drive circuit ( 14 , 26 ) has a video timing circuit for generating video timing signals (CSYNC, HSYNC, VSYNC) which are compatible with the monitor type of the coupled monitor ( 27 ),
characterized by
that the monitor ( 26 ) is designed such that it delivers an identification signal (MON.ID) identifying the monitor type to the monitor drive circuit ( 14 , 26 ),
that the monitor drive circuit ( 14 , 26 ) is self-configuring, and depending on the identification signal (MON.ID) selects a set of monitor display parameters compatible with the monitor type,
that the monitor drive circuit ( 14 , 26 ) has a dot clock generator ( 18-20 , 66 , 88 ) for generating a dot clock signal depending on the identification signal of the type that the dot clock signal is compatible with the monitor type, and
that the video timing circuit generates the compatible video timing signals (CSYNC, VSYNC, HSYNC) depending on the identification signal and / or the selected monitor display parameters. 2. Computer system according to claim 1, characterized in that
that the RAM ( 11 ) stores the video data to be displayed, that a register device ( 71 ) is provided which receives the identification signal (at 35), decodes it and selects an associated set of monitor display parameters, and
that the dot clock generator with the register means (71) and a plurality of reference frequency sources (18-20) is coupled, and selects in response to the identification signal, a reference frequency source (18-20). 3. Computer according to claim 2, characterized in that the point clock generator has a multiplexer ( 88 ) having a plurality of inputs ( 37 , 38 , 41 ) coupled to different reference frequency sources and an output ( 30 ) for outputting the point clock signal. 4. Computer system according to claim 1, characterized in that
that storage means is provided for storing all sets of monitor display parameters, and
that a selection device is coupled to the storage device which, depending on the identification signal, selects the compatible set of monitor display parameters. 5. Computer according to one of claims 1 to 3, characterized in that the set of monitor display parameters contains a number of bits per pixel of the video data supplied to the monitor ( 27 ) ge. 6. Computer according to one of claims 1 to 4, characterized characterized in that the point clock generator is programmable is. 7. Computer according to one of claims 1 to 6, characterized in that a video-digital / analog converter ( 26 ) is provided which receives the video timing signals and the video data and from these analog red, green and blue color video signals for the monitor ( 27 ) generated.