DE4024029C2 - Decision logic for prioritizing and synchronizing asynchronous signals - Google Patents

Description

The invention relates to decision logic for prioritization and synchro nization of temporally asynchronous signals according to the genus of the main claim.

State of the art

In multiprocessor systems, processor requirements for one Access to a global bus assigned to several processors organized a decision logic. This decision logic determines the Priority of the requesting processors according to a certain ranking, the then in the case of parallel requests, the order of allocation of the global Busses determined.

The decision logic must continue with a data transmission from the request changing processor to a peripheral device connected to the global bus the clock frequency asynchronous to the requested global bus the autonomous processor to transfer data to the clock frequency synchronize the global bus as the reference clock.

An interface controller for selective is known from EP-A2 01 30 471 Connecting two or more master bus systems with one slave bus system, one or more bus masters using one of the master bus systems one or more shared resources via a slave bus system are connectable. The interface controller contains means for reception of requirements of the bus master. Metastable states resulting from the requirements changes result, are hidden and it becomes a stable output signal delivered.

The interface controller also contains means for prioritizing the same requests from different bus masters to grant access on one of the resources to a higher priority master bus system.

This interface controller can meet lower priority requirements be permanently displaced, so that the lower priority bus master does not get access rights. This problem only becomes apparent when can request three or more bus masters. The longer the transmission time the higher prioritized bus master, the more likely it is that lower Priority bus masters are excluded from access.

task

The object of the invention is to provide a decision logic in which a fixed or rotating and a temporal prioritization of the occurrences the requirements are met and the signal throughput time and the Circuit effort is minimized.

The object is achieved by those mentioned in the characterizing part of claim 1 Features resolved.

Advantages of the invention

The decision logic according to the invention has the status of the Technology called the advantage that the turnaround time request one the signal is lower because the one-level prioritization between the Synchronization levels the clock frequency can be higher.

Furthermore, the decision logic according to the invention is able to, during a Output signal is active, d. that is, the global bus is allocated in parallel to to process the active output signal further requirements to the extent that a newly prioritized signal at the input of the second synchronization logic pending. This results in a faster processing time, because the Decision on further awarding of the global bus has already been made is. The principle of prioritization ensures that too lower priority requirements are taken into account and not out getting closed.

Figure description

The invention is explained in more detail using an exemplary embodiment.

Show it:

Fig. 1 shows a multiprocessor system having a common global bus, and a decision logic according to the invention in a block diagram,

Fig. 2 shows an embodiment of the decision logic according to the invention in a block diagram,

Fig. 3 is a timing diagram.

In Fig. 1, a multiprocessor system with a common global bus and a decision logic according to the invention is shown in a block diagram.

Four processors A to D working asynchronously with the central clock clk are via buses and ports A to D with the global bus and via request signals e ₁ to e ₄ with the decision logic and via signals a ₁ to a ₄ is the decision logic with the Ports A to D connected. Also on the global bus are global resources, e.g. B. memory, input / output interfaces, timers connected.

Resources and decision logic are supplied by the central clock clk.

Does one processor or multiple processors want to access the global bus grab, the corresponding signal e is activated by the processors. The decision logic decides according to a priority scheme (temporal and fixed prioritization or temporal and rotating prioritization), which The global bus is assigned to processors A to D, which activates the ent speaking signal a and turns it on, synchronized with the clock clk the port assigned to the corresponding processor. The port connects the Processor with the global bus so that the processor transfers its data to the global bus can transmit.

Fig. 2 shows an embodiment of a decision logic according to the invention in a block diagram.

The decision logic contains the five blocks of masking logic M, synchro nization logic S1, priority logic P, synchronization logic S2 and detection logic D.

Masking logic M and priority logic P as well as synchronization logic S1 and synchronization logic S2 are connected to one another. The masking logic M consisting of a combinatorial gate circuit M takes over the returned signals p ₁ 'p ₂ ', p _n 'and a ₁ ', a ₂ ', a _n ' tasks of the priority logic P. The synchronization circuits S1 and S2 are around Priority logic P consisting of a purely combinatorial switching network is arranged around. Each of the synchronization circuits S1 and S2 contains a flip-flop (FF) per input signal e ₁ to e _{n of} the decision logic. The FF's of the synchronization circuits S1 and S2 pass the signals pending at their inputs m ₁ to m _n and p ₁ to p _n with the reference clock clk. The signals m ₁ to m _n arriving asynchronously in time are synchronized by the synchronization logic S1 to the reference clock clk. The synchronization logic S2 processes the prioritized signals p ₁ to p _n and outputs them synchronously to the reference clock clk as output signals a ₁ to a _n .

The detection logic D monitors the output signals a ₁ to a _{n of} the decision logic by means of a logical OR operation. As soon as one of these signals is active, the current state of the synchronization logic S2 is "frozen" via the output signal d of the detection logic D. This mechanism prevents the withdrawal of the active output signal a _x and at the same time allows the preparatory prioritization of subsequent requests.

The current state of the synchronization logic S2 is signal c deleted. The signal c is generated via an external logic, if a processor has finished accessing the global bus. Then it can the next input signal e in the priority order take effect.

functionality

The request signals e ₁ to e _{n of} the connected processors are fed in at the inputs of the masking logic M. The request signals e ₁ to e _n occur asynchronously to one another and to the reference clock clk. In the initialization state, the masking logic M forwards all existing signals m ₁ to m _n directly to the first synchronization logic S1. In the first synchronization logic S1, the signals m ₁ to m _{n are} sampled with the reference clock clk. Only signals to the priority logic P that occur during a clock period of the reference clock clk are passed on. If several requests are detected by the first synchronization logic S1 at the time of sampling t _o , one of the signals S ₁ to S _{n is} selected by the priority logic P. The selection is made according to a fixed or rotating sequence. The successively occurring output signals p ₁ to p _n are passed on to the second synchronization logic S2. In addition, p ₁ to p _{n act} as feedback signals p ₁ ', p ₂ ', p _n 'also on the masking logic. Thus, the masking logic M achieves a temporal prioritization, which prevents subsequent request signals e ₁ to e _n to undo the decision made. The masking logic M now has the effect that the signals prioritized higher by the priority logic P, which occur at a later point in time than at the sampling time t _o, are not taken into account in the following sampling times.

After a running time td, only one signal p _{x is} active at the outputs of the priority logic P. Due to hazards (Hazards are interference signals that occur during the simultaneous transition from L to H and H to L in logic logic circuits, see Fig. 3, t _H ), several output signals p may be affected by spikes for a short time. Therefore, the second synchronization logic S2 is connected downstream. With the reference clock clk, the signal P _{x is released} after a sufficient calming time. The output takes place via the signals a ₁ ... a _n . The output signals a ₁ to a _{n also} act back on the masking logic M from a ₁ , a ₂ , a _n . In this way, an active signal a _x masks out the assigned request signal e _x . This allows all other request signals e to compete with each other again.

Fig. 3 shows a pulse diagram, based on which the function of the decision logic, corresponding to Fig. 2, is to be explained in detail.

All signals shown in Fig. 3 are active in the low state.

T ₁ : All input signals e ₁ to e _n become active within the same time window.
T ₂ : Since no output signal a ₁ to a _n and no prioritized signal p ₁ to p _{n is} active, all input signals e ₁ to e _n can pass through the masking logic M, m ₁ to m _n become active.
With the falling edge of T ₁ , the signals m ₁ to m _{n are} sampled in the first synchronization stage S1. Since all signals m ₁ to m _{n are} active, all output signals s ₁ to s _{n of} the first synchronization stage S1 are also activated.
In the event that the input signal e _{1 has} the highest priority, the input signal e _{n has} the second highest priority and the input signal e _{n has} the third highest priority, the signals p ₂ and p _{n are} masked out by the priority logic P, ie, p ₁ active and p ₂ and p _n remain inactive.
T ₃ : With the rising edge of T ₃ , the output signals p ₁ to p _{n of} the priority logic P are sampled by the second synchronization stage S2. Since p _{1 is} active, the output signal a _{1 of} the second synchronization stage S2 is activated. Via the connection to the input of the masking logic M _{1 a} ', the request signal e ₁ still pending is masked out, thereby making m ₁ inactive.
T ₄ , T ₅ , T ₆ : Since m _{1 is} inactive, S1 is also withdrawn with the falling edge of T ₃ . The output signal p _{2 of} the priority logic P is thus prioritized. This state is now held until the logic c is forced to release the logic, ie the processor requesting signal e ₁ has ended its data transmission (in M ₅ ) and releases the common global bus (M ₆ ) . The output signal a ₁ becomes inactive. With the following rising edge (T ₇ ) the output signal a ₂ is already output for the processor requesting the second highest priority.
T ₇ : Via the signal a ₂ ′ which is attributed to the input of the masking logic M, m ₂ becomes inactive. With the falling edge of T ₇ , the output signal s _{2 of} the first synchronization stage s _{1 is} withdrawn. The output signal p _{n of} the priority logic p is thus prioritized. This state is maintained again until the logic c is forced to release the logic again, ie the processor requesting the signal e ₂ has ended its data transmission and is releasing the common global bus. P _n becomes active.
T ₈ to T ₁₂ : Despite a request by e ₁ , p _n remains active during the following clocks, since the return of the prioritization to the masking logic prevents low-priority requests from being blocked.
The processor requesting signal e ₂ transmits its data.
With the rising edge, a _{n is} output.

Claims (1)

Decision logic for prioritizing and synchronizing to a reference clock of temporally asynchronous request signals for the bus access of processors to a global bus connecting them and, if necessary, these with other devices, with a first synchronization logic and a priority logic with a predetermined order of priority for the request signals and a second synchronization logic, characterized in that that a masking logic (M) is provided, which signals the asynchronous request signals (e ₁ -e _n ), signals derived from the priority logic (P) (p ₁ -p _n ) and signals (a _1. ) returned by the second synchronization logic (S2) '-A _n ') are supplied so that with the masking logic (M) subsequently occurring at a sampling time (t _o ) request signals (e₁-e _n ) with higher priority until the end of the accesses of the access signals generated according to the predetermined priority order (a₁ -a _n ) ge be blocked.