DE4016695C2 - Method of forming buried areas in a semiconductor substrate - Google Patents

Description

The invention relates to a method for producing Insular areas in a semiconductor substrate.

In such a method described in DE-OS 40 02 673 the substrate is made of an n-type polycrystalline silicon treated after the introduction of V-shaped grooves so that an insulating layer on the side walls delimiting the grooves is formed, below which an n + -type layer lies, which consists of a layer of polycrystalline silicon and one Diffusion layer is composed. After that, the substrate so far on its surface facing away from the grooves sanded until the base areas of the grooves also are ground away so that the insulating layer and the n + type layer free on the ground surface lie. The remaining substrate is then turned over so that the Island areas, each delimited by the layers and both against each other and towards the others Parts of the substrate are insulated, freely accessible upwards. This is on the surface of the substrate that is now at the bottom by another substrate of a certain thickness from an n - type reinforced polycrystalline silicon. The island areas and the between neighboring island areas buried areas of the substrate are each from the same material with the same cable type.

A semiconductor component is known from EP 02 223 694 A2 for the purpose of isolating island areas from the Substrate provides that vertical island surrounding an island area Grooves into the p-type substrate to such a depth and be cut in such a position that a buried n-doped region is reached via the vertical grooves. The side walls of these grooves are covered with an insulating film  provided, after which the grooves are filled with a glass mass become. An oxide layer is applied to this glass mass, which extends as bridges over the grooves after the Glass mass from the grooves and the surface area of the Substrate was removed. Over the then empty vertical grooves the material of the buried area is etched out so that below the island area with the island area surrounding grooves forms connected cavity. This The cavity is then together with the grooves with one not filled doped polycrystalline silicon that the Island area insulated on all sides from the substrate.

From US-PS 39 90 102 is an integrated semiconductor circuit known that a layer of high resistance, a dielectric insulating film and monocrystalline island areas from n-type and a low-resistance layer of the n-type having.

From US-PS 38 71 007 is a semiconductor integrated circuit known, which has individual crystal regions, of evaporated polycrystalline areas of higher resistance are surrounded. The areas are isolated from each other.

EP 01 191 476 A2 is a composite Semiconductor device known that a space, an annular Groove filled with a filler, n-type post or buried areas, an insulating layer and one Has transistor. The buried areas are from the substrate isolated over the insulating layers.

The object of the invention is a method of the type mentioned develop that in a simple manner a semiconductor device is to produce, in which parasitic effects, such as a latch-up effect between semiconductor elements in two adjacent island areas are formed over the substrate  are to be prevented by improving the thermal conductivity and the breakdown resistance against Voltage peaks and static electricity is increased, whereby these semiconductor devices without using Epitaxial procedures are to be established.

This object is by the specified in claim 1 Features resolved.

The inventive method is characterized in that the buried areas in a simple manner and a minimal Number of process steps within the substrate see above are appropriate that the respective island areas are complete and sufficient against the substrate by the material of the buried areas are electrically isolated so that no latch-up effects or material breakthrough due to high electrical voltages or electrostatic fields may occur.

Embodiments of the invention are in the subclaims specified.

Conventional and inventive embodiments explained in more detail with reference to the drawings; show it:

Fig. 1 to 3 are longitudinal sections of conventional semiconductor devices;

Fig. 4 is a plan view of a first embodiment of the semiconductor device according to the invention;

Fig. 5 is a longitudinal section along the line V of Fig. 4;

Fig. 6 is a longitudinal section along the line VI-VI of Fig. 4;

Fig. 7 is a longitudinal section along the line VII-VII of Fig. 4;

Fig. 8 is a longitudinal section along the line VIII-VIII of Fig. 4;

FIG. 9A to 9E cross sections for explaining a proze sses for manufacturing the semiconductor device shown in Fig. 4;

FIG. 10A is a plan view of a second exporting approximate shape of the semiconducting terbauelements invention;

Fig. 10B is a longitudinal section along the line XB-XB of Fig. 10A;

Fig. 10C is a longitudinal section along the line XC-XC of Fig. 10A;

FIG. 11A is a plan view of a third form of exporting approximately semiconducting terbauelements invention;

Fig. 11B is a longitudinal section along the line XIB-XIB of Fig. 11A;

Fig. 11C is a longitudinal section along the line XIC-XIC of Fig. 11A.

In Fig. 1, a CMOS structure is shown as a conventional semiconductor device in the MOS structures of a self-separation process are electrically separated from each other by using, in order to avoid mutual interference between them. In a surface area of an n-substrate 1 , a p sind-source area 2 and a p⁺-drain area 3 are formed at a certain distance from one another, while a gate electrode 5 is formed on the substrate 1 , wherein between the substrate 1 and the gate electrode 5 a gate oxide film 4 arranged between the source region 2 and the drain region 3 ; a p-channel MOSFET (pMOS 8 ) is thus obtained in the right part of the substrate 1 . A p-well region 11 is also formed in the surface region of the substrate 1 . An n⁺-source region 12 and an n⁺-drain region 13 are formed in the surface region of the well region 11 , while a gate electrode 15 is formed on the well region 11 , wherein between the well region 11 and the gate electrode 15 there is a between the source region 12 and the drain region 13 arranged gate oxide film 14 is located; an n-channel MOSFET (nMOS) 18 is thus obtained in the left part of the substrate 1 .

The pMOS 8 and the nMOS 18 are each surrounded by a field oxide film 19 formed in the surface region of the substrate 1 in order to separate the pMOS and the nMOS. An insulating film covers the entire surface of the pMOs and nMOS structures 8 and 18 obtained on the substrate 1 . The insulating film 10 is penetrated by a pair of source and drain electrodes 6 and 7 , which are connected to the respective source and drain regions 2 and 3 in the pMOS 8 . Furthermore, the insulating film is penetrated by a pair of source and drain electrodes 16 and 17 , which are connected to the respective source and drain regions 12 and 13 in the nMOS 18 . In this CMOS component, the n-substrate 1 is connected to a power source V _DD (<0), while the p-well region 11 is coupled to a low-voltage point, as a result of which the pMOS 8 and the nMOS 18 are electrically isolated from one another. The pMOS 8 and the nMOS 18 can therefore be operated independently of one another.

In this CMOS component, however, a parasitic thyristor is formed, which is built up by the series connection of the p⁺ source region 2 , the n substrate 1 , the p well region 11 and the n⁺ source region 12 , so that in this CMOS Component has a tendency to latch-up.

A conventional bipolar IC component is shown in FIG. 2, in which the npn and pnp transistors are separated from one another by using a zone transition separation method, ie by a pn transition formed between the transistors. This bipolar IC device is manufactured as follows.

As shown in Fig. 2A, the growth of an epitaxial n-layer 22 is first accomplished on a p-substrate 21 , whereupon in the epitaxial layer 22 p⁺-separating diffusion regions 23 are formed so that they reach the substrate 21 in order to between the Separation diffusion regions 23 to obtain n-island regions 24 . Then, as shown in FIG. 2B, a p base region 25 is formed in an n island region 24 , which serves as a collector region, whereupon an n⁺ emitter region 26 is formed in the surface of the p base region 25 . An n Insel collector contact region 27 is formed in the island region 24 in order to obtain an npn transistor 28 . In a further n-island region 24 , which serves as the base region, a p⁺-emitter region 29 , a p⁺-collector region 30 and n⁺-base contact region 31 are formed separately from one another in its surface in order to obtain a pnp transistor 32 . Before that, a buried n + region 33 is formed between the p-substrate 21 and the n-island region 24 . In this case, the substrate 21 is connected to a low-voltage point in order to electrically separate the n-island regions 24 from one another by the p⁺ separation regions 23 . Therefore, the NPN transistor 28 and the PNP transistor 32 can be operated independently of each other.

In this case, however, an epitaxial procedure is essential which is why the process costs are so high that they too lead to increased costs of the end product.

FIG. 3 shows a further conventional semiconductor component in which transistors are separated from one another by using a dielectric separation method, ie by means of an insulating film. As shown in FIG. 3, n-island regions 43 are formed in the surface of a semiconductor substrate 41 such as polycrystalline silicon, and there is an insulating film 42 made of SiO 2 or the like between the substrate 41 and the island regions 43 around the island regions 43 from the substrate 41 to separate. In an island region 43 serving as a collector region, a p-base region 44 is formed in its surface, while an n⁺ emitter region 45 is formed in the surface of the base region 44 . An n⁺ collector contact area 46 is also formed in the island area 43 , so that an npn transistor 47 is obtained. The transistors formed in each island region 43 can be operated independently of one another.

In this case, however, since the island regions 43 are separated by the insulating film 42 , the heat radiation property is poor on the one hand, while on the other hand the resistance to an increased voltage and to destructive static electricity is low.

In Figs. 4 to 7, a first embodiment of the semiconductor device according to the invention is shown. In Fig. 4, a field oxide film 62 and an insulating film 63 are omitted for easy understanding.

In the drawings, in a surface area of an n- (or possibly a p-) silicon semiconductor substrate 51, a plurality of island areas, for example a p-island area 52 , an n-island area 53 and an n-island area 54 , are removed from the substrate 51 Arranged buried p-regions 55 and 56 surrounded and isolated from polycrystalline or amorphous silicon.

The buried areas 55 and 56 are connected to a low voltage point. As clearly shown in Fig. 6, an n⁺-type source region 57 and an n⁺-type drain region 58 at a certain distance are formed from each other in the surface area of the p-type island region 52, while on the p-type island region 52, a gate electrode 59 of polycrystalline silicon is formed, with a gate oxide film 60 arranged between the source region 57 and the drain region 58 between the p-island region 52 and the gate electrode 59 ; an nMOS 61 is thus obtained. A field oxide film 62 formed on the substrate 51 surrounds the nMOS 61 , and the entire surface of the component obtained is covered by an insulating film 63 . The source electrode 65 and the drain electrode 66 are connected through the insulating film 63 to the corresponding source and drain regions 57 and 58 , respectively. Furthermore, a pair of electrodes 67 and 68 are connected to the buried regions 56 through the insulating film 63 .

As clearly shown in FIG. 7, a p Oberfläche-source region 70 and a p in-drain region 71 are formed in the surface of the n-island region 53 at a certain distance from one another, while a gate electrode 72 is formed on the n-island region 53 polycrystalline silicon is formed, a gate oxide film 73 arranged between the source region 70 and the drain region 71 being located between the n-island region 53 and the gate electrode 72 ; a pMOS 74 is thus obtained. A source electrode 75 and a drain electrode 76 are connected through the insulating film 63 to the source region 70 and the drain region 71 , respectively.

As clearly shown in FIG. 8, a p-base region 78 is formed in the surface of the n-island region 54 serving as the collector region, while an n + emitter region 79 is formed in the surface of the base region 78 . At a distance from the base region 78 in the surface of the island portion 54 is formed a rich Kollektorkontaktbe 80 so that, finally, an npn transistor 81 is obtained in n-Inselbe rich 54th The base electrode 82 , the emitter electrode 83 and the collector electrode 84 are accordingly through the insulating film 63 through with the base region 78 or with the emitter region 79 or with the collector contact region 80 connected.

In this embodiment, the nMOS 61 and the pMOS 74 form a CMOS transistor. In this case, by applying a reverse voltage to the pn junction between the n-island region 53 or 54 and the buried p-region 55 or 56, these two regions 53 or 54 and 55 or 56 can be electrically separated.

Since a substrate voltage (low voltage) is applied to both the p-type island region 52 and the buried p-type regions 55 and 56, needs between the p-Inselbe rich 52 and the buried p-type regions 55 and 56 no pn junction formed . However, if the p-island region 52 is formed by p-type impurity doping in the n-region, a part of the n-region can be left in its original state, which means that it is not converted into a p-region, so that there is an n-region between the p-island region 52 and the buried p-regions 55 and 56 ; thereby who the p-island region 52 and the buried p-regions 55 and 56 through the pn junction between the buried p-regions 55 and 56 and the n located between the p-island region 52 and the buried p-regions 55 and 56 - Electrically separated area.

As described above, in this embodiment, island regions 52 , 53 and 54 can be formed without using an epitaxial process. Compared to monocrystalline silicon, the polycrystalline or amorphous silicon of the buried regions 55 and 56 contains many recombination centers, which is why the gain sum of the parasitic thyristor of the CMOS fulfills the following equation:

αNPN + αPNP <1.

Therefore, the cause of the latch-up effect can be completely dig be suppressed. Furthermore, since the polycrystalline or amorphous silicon has good thermal conductivity  owns, even if an overvoltage or static electricity from the connectors or the like Lichem act on the semiconductor device, the cons stability properties against overvoltage and static electricity can be greatly improved.

Now, an embodiment of a manufacturing method of the above-described semiconductor device according to the present invention will be explained in detail with reference to FIGS . 9A to 9E, and FIGS . 9B and 9D also include partial plan views.

As shown in FIG. 9A, a p-type region 85 having a surface is formed in the surface region of an n-type silicon substrate 51 in order to later create a p-type island region; thereupon, a three-layer laminating film 86 serving as a pattern mask is applied to the substrate 51 and is composed of two SiO ₂ layers and an Si ₃ N ₄ layer arranged therebetween.

In FIG. 9B, vertical grooves 87 are formed in the surface region of the substrate 51 using the laminated film mask 86 by means of a reactive ion etching method.

In Fig. 9C, the sidewalls of the vertical grooves 87 are etched using an alkaline, anisotropic etching solution such as hydracin or ethylenediamine to form enlarged grooves 88 and triangular sections to the p-island region 52 and the n-island regions 53 and 54 to lend. During the etching of the silicon by using, for example, an alkaline, anisotropic etching solution, the etching rate on the surfaces is considerably delayed when the surfaces are exposed, which is why the island regions 52 , 53 and 54 can be excellently cut out without difficulty.

In Fig. 9D, the widened grooves to obtain 88 doped p-type with a polycrystalline or amorphous silicon on filled to p-type buried regions 55 and 56 from polykri stallinem or amorphous silicon so that the island regions 52, 53 and 54 completely to the substrate 51 are separated.

In Fig. 9E, the surface areas of the p-doped polycrystalline or amorphous silicon of the buried areas 55 and 56 are oxidized to conventionally form an oxide film 62 on the surface with a thickness of about 700 nm to thereby obtain a substrate circuit board. Then, the required nMOS, pMOS and bipolar transistors are formed in the island regions 52 , 53 and 54 in a conventional manner, whereby a semiconductor component according to the invention is obtained. As described above, in this embodiment, the p-island region 52 and the n-island regions 53 and 54 can be formed without using an epitaxial process.

FIGS. 10A to 10C show a second embodiment of the semiconductor component according to the invention, which has the same structure as the first embodiment of the semiconductor component shown in FIGS. 4 to 9, with the exception that a p-island region 92 , an n- Island region 93 and an n-island region 94 , which are surrounded by buried p-regions 95 and 96 made of polycrystalline or amorphous silicon, are formed deeper than the island regions 52 , 53 and 54 shown in FIG. 5, so that the island regions 92 , 93 and 94 are in their upper half each with vertical side walls 92 a, 93 a and 94 a hen. In this embodiment, since the upper halves of the island areas 92 , 93 and 94 are formed with vertical side walls 92 a, 93 a and 94 a, the effective area of the island areas 92 , 93 and 94 is greatly increased in the depth direction, which is why they are used for components elements that require a certain thickness to be formed in the island regions 92 , 93 and 94 is very much more suitable. Of course, the CMOS and bipolar transistors shown in Figs. 4 to 9 in the Inselbe range can be formed in the same manner as in the first embodiment described above.

In a manufacturing process for the semiconductor device shown in FIGS. 10A to 10C, the process is carried out in the same manner as in the first embodiment described above, except that in the middle of the formation of the vertical grooves in the surface area of the substrate 51 , which takes place in the same way as in Fig. 9B, the side walls of the vertical grooves, which correspond to the upper half of the vertical side walls 92 a, 93 a and 94 a of the island areas 92 , 93 and 94 , with an etching permanent film of Si ₃ N ₄ or the like are coated.

In FIGS. 11A to 11C, a third embodiment of the semiconductor device according to the invention is shown having the same structure as that in FIGS. 4 to 7 shown first embodiment has, with the exception that now a bulk CMOS structure or a complementary MISFET Structure to be trained. In Fig. 11A, the field oxide film 62 and the insulating film 63 are omitted for easier understanding.

In this embodiment, a p-well region 102 is formed in the surface region of an n-silicon semiconductor substrate 51 , while in the same manner as described above, an nMOS 61 having the same structure as that shown in FIG. 6 is formed in the surface region of the p-well region 102 becomes. An n-island region 103 surrounded by buried n-regions 105 and 106 made of polycrystalline or amorphous silicon is separated from the p-well region 102 contained in the pMOS 61 in the same manner as that shown in FIGS . 4 to 7 Embodiment is formed in the surface region of the substrate 51 , while a pMOS 74 with the same structure as in FIG. 7 is formed in the surface region of the n-island region 103 in the same way as in the first embodiment described above. Power sources V _SS and V _{DD are} connected to the source electrodes 65 and 75 of the MOS transistors 61 and 74 .

By creating buried regions 105 and 106 made of polycrystalline or amorphous silicon, in this embodiment the amplification of a parasitic thyristor, which is achieved by the series connection of a p⁺ source region 70 , the n-island region 103 , the buried n-regions 105 and 106 , the n-substrate 51 , the p-well region 102 and an n⁺-source region 57 and occurs between the nMOS 61 and the pMOS 74 can be reduced, thereby eliminating the cause of the latch-up effect .

As described above, this embodiment is applied to a self-separation type CMOS structure, therefore the conduction type of the buried regions 105 and 106 and the island region 103 is of the same n-type. Furthermore, in addition to the island region 103, the p-well region 102 can also be designed in the form of an island region surrounded by buried p-regions in order to prevent the cause of the latch-up effect even more precisely. Furthermore, in this embodiment, instead of the n-island region 103, the p-well region 102 can be designed in the form of an island region surrounded by buried p-regions in order to eliminate the cause of the latch-up effect. This means that the nMOS 61 can be formed in the surface region of the p-island region surrounded by buried p regions and the pMOS 74 can be formed in the surface region of the substrate.

Claims (6)

1. A method for forming buried regions ( 55 , 56 ; 95 ; 96 ; 105 , 106 ) in a semiconductor substrate ( 51 ) of a first conductivity type, whereby at least two island regions ( 52 , 53 , 54 ; 92 , 93 , 94 ; 103 ) in a surface area of the semiconductor substrate ( 51 ) are formed with the following method steps:

• (a) forming an insulating film ( 86 ) on surface areas of the semiconductor substrate ( 51 ) in which island areas ( 52 , 53 , 54 ; 92 , 93 , 94 ; 103 ) are to be formed;
• (b) etching grooves ( 87 ) into the exposed surface areas of the semiconductor substrate ( 51 ), the grooves having vertical sidewalls;
• (c) enlarging the grooves ( 87 ) along preferred crystal directions of the semiconductor substrate ( 51 ) by anisotropically etching the vertical sidewalls of the grooves ( 87 );
• (d) Filling the enlarged grooves ( 88 ) with a polycrystalline or amorphous semiconductor material which is doped according to a second conductivity type, so that island regions ( 52 , 53 , 54 ; 92 , 93 , 94 ; 103 ) are penetrated by buried regions ( 55 , 56 ; 95 , 96 ; 105 , 106 ) are electrically isolated, are obtained, and
• (e) forming an oxide film ( 62 ) on the exposed surfaces of the polycrystalline or amorphous semiconductor material.

2. The method according to claim 1, characterized in that the substrate ( 51 ) is an n-type silicon substrate and that the vertical side walls of the grooves ( 87 ) are etched with the aid of an alkaline, anisotropic etching solution, the etching speed by exposure of the surface considerably can be delayed. 3. The method according to claim 1, characterized in that a reactive ion etching method is used in step (b) becomes. 4. The method according to claim 1, characterized in that the island regions ( 52 , 53 , 54 ) formed in step (c) have a triangular cross section along a crystal direction of the semiconductor substrate ( 51 ). 5. The method according to claim 1, characterized in that the island regions ( 92 , 93 , 94 ) by partially coating the vertical side walls of the grooves ( 87 ) formed in step (b) with an etch-resistant film before forming the grooves enlarged by etching are formed, as a result of which the island regions ( 92 , 93 , 95 ) formed have a pentagonal cross section along a crystal direction of the semiconductor substrate ( 51 ). 6. The method according to claim 1, characterized in that in step (d) the enlarged grooves are filled with a polycrystalline or amorphous semiconductor material which is doped according to a first conductivity type in order to a buried region ( 105 , 106 ) of a first conductivity type is obtained, whereby an island region ( 103 ) of the first conductivity type is formed, which is isolated from the substrate ( 51 ) by the buried region ( 105 , 106 ) of the first conductivity type, a MOS transistor ( 74 ) in the island region ( 103 ) of a second conductivity type, and that a well region ( 102 ) of a second conductivity type is formed in a surface region of the substrate ( 51 ), a MOS transistor ( 61 ) of a first conductivity type being formed in the well region ( 102 ).