DE3943764C2 - Digital multichannel signal reproducer - Google Patents

Abstract

The arrangement contains n reproduction heads for acquiring signals from a number of parallel tracks of a recording medium contg. digital data for n tracks where n is greater than one. The information in the signals is stored and accessed for defined processing. An identifying device determines which of the digital signals for the n channels corresp. to the n reproduction heads and generates identity data. A controller adjusts the time for access to the memory device taking account of a reproduction time for acquisition of the digital information by the n heads according to the identity data.

Description

The invention relates to a device for Reproduction of digital information from a record carrier according to the preamble of claim 1.

A facility with all the features of the generic term of Claim 1 is known from US 4,539,605.

An example of a multi-track playback device for digital signals is a digital video tape recorder. In the The following description will be the digital video tape device explained.

Generally, video signals have a wide bandwidth. Therefore is the amount of data per unit of time for digital video large signals into which the video signals are digitized, and it's difficult to make a serial magnetic record and perform playback of the digital video signals.  

As a result, these digital video signals have been applied to several Channels distributed to the amount of data or the data clock depending Channel decrease. Therefore, in a digital video tape usually recorded and reproduced in multiple channels give.

If all the digital signal processing in one Di gital video tape recorder executed in chronological order part of a picture goes as a result of the creation of bundles of errors completely lost by a Damage to a tape, clogging of a magnetic head and the like are caused. Therefore, a correction difficult by interpolation or the like, leading to leads to adverse results. Since also the majority a data matrix or an error correction block an error correction code (ECC) is added the whole error correction block itself results when adding a code with high error correction Incorrect data capability, so the code has very little effect is full.

In general, it follows in a digital video tape device the recording and playback with division of an error correction blocks into several sections regarding the time sequence are distributed. It is also conceivable the order of data of each picture element an image area with regard to the temporal succession follow change, creating excellent interpolation can also be made if an error correction is impossible. In such a digital video tape recorder the processing such as encoding and decoding one Error correction codes, the arrangement and implementation of the data and the like, using the video signals for one predetermined period of time as a unit. In a digital video tape recorder, in which multi-channel is drawn and reproduced, these processing  executed such that a unit by video signals is formed, which is recorded on tracks in a number are an integer multiple of a number n Channels is. As a result, an ambiguous signal ver prevents work during playback. In a digi tal video tape device is usually the round-trip frequency from rotating heads to an integer ratio with respect to the frame rate of the video signals. This is advantageous in that the design of servo system circuits, from conditioning circuits for the Video signals and the like is simplified.

Accordingly, in a multi-channel digital video tape device generally the video signals for one frame on (n × j) tracks are recorded, where n is the number of channels is and j is an integer and at least "1", and the Processing described above completely below Formation of the video signals recorded on (n × i) tracks executed to a unit, where i is an integer and is at least "1".

Fig. 1 shows a head assembly of a multi-track di gital video tape device. According to Fig. 1, eight rotary heads H1 are arranged on a rotary drum 1 to H8. The heads H1 to H4 and H5 to H8 are each arranged directly next to each other. The heads H1 to H4 are further arranged so that they sweep a magnetic tape at the same time. Likewise, the heads H5 to H8 are arranged so that they sweep over the magnetic tape at the same time. The heads H5 to H8 are rotated with a phase difference of 180 ° with respect to the heads H1 to H4. For a four-channel recording, the heads H1 to H4 and the heads H5 to H8 thus alternately sweep over a magnetic tape which is laid around the drum 1 over an angular range of at least 180 °.

FIG. 2 shows a track pattern recorded on a magnetic tape T by means of the heads shown in FIG. 1. Tracks labeled Tr1 to Tr8 are the tracks recorded by heads H1 to H8, respectively. By moving the heads H1 to H4 obliquely upward from the positions shown in FIG. 2 by the reference numerals H1 to H4, the four-channel recording is carried out, whereby the tracks Tr1 to Tr4 are formed. The four-channel playback is also carried out by sweeping tracks Tr1 to Tr4. The heads H1, H3, H5 and H7 have the same azimuth angle and the H2, H4, H6 and H8 also have the same azimuth angle, but which is different from that of the heads H1, H3, H5 and H7. As a result, a so-called azimuth recording is carried out.

In the digital video tape recorder according to this example, the rotation speed of the drum is 1 1800 revolutions per minute and the video signals for one frame are recorded on eight tracks. The signal processing described above is carried out for the eight tracks, namely on the video signals for one frame. Since the frame frequency thereby coincides with the revolution frequency of the drum 1 and the signal processing is carried out in frame units, it is possible to carry out the timing of each unit together, resulting in a digital video tape device having a simple circuit structure.

In the above-described digital video tape apparatus, during the signal processing during playback, the reproduction signals from the heads H1 to H4 and the subsequent reproduction signals from the heads H5 to H8 are formed into one unit. As a result, heads H1 to H8 must inevitably scan tracks Tr1 to Tr8 during playback. Although it is possible to reproduce the signals, for example, even if the heads H1 to H4 with the same azimuth angle, the tracks Tr3 to Tr6 (as shown by H1 'to H4' in Fig. 2) or the tracks Tr5 to Tr8 (according to the Dar position by H1 '' to H4 '' in Fig. 2), it is not possible to recover the original video signals, since according to the above statements, the signal processing by forming the playback signals from the heads H1 to H4 and the subsequent ones Playback signals from the heads H5 to H8 to one unit.

Therefore, in digital video tapes of this type So far, the tracking control performed such that the Head H1 inevitably scans track Tr1. However, since Out of eight tracks, only one track is the target for the head is H1, a tracking or tracking error of ± four tracks arise. As a result, if immediately after starting the device or from any Chen the tracking control is disturbed for other reasons, a very long period of time is required to engage to achieve status with the tracking control. While video signals cannot be played back during this time. Accordingly, the video signals can last for a long period of time when starting the device or in the event of a tracking fault cannot be played back, so a playback picture is very is unsightly.

Furthermore, a pattern of recording signals for the Track control a period of eight tracks have so that the circuits for tracking both unavoidable when recording as well as during playback get complicated. In addition, in one device, in which a pilot signal is recorded on part of a track net that is used for tracking control is not only the circuit complicated, but also a big one  Recording area required for the pilot signal. This Circumstances prevent high-density recording.

These problems are compounded by an increase in the number of Channels and the number of tracks for signal processing more serious. This represents a greater disability represents if a further improvement of a record high-density broadband signals.

The invention has for its object a reproduction direction according to the preamble of claim 1 form that a quick tracking lock is enabled, which are particularly well suited for use in a system is in which digital signals with extremely high Data density recorded and reproduced in high density will.

The task is carried out by a facility with solved the features specified in claim 1. Advantageous developments of the invention are Subject of the subclaims.

The invention is described below with reference to exemplary embodiments len explained with reference to the drawing.

Fig. 1 shows a head assembly of a digital video tape device.

Fig. 2 shows a recording pattern on a tape in the digital video tape apparatus having the head arrangement shown in Fig. 1.

Fig. 3 shows schematically a recording system of a digital video tape device according to an embodiment example.

Fig. 4, 5 and 6 are diagrams for explaining the maintenance of In by means of the shown in Fig Di. 3 gital-VTR recorded data.

FIG. 7 shows an example of a pilot signal generator according to FIG. 3.

Fig. 8 shows the arrangement of pilot signals for tracking control, which are recorded on a tape by means of the digital video tape device shown in Fig. 3.

Fig. 9 shows schematically as a first embodiment of the playback device a playback system of a digital video tape device.

Fig. 10 shows an example of a tracking control circuit shown in Fig. 9 for automatic tracking.

Fig. 11 is a time chart of the operation times for jewei celled units according to Fig. 9.

FIG. 12 shows an example of a reproduction track detection circuit shown in FIG. 9.

FIG. 13 shows an example of a timing circuit shown in FIG. 9.

Fig. 14 schematically shows a reproducing system of a digital video tape device as a second embodiment of the reproducing device.

Fig. 15 schematically shows a playback system of a digital video tape device as a third embodiment of the playback device.

FIG. 16 is a timing chart for explaining the operation of an address control circuit shown in FIG. 15.

Fig. 17 (A) and 17 (B) show an arrangement of a head mehrka naligen digital data recording device device as a fourth embodiment for playback.

Fig. 18 shows a pattern recorded by the head arrangement shown in Figs. 17 (A) and 17 (B).

Fig. 19 shows schematically the design of the digital data recording device according to the fourth embodiment of the playback device.

FIG. 20 shows an example of a recording processing circuit of the data recording apparatus shown in FIG. 19.

FIG. 21 shows a possible configuration of a pilot signal generator of the data recording device shown in FIG. 19.

Fig. 22 shows a pattern of memory areas and addresses in a memory of the data recorder shown in Fig. 19.

FIG. 23 shows the layout of a reproduction processing circuit of the data recording device shown in FIG. 19.

Fig. 24 is a flowchart for explaining part of the operation of the digital data recording device as an embodiment of the reproducing apparatus.

1st embodiment

Fig. 3 shows schematically the design of a recording system in a digital video tape device in which the playback device is used.

According to FIG. 3, a video signal is input at a terminal 2 , which is fed to a serial processing circuit 4 , in which signal processing is carried out after an analog / digital or AD conversion, which can be carried out serially in time. For example, a relatively simple band compression such as undersampling, digital pulse code modulation (DPCM) or the like, and accompanying processing such as filtering or the like can be performed in series or sequentially without using a large memory. In the recording system according to this example, the conditioning circuit 4 includes an A / D converter, a two-dimensional spatial frequency filter, an undersampling unit and a digital pulse code modulation circuit. The digital signal from the processing circuit 4 is fed to a read / write memory (RAM) 6 .

The read / write memory 6 is a memory for processing necessary for changing data within one frame, namely processing that is carried out entirely in one frame. For example, an error correction coding, a conversion of the data arrangement within a frame with respect to output data and the like is carried out via the memory 6 . An error correction encoder (ECC encoder) 8 receives data from the memory 6 and delivers data to it, while characteristic data ID is supplied by a characteristic signal generator 10 in addition to the data in the memory 6 .

The access time to the data in the memory 6 is determined by a signal with a frame period, which is formed by entering a vertical synchronization signal extracted circuit 12 with a vertical synchronization signal in a timer or T flip-flop 14 .

The processing carried out in the memory 6 in this example is explained below with reference to FIGS. 4, 5 and 6.

It is assumed that the video data contained in a single error correction block or ECC block is that amount of data which corresponds to an image area which, as shown in FIG. 4, is formed by dividing an image area G of a frame into 4 × 6 areas. The data is not simply data within an area obtained by dividing the image area into 4 × 6 parts, but data which, after rearranging the image data stored in the memory for one frame, for example in line units, from one by dividing the memory area for a full image in 4 × 6 partial areas obtained memory area are picked out and the distributed locations correspond to the actual image area.

After reordering the data into a data matrix of such image data, which for example consist of 60 lines in the vertical direction and 84 image elements (each consisting of one byte) in the horizontal direction, four-byte parity data C2 and four become respectively in the vertical and horizontal directions -Byte parity data C1 added to get an error correction block. In the apparatus according to the example, since the video signals are recorded for one frame divided into eight tracks, three error correction blocks are recorded on one track. In fact, however, 16 × 88 data is allocated to each track, which are picked from twelve error correction blocks. As shown in Fig. 5, a single error correction block contains four 16 x 88 byte data blocks, each of which is recorded on a different track. The numbers 1 , 3 , 5 and 7 in Fig. 5 indicate the track numbers for each frame and correspond to the tracks Tr1, Tr3, Tr5 and Tr7, respectively. In the example, the error correction blocks on the right side of the screen are recorded on tracks with even numbers, while the error correction blocks on the left side are recorded on tracks with odd numbers.

Fig. 6 shows an example of the format of synchronizing blocks. Referring to FIG. 6, the error correction blocks for four lines form a unit, the synchronizing bit Sy with about one byte, and data X with about three bytes, which receive the numbers of the sync blocks and redundant bits thereof are added to the assembling of the format. As a result, there are 12 × 4 = 48 sync blocks on each track that contain the video data Vd.

The identification signal generator 10 according to FIG. 3 generates additional 4 × 88 byte identification data ID per track, for which the memory 6 forms a synchronization block per track. The identification data ID contains, in addition to known time code data, marking information and the like, data which shows the track numbers (Tr1 to Tr8) within each frame.

The data output from the memory 6 are divided into four channels in a distributor 16 in accordance with the rules described above and are each modulated in digital modulators 18 a, 18 b, 18 c and 18 d. The modulated signals are mixed in adders 20 a, 20 b, 20 c and 20 d each with a tracking pilot signal from a pilot signal generator 24 described below, after which the resulting signals via amplifiers 22 a, 22 b, 22 c and 22 d Switches 26 a, 26 b, 26 c and 26 d are supplied. A head switching pulse generator 28 generates a single-period square wave signal as head switching pulse HSP, with which the switches 26 a, 26 b, 26 c and 26 d are controlled per revolution of the drum 1 in synchronism with the rotation phase thereof. That is, when the tape T is scanned with the heads H1, H2, H3 and H4, the head switching pulse HSP assumes the high level H, and when the tape T is scanned with the heads H5, H6, H7 and H8, the Head switching pulse HSP at the low level L.

The phase of the head switching pulses HSP is compared with that of the output signal of the T flip-flop 14 with the full frame period in a phase comparator 30 , the output signal of which controls a circulation control circuit 32 for regulating the drum rotation. The rotation phase of the drum 1 is controlled in such a way that the phase difference between the head switching pulses HSP and the output signals of the T flip-flop 14 becomes zero and thus synchronization between the signal processing time of the memory 6 and the recording time of the respective head is achieved.

The head switching pulses HSP are also fed to the pilot signal generator 24 , in which the time of generating a pilot signal is controlled for the tracking control. Fig. 7 is a circuit diagram showing an example of the pilot signal generator 24 . FIG. 8 shows a pattern of pilot signals recorded on the tape T which are generated by the pilot signal generator 24 shown in FIG. 7.

FIG. 7 shows an input connection 100 for the input of the head switching pulses HSP, an oscillator 102 for generating a signal, hereinafter referred to as f1, with a frequency f1 and an oscillator 104 for generating a signal, hereinafter referred to as f2, with a frequency f2. A switch 106 is switched at a high level of the head switching pulse HSP into a position H or at a low level of the head switching pulse HSP into a position L and outputs the signal f1 and the signal f2, respectively. Monostable multivibrators 108 and 110 determine the switching times of switching elements 112 a, 112 b, 112 c and 112 d. The flip-flop 108 is triggered by the leading and trailing edges of the head switching pulses HSP and supplies the flip-flop 110 with an output signal held at the high level H for a predetermined period of time. The flip-flop 110 is triggered by the trailing edge of an output of the flip-flop 108 to obtain an output signal which is held high for a predetermined period of time. The switching times are determined by the output signal of the multivibrator 110 . To simplify the explanation, it is assumed that the heads H1 to H4 and the heads H5 to H8 each have the same rotation phase and the switching elements 112 a, 112 b, 112 c and 112 d are switched on in the same timing, but actually the actual Switching times offset by the extent of a phase difference between the heads H1 to H4, so that each head records a pilot signal for tracking in the same phase.

The signals f1 and f2 switched by means of the switching elements 112 a, 112 b, 112 c and 112 d are fed to the adders 20 a, 20 b, 20 c and 20 d via connections 114 a, 114 b, 114 c and 114 d and recorded on the tape as shown in Fig. 8. That is, the signals f1 and f2 are recorded on the same track sections on tracks Tr1, Tr3 and Tr5 and on tracks Tr2, Tr4, Tr6, Tr7 and Tr8, respectively.

Next, a playback system will be explained. Fig. 9 shows as a first embodiment of the playback device a playback system which corresponds to the recording system of FIG. 3.

Output signals from the heads H1 to H8 are fed via switches 34 a, 34 b, 34 c and 34 d, which are controlled by the head switching pulses HSP, to playback amplifiers 36 a, 36 b, 36 c and 36 d, respectively. A track tracking circuit 38 for automatic tracking follows the output signals of the playback amplifier 36 a and 36 c a tracking control signal and this leads a tape drive control circuit 40 to. The tape drive control circuit 40 controls the rotation phase of a tape drive roller 42 in accordance with the tracking control signal so that each of the heads H1 to H8 sweeps a track from which can be reproduced. In particular, the tracking is not carried out as in the prior art, in which the head H1 inevitably scans the track Tr1, but is carried out in such a way that the head H1 sweeps over one of the tracks Tr1, Tr3, Tr5 and Tr7, on those with the same azimuth angle was recorded.

FIG. 10 shows an example of the track tracking circuit 38 shown in FIG. 9. According to FIG. 10, the outputs of the playback amplifiers 36 a and 36 c through ports 120 a, and 120b respectively fed to a circuit C1 and C2. Since the circuits C1 and C2 are constructed identically, only the circuit C1 is described in detail below.

Signal f2 is filtered out by a bandpass filter 122 in order to detect its level, and signal f1 is extracted by a bandpass filter 124 in order to determine its level. If the head H1 scans one of the tracks Tr1, Tr3 and Tr5 while the heads H1 to H4 scan the tape, the head H1 mainly receives the signal f1. For example, if the head H1 sweeps the track Tr3 as shown by Hta and Htb in Fig. 8, the signal f1 is mainly taken from the position Hta to the position Htb. A level comparator 126 outputs a square wave signal which indicates whether or not the detected level of the signal f1 picked out by the bandpass filter 124 is not lower than a predetermined threshold level. This signal is input to a terminal D of a D flip-flop 128 , the Q output signal of which is input into a terminal D of a D flip-flop 130 . The D flip-flops 128 and 130 are driven by a clock signal CLK with a sufficiently high frequency. The output signal of the D flip-flop 130 is delayed by one clock with respect to the output signal of the D flip-flop 128 . Therefore, by ANDing the Q output of the D flip-flop 128 with the Q output of the D flip-flop 130 in an AND gate 132 at the time of a leading edge of the above-mentioned square wave signal, a pulse can be obtained for one clock period. Likewise, by NOR gating the Q output of the D flip-flop 128 with the Q output of the D flip-flop 130 in a NOR gate 136, a pulse for one clock period is obtained at the time of a trailing edge of the above-mentioned square wave signal. That is, the AND gate 132 outputs a pulse to the time at where the head H1 reached the designated in Fig. 8 with Hta place while the NOR gate 136 outputs a pulse to the time at which the head H1, the reached in Fig. 8 designated Htb.

On the other hand, the output signals from the bandpass filter 122 for the detection of the level of the signal f2 are received and held in query / hold circuits 134 and 138 , which are switched by the output pulses from the AND gate 132 and the NOR gate 136 , respectively. That is, the level of the signal f2 from the previous track Tr2 taken from the head H1 at the position Hta and the level of the signal f2 from the subsequent track Tr4 taken from the head H1 at the position Htb , namely the levels of the signals from the areas shown by oblique lines in FIG. 8 are queried and stored. By applying the output signals of the query / hold circuits 134 and 138 to a differential amplifier 140 , a tracking error signal is emitted by the latter, which indicates the extent to which the position of the head H1 is offset with respect to the track Tr3 when it is scanned. At the same time, a track error signal for the head H3 with respect to the track Tr5 is obtained from the circuit C2 in the same way. The tracking control signal formed by adding these signals in an adder 142 is supplied to the tape drive control circuit 40 through a connector 144 .

Similarly, a tracking error signal is obtained from circuit C1 when head H1 or H5 is scanning close to one of the tracks Tr1, Tr3 and Tr5, while a tracking error signal is obtained from circuit C2 when head H3 or H7 is close to one of the tracks Scans tracks Tr1, Tr3 and Tr5. If heads H1 and H5 scan track Tr5, heads H3 and H7 sweep track Tr7. If heads H3 and H7 scan track Tr1, heads H1 and H5 sweep track Tr7. When the heads scan near the track Tr7, the signal f1 is not picked up at all and the polling / holding circuits 134 and 138 are not switched; but since the track error signal generated immediately before when the track Tr3 is scanned is recorded, a similar track error signal is formed. As a result, by controlling the band drive control circuit 40 with the tracking control signal from the terminal 144, the heads H1, H3, H5 and H7 are controlled so as to sweep one of the tracks Tr1, Tr3, Tr5 and Tr7, respectively. In this case, since the maximum tracking error is ± 1 track, the tracking control lock state can be reached very quickly.

According to FIG. 9, the output signals of the Wiedergabever become stronger 36 a, 36 b, 36 c and 36 d by digital demodulators 42 a, 42 b, 42 c and demodulated 42 d, after which the demodulated signals are supplied to a switch 44. A read / write memory (RAM) 46 is a memory for receiving playback data for one frame. The switch 44 is successively switched on for each cycle time for writing a word into the memory 46 . The cycle time of the memory 46 is in this case fixed to a quarter of the transmission time of 1-byte data in each channel, so that the output signals of the demodulators 42 a, 42 b, 42 c and 42 d appear to be parallel in the memory 46 be registered. In this case, a write address is determined for each playback head and a playback signal from a respective head is written into a predetermined address.

FIG. 11 is a timing chart illustrating the operation timing of each unit shown in FIG. 9. The figure shows write addresses WA1, WA2, WA3 and WA4 in the memory 46 for the output signals of the demodulators 42 a, 42 b, 42 c and 42 d and a read address RA in the memory 46 . Also shown in FIG. 11 are addresses h1 to h8 which determine the areas in memory 46 for storing the data for one track which were removed by means of heads H1 to H8. From Fig. 11, it can be seen that the reproduction signals from the heads H1 to H8 are serially output from the memory 46 . A read / write memory 52 executes processing to be completed in one frame period, such as error correction decoding and the like, and forms a storage device together with the memory 46 . If the track corresponding to the data output from the address h1 in the memory 46 is not set, the access time for a respective address cannot be set in a respective processing unit. In this embodiment, a playback track detection circuit 48 determines from which of the tracks Tr1 to Tr8, the heads H1 to H8 take the playback signals, and sets the output timing for a timing pulse to be supplied from a timing control circuit 50 to the memory 52 . The functions of the playback track detection circuit 48 and the timing control circuit 50 will be explained in detail below.

FIG. 12 is a circuit diagram showing an example of the playback track detection circuit 48 shown in FIG. 9. Fig. 12 shows an input terminal 150 for the head switching pulses HSP and a monostable stage 152 , which is triggered by the leading and trailing edges of the head switching pulses HSP. A monostable single-pulse flip-flop 154 is triggered by a trailing edge of the output of flip-flop 152 and outputs a pulse at the time when heads H1 through H8 each scan an area in which a pilot signal is recorded. As a result, the pulse has half the frame period. The output signals of the playback amplifiers 36 a to 36 d are respectively input at connections 156 a to 156 d. The signals entered at connections 156 a to 156 d are fed via bandpass filters 157 a to 157 d for reaching out signal f1, level comparators 158 a to 158 d, respectively. The level comparators 158 a to 158 d each output the high level H if the playback signal from a respective channel contains a signal f1 with a level which is not lower than a predetermined level, or the low level L if none such signal f1 is present. At a point in time at which a pilot signal is reproduced, the output signals of the level comparators 158 a to 158 d are buffer-stored in D flip-flops 160 a to 160 d, the output signals of which are delayed by half the frame period by D flip-flops 162 a to 162 d .

Q output signals D1, D2, D3 and D4 of the D flip-flops 160 a to 160 d and Q output signals D5, D6, D7 and D8 of the D flip flops 162 a to 162 d are supplied in parallel to a read-only memory (ROM) 164 . The read-only memory 164 is designed in such a way that, when the signals D1 to D8 correspond to the output signals of the heads H1 to H8, it outputs in three bits the number of a track which is being scanned with the head H1. For example, if the signals D1, D3 and D5 are at level H and the other output signals are at level L, output signals d1, d2 and d3 of the read-only memory become "0,0,1". Specifically, in this example, output signals D6, D7 and D8 indicate that heads H6, H7 and H8 scan tracks Tr6, Tr7 and Tr8, respectively (see Fig. 8). This simply determines that the head H1 scans the track Tr1. As a result, the RAM 164 outputs the three-bit binary number "0,0,1" in the form of the output signals d1, d2 and d3, which represents the number "1" corresponding to the track Tr1. When the signals D1, D5 and D7 are at level H and the other output signals are at level L, the output signals d1, d2 and d3 become "1,0,1". In this case, the output signals D2, D3 and D4 have the low level L. From the track arrangement shown in FIG. 8, it is therefore easy to see that the heads H2, H3 and H4 are just sweeping over the tracks Tr6, Tr7 and Tr8, respectively . As a result, the head H1 is scanning the track Tr5. The read-only memory 164 therefore outputs the three-bit binary number “1,0,1” in the form of the output signals d1, d2 and d3, which represents the number “5” corresponding to the track Tr5. The output signals d1, d2 and d3 are each temporarily stored on the trailing edge of the head switching pulse HSP in D flip-flops 166 a to 166 c, after which data are only output at connections 168 A to 168 C if the signals D1 to D8 are the output signals of the heads Correspond to H1 to H8. As a result, when the track just scanned by the head H1 is the track Trx within the frame, the three-bit data "x1, x2, x3" is output at the terminals 168 A to 168 C, the "x" in three Show bit.

FIG. 13 is a circuit diagram showing an example of the timing control circuit 50 shown in FIG. 9. Referring to FIG. 13, the data x1, x2 and x3 are from the reproducing track-Er-detection circuit 48 at terminals 170, 172 and 174 give inserted, while the head switching pulses HSP is input to a terminal 176th A phase locked loop circuit or PLL circuit 178 for doubling the frequency of the head switching pulses HSP outputs an output signal designated HSP × 2 in FIG. 13. If the detection circuit 48 detects that the head H1 is scanning the track Tr1, so that the signal x3 is "1" (= H1) while the signals x1 and x2 are "0" (= L), the signals HSP and HSP × 2 are emitted by antivalence elements 180 and 182, respectively. Therefore, a timing control signal TC output from an AND gate 186 becomes a signal TC1 shown in FIG. 11. In a similar manner, when the detection circuit 48 determines that the head H1 is currently scanning the track Tr3, Tr5 or Tr7, output signals TC3, TC5 or TC7 according to FIG. 11 are obtained from the AND gate 184 . Furthermore, if the head H1 is currently scanning the track Tr2, Tr4, Tr6 or Tr8, the AND gate 184 does not emit an output signal since x3 = "0". This is because when the head H1 is just sweeping a track with an even number, normal playback does not take place and therefore no signal processing is required.

For example, if the head H1 is scanning the track Tr7, the obtained data x1 = x2 = x3 = "1", so that the SpeI cher as a timing signal through a terminal 186 which is supplied in Fig. Signal TC7 shown 11 52. The memory 52 is designed such that it sequentially executes processing completed within one frame of the data written in a predetermined address from the track Tr1 in accordance with the fall time of an output signal of the timing circuit 50 . In this case there is an access from a read signal from the address h3 of the memory 46 , which is a reproduction signal of the head H3. At this time, since the track Tr1 is scanned by the head H3, the memory 52 can process data for one frame which is identical to that in the recording.

By accessing the memory 52 , an error correction processing, an arrangement changeover and the like are carried out by an error correction decoder 54 which speaks the error correction encoder 8 according to FIG. 3, and serial digital video signals are input to a serial processing circuit 56 . In the processing circuit 56 , processing is carried out which is opposite to that of the serial processing circuit 4 shown in FIG. 3. For example, digital pulse code modulation decoding, interpolation, digital / analog or D / A conversion and the like are carried out. The video signal output in this way from the serial processing circuit 56 is output to the outside via a connection 58 .

With the design of the reproduction described above every second track is a control target the tracking control so that the settling time in controlling for the tracking lock state becomes extremely short. This will be a period of time  extraordinarily short during which the serial video signals can not be reproduced and it can emerge reproduced video signals can be achieved.

2nd embodiment

Fig. 14 shows the configuration of a reproducing system as a second embodiment of the reproducing device. The recording system shown in Fig. 3 is assumed. In FIG. 17, the same components as those shown in FIG. 9 are denoted by the same reference numerals and are not described in detail below.

Shift memories (FIFO) 60 a to 60 d can each take the data taken from a respective head for 1/4 full frame. When the data contained in the reproduced signals from the heads H1 to H4 cher simultaneously in the Schiebespei 60 a are enrolled to 60 d, this data frame is reproduced during their heads H5 to H8 in a period eighth during the time, d sequentially read out from the shift memories 60 a to 60 also registered data contained in the playback signals of the heads H5 to H8. In this case, a switch 62 is switched on for a period of one eighth frame in the sequence a → b → c → d. The data contained in the reproducing signals of the heads H5 to H8 are sequentially read out during the time during which the heads H1 to H4 are reproduced. The data output by the switch 62 thereby become serial data which are completely identical to the data read out from the memory 46 in the exemplary embodiment according to FIG. 9.

A characteristic signal detector 64 picks up the synchronization blocks containing the characteristic signals ID from the demodulator 42 a and takes out the data which represent the track numbers within a frame in the characteristic signals ID. The identification signal detector 64 then selects only the data from the playback signal of the head H1 from data for the track numbers corresponding to the head switching pulses HSP and supplies it to the timing control circuit 50 as parallel 3-bit data. The output signal of the identification signal detector 64 for the timing control circuit 54 thus becomes identical to the output signal of the playback track detection circuit 48 according to FIG. 9. The function of the output signal in the timing control circuit 50 is also the same.

In the second embodiment described above can have the same functions and services as with the memories go beyond the first embodiment capacity can be reduced. Therefore there is a price favorable design. Since also be accepted can that originally for any other purpose Identification signal detector is provided, by using it for the track detection of the circuit structure be simplified. Since also for the playback track orken do not use the pilot signals for the tracking control can be drawn, the recording pattern of the pilot signals have two-track periodic throughout, so that for example on the track Tr7 in the first embodiment Signal f1 can be recorded. This will make one high-precision tracking control enables without a Recording after a complicated tracking pattern is required.  

3rd embodiment

Fig. 15 shows the design of a playback system of a digital video tape recorder as a third embodiment of the playback device. As in the second embodiment, the design of a recording system is assumed to be that shown in Fig. 3 and the same components as those in Fig. 9 are given the same reference numerals.

A read / write memory 72 of FIG. 15 is a memory which can record the data for at least three half frames. In this third embodiment, it is assumed for the sake of simplicity that the memory 72 can hold the playback data for two frames. An address control circuit 70 controls the read addresses of the memory 72 . Fig. 16 is a time chart for explaining the operation of the address control circuit 70.

It is assumed that the addresses of the memory 72 have areas h1-1 to h8-1 for storing the playback data from the respective heads H1 to H8 for a first frame and areas h1-2 to h8-2 for storing the playback data from the respective heads H1 through H8 for a second frame. Here, as in the first exemplary embodiment, the memory 72 is apparently written in parallel on four channels, the write addresses for the playback signals on each channel being determined in accordance with the head switching pulses HSP as shown by WA-1 to WA-4 in FIG. 16 .

On the other hand, the read addresses are determined by the 3-bit data from the playback track detection circuit 48 . That is, when the output signals x1, x2 and x3 of the reproduction track detection circuit 48 are "0,0,1", namely, it is determined that the track scanned by the head H1 is the track Tr1, read addresses RA-1 in Fig. 16 chosen. Likewise, when it is determined that the reproduction track of the head H1 is the track Tr3, Tr5 or Tr7, the addresses RA-3, RA-5 or RA-7 shown in Fig. 16 are selected as read addresses.

As a result, the data read out from the memory 72 immediately after a trailing edge of the head switching pulse HSP is the data which was taken from the track Tr1. As a result, in the memory 52, the access time for the signal processing to be completed in one frame period can always remain constant starting from the head switching pulses HSP. This results in the same signal processing timing as in the case that the head H1 is brought on the track Tr1 by the tracking control.

In the third embodiment described above will also have the same benefits as the first Embodiment achieved. In addition, the signal always process when recording and playing back is executed in accordance with the head switching pulses HSP, is the playback device according to the third embodiment example particularly suitable for the case that multiple devices operated under synchronization.

4th embodiment

The Fig. 17 (A) and 17 (B) show a fourth Ausführungsbei the reproduction device match, the head assembly of a multi-channel digital data recording apparatus. Of FIG. 17 (A) 1 has six rotary heads are arranged H1 to H6 at a rotating drum. The heads H1 to H3 and the heads H4 to H6 are each arranged in such a way that the phase difference between adjacent heads is Θ °.

A sufficiently small value is chosen as Θ and the respective three heads are arranged in the distance in this way net that they sweep a tape almost simultaneously. The heads H4 to H6 are with a phase difference of Rotated 180 ° with respect to the heads H1 to H3, so that heads H1 to H3 and heads H4 to H6 alternate selectively one over an angular range of at least 180 ° scan the magnetic tape applied to the drum and dreikana lig recorded or played back.

As shown in Fig. 17 (B), heads H1, H3 and H5 have the same azimuth angle, while H2, H4 and H6 also have the same azimuth angle which is different from that of the heads H1, H3 and H5. As a result, the so-called azimuth recording is carried out.

Fig. 18 shows a track pattern recorded on a magnetic tape T by the heads shown in Figs. 17 (A) and 17 (B). Tr1 to Tr6 denote tracks which are recorded by means of heads H1 to H6, respectively. By moving the heads H1 to H3 over the tape from the positions labeled H1 to H3 in the direction obliquely upwards in FIG. 18, three-channel recording is carried out, the tracks Tr1 to Tr3 being formed.

Fig. 19 shows schematically the design of a digital data recording device as an embodiment. According to FIG. 19, data is received from the outside via a network interface 202 and released to the outside. Further, the Figure 19 shows, a read / write memory 204 with large SpeI cherkapazität, error correction encoding and -decodier circuit and error correction circuit 206 and a central processing unit (CPU) 208.

Data entered via the network interface 202 are stored in the memory 204 via a data bus Db, after which, after the addition of an error correction code (ECC) in the error correction circuit 206, the data containing the error correction code three recording processing circuits 210 a, 210 b and 210 c be fed. Addresses in the memory 204 , which are retrieved from the network interface 202 , the error correction circuit 206 and the recording processing circuits 210 a, 210 b and 210 c, are transmitted via an address bus Ab.

Fig. 20 shows a concrete example of the recording processing circuits 210 a, 210 b and 210 c of Fig. 19. The data containing the error correction code is input from the data bus Db at a terminal 250 . The inputted data are fed to a summing circuit 251 and assembled with the characteristic data ID described below.

The head arrangement of the digital data recorder according to this embodiment is that shown in Figs. 17 (A) and 17 (B) described above. A head switching pulse generator 216 of FIG. 19 generates rectangular head switching pulses HSP, which drop at the times when the heads H1, H2 and H3 start to scan the tape T, and increase at the times when the heads H4, H5 and H6 begin to scan tape T. Referring to FIG. 20, the head switching pulse HSP is inputted to a terminal 252. An addressing circuit 253 determines, in accordance with a clock signal CLK with a frequency corresponding to the data clock and in accordance with the head switching pulses HSP, an address in the memory 204 which is called up by the recording processing circuit 210 . An output signal of the addressing circuit 253 is transmitted via a connection 255 to the address bus Ab, whereby the reading of the data from the respective address in the memory 204 is commanded. The three recording processing circuits 210 a, 210 b and 210 c, the error correction circuit 206 and the network interface 202 call up the memory 204 , these calls or accesses being carried out by a worker (not shown) in chronological succession.

The addressing data output by the addressing circuit 253 is also input into an identification signal generator 254 , which generates additional data or characteristic data including the data (described in detail below) for the address and supplies them to the summing circuit 251 .

The main information data are output from the summing circuit 251 via the network interface 202 , the error correction code and the data containing the characteristic data ID and, after processing, such as digital modulation and the like, is further output in a data processing circuit 255 at an output connection 256 as a digital signal which outputs the recording editing circuit 210 .

The digital signals output in three channels from the recording processing circuits 210 a, 210 b and 210 c are mixed in mixing stages 212 a, 212 b and 212 c in time division multiplexing with a pilot signal that a pilot signal generator 218 generates.

FIG. 21 is a circuit diagram showing an example of the pilot signal generator 218.

Fig. 21 shows an input terminal 400 for the head switching pulses HSP, an oscillator 402 for generating a signal hereinafter referred to as f1 with the frequency f1 and an oscillator 404 for generating a signal hereinafter referred to as f2 with the frequency f2.

Switches 406 a, 406 b and 406 c are switched to a position H if the head switching pulse HSP is at high level H and into a position L if the head switching pulse HSP is at low level L. The switching times of switching elements 412 a, 412 b and 412 c are determined by monostable multivibrators 408 and 410 . The flip-flop 408 is triggered by the leading and trailing edges of the head switching pulses HSP and supplies the flip-flop 410 with an output signal which is held high for a predetermined time. The flip-flop 410 is triggered by the trailing edge of the output of the flip-flop 408 to obtain an output signal which is held high for a predetermined time. The switching times are determined by the output signal of the multivibrator 410 . To simplify the explanation, it is assumed that the heads H1 to H3 and the heads H4 to H6 each have the same rotational phases and that the switching elements 412 a, 412 b and 412 c are switched through at the same time, but the switching times are actually the same a phase difference between the heads H1 to H3 offset such that each head records a pilot signal for tracking in the same phase.

The signals f1 and f2 switched through by the switching elements 412 a, 412 b and 412 c are fed via connections 414 a, 414 b and 414 c to the mixing stages or adders 212 a, 212 b and 212 c and are similar to the illustration on the tape recorded in Fig. 8. That is, the signals f1 and f2 are recorded on the same portions of each track on the tracks Tr1, Tr3 and Tr5 and the tracks Tr2, Tr4 and Tr6, respectively.

The digital signals are via recording amplifiers 214 a, 214 b and 214 c and via switches 220 a, 220 b and 220 c, which are switched to positions R during recording, in time division multiplexing, each with a pilot signal in head switches 222 a, 222 b and 222 c entered. The head switches 222 a, 222 b and 222 c are switched at low level L of the head switching pulses HSP to terminals L and at high level H of the head switching pulses HSP at terminals H and the digital signals of the three channels are recorded in such a way that according to the illustration 18 three tracks are formed with three heads in FIG .

Next, the function will be explained during playback. The output signals from the heads H1 to H6 are via the head switches 222 a, 222 b and 222 c, and via connections P to the switches 220 a, 220 b and 220 c, respectively, reproducing amplifiers 224 a, 224 b and 224 c.

A track tracking circuit 226 forms a tracking control signal corresponding to the output signal of the playback amplifier 224 a, which is fed to a tape drive control circuit 228 . In accordance with the tracking control signal, the tape drive control circuit 228 controls the rotation phase of a tape drive roller 230 such that the heads H1 to H6 each pass over a track from which can be reproduced. Specifically, the tracking control is not, as in the prior art, such that the head H1 inevitably scans the track Tr1, but is performed such that the head H1 sweeps either the track Tr1 or the track Tr3 or Tr5, which has the same azimuth angle as that Have track Tr1.

As Spurnachführschaltung 226 of FIG. 19, a scarf can be used tung, which is equal to the circuit shown in Fig. 10 C1. Therefore, by driving the tape drive control circuit 228 with a tracking error signal from the tracking circuit 226, the heads H1, H3 and H5 are controlled such that they cover one of the tracks Tr1, Tr3 and Tr5, respectively. Since the maximum track error is ± 1 track, a tracking control engagement state can be achieved very quickly.

According to FIG. 19, the output signals of the Wiedergabever become stronger 224 a, 224 b and 224 c are each a reproduction Ausbe reitungsschaltung 232 a, b supplied to c 232 and 232, respectively. From the reproduction processing circuits 232 a, 232 b and 232 c, data including the error correction codes (ECC) are written into the memory 204 , in which the error correction is carried out by means of the error correction circuit 206 . The network interface 202 reads only the main data from the memory 204 and releases it to the outside.

A pattern for data storage areas and their addresses in memory 204 is shown in FIG . In Fig. 22 are A-1 to A-8 ranges to those described in the processing circuit recording Aufberei associated data to be processed 210 a, namely below ten than A channel data denote data on the tracks Tr1 and Tr4 are recorded, each of areas A-1, A-2. . . A-8 can record the data for one track. Likewise, memory areas B-1 to B-8 are provided for the B-channel data to be processed in the recording processing circuit 210 b, and storage areas C-1 to C-8 are to be processed in the recording processing circuit 210 c Allocated C-channel data, with each memory area capable of holding data for a single track.

The address data that the previously described recording processing circuits 210 a, 210 b and 210 c deliver to the address bus Ab contain at least the above-mentioned area numbers. Specifically, the address data contains higher-value bits (as identification addresses) which indicate the numbers 1 to 8 of the respective areas and lower-value bits (sub-addresses) which correspond to addresses within the respective area. If during recording the recording processing circuit 210 a for example in the area A-1 retrieves the call on drawing-conditioning circuits 210 b and 210 c, respectively, the areas B-1 and C-1 from. This means that the areas with the same number 1 to 8 are called up at the same time as the identification address after the channel designation A to C. The inscription from the network interface 202 into the memory 204 is also carried out simultaneously with respect to the areas A-1, B-1 and C-1.

On the other hand, during the playback when the data is written into the memory 204 by the respective playback processing circuit 232 a, 232 b and 232c, the data are forcibly written into an area with a matching number or channel designation. FIG. 23 shows an example of the playback processing circuits 232 a, 232 b and 232 c according to FIG. 19.

Referring to FIG. 23, a digital signal of the reproducing amplifier input from a terminal 260 to a. The input signal is converted back to the original data by a data processor 261 , which contains a digital demodulator. A characteristic data extraction circuit 262 takes out the characteristic data ID described above and restores an address in the memory 204 for the output as address data, which address was called up during the recording. The playback conditioning circuits 232 a, 232 b and 232 c determine the access addresses for access to the memory 204 in accordance with the restored address data. Assuming that no adder 264 is provided, the data including the error code, which are output from the playback processing circuits 232 a, 232 b and 232 c each at a connection 268, are given to the output at a connection 267 Address data is written into areas that are the same as the areas in which the data was stored in memory 204 during recording. This has the following effects:
As described above, the tracking circuit 226 controls that the head H1 scans one of the tracks Tr1, Tr3 and Tr5. When the head H1 scans the track Tr1 as shown by H1 in FIG. 18, the reproduction processing circuits 232 a, 232 b and 232 c write the data into areas on the same channel as during the recording, with the identification addresses 1 to 8 are identical, which select the playback conditioning circuits 232 a, 232 b and 232 c. However, when the head H1 scans the track Tr3, the heads H4, H5 and H6 each scan tracks as shown by H4 ', H5' and H6 'in Fig. 18, so that when the playback processing circuit 232 a outputs the data read out from the area C-3 during the recording, the reproduction processing circuits 232b and 232c output data which was read out from the area A-4 and B-4 during the recording. Therefore, the data from these three playback processing circuits 232 a, 232 b and 232 c change channels and become data that are relatively offset in time. This also occurs when the head H1 sweeps the track Tr5. Here, the heads H4, H5 and H6 digits H4 '', H5 '' and H6 '' according to Fig. 18.

However, with such a design that the data is returned to the area in the memory 204 where it was stored during the recording, the arrangement of the data read from the network interface 202 can be the same as the arrangement of the data input to the network interface 202 Data will. That is, the network interface 202 sequentially retrieves the memory 204 in accordance with the identification addresses 1 to 8 and a predetermined time control suitable for an external device and only the data from the areas A-1, B-1 and C-1 need to be Memory 204 (or more specifically the data sequences) are forcibly released to the outside at the same time. Furthermore, even if the processing unit of the error correction circuit 206 detects multiple areas, the error correction is possible by easy access to the same addresses as during the recording.

As a result, as described above, by returning the respectively reproduced data to the area in the memory 204 in which the data was stored during the recording, with respect to the tracking control, the reproduction becomes possible provided that each head scans a track, the Azimuth matches that of the head.

However, since there is an access address in the network interface through downstream circuit stages like an external one Device or the like is determined and the identification addresses of each channel can only be changed sequentially, the following problems can arise:

It is assumed that the characteristic addresses the preparation circuits the reproduction on 232 a, 232 b and dial 232 C, the regions C-1, A-2 and B-2 are the identification addresses, which selects the network interface 202, the areas A-2, B-2 and C-2, and the sub-address that selects the network interface 202, precede the sub-addresses, dial the Playb-conditioning circuits 232 b and 232 c. In this case, the data read out from the areas A-2 and B-2 and the data read out from the area C-2 are staggered in time by a period close to a single read cycle of the memory 204 . Furthermore, in the data recorder according to the embodiment, the error correction circuit 206 also calls the memory 204 . Therefore, the network interface must be 202 after the data from either the reproduction processing circuits 232 a, 232 b and 232 c of the memory or are written 204 to retrieve the data after the elapse of the processing time of the error correction circuit 206th Otherwise, the network interface 202 reads data on which no error correction or incomplete error correction has been carried out.

The playback device according to the embodiment is therefore designed in such a way that the identification addresses can be shifted, which select the playback processing circuits 232 a, 232 b and 232 c. This process is explained below.

From the address data which the characteristic data extracting circuit 262 of FIG. 23 outputs, the 3-bit data corresponding to the characteristic addresses 1 to 8 described above are output via a connection 263 to a control bus Cb. The identification addresses 1 to 8 of the access addresses of the network interface 202 are also applied to the control line Cb. The central unit 208 compares this data and issues a command to the playback processing circuits 232 a, 232 b and 232 c for such a displacement of the access addresses that between the access addresses of the network interface 202 and the access addresses of the playback processing circuits 232 a, 232 b and 232 c there is no connection that causes the problems described above.

Assuming that the processing time of the error correction circuit is the time for three tracks, namely the data access time for one identification address, then no problem arises if a identification address An, which the network interface 202 selects, by at least "3" in relation is delayed to a identification address Aa, which selects the playback processing circuit 232 a. Accordingly, if Aa-An is less than or equal to "2", the identification addresses Aa, Ab and Ac of the playback processing circuits 232 a, 232 b and 232 c must be offset.

The function of the central unit 208 for this purpose is explained using the flow diagram in FIG. 24. If playback has started (step S1), the characteristic address is first added to the network interface 202 (step S2), after which further through the terminal 263, the characteristic address Aa of the reproduction processing circuit 232 is added to a (step S3). It is then determined whether or not the difference (Aa-An) between these addresses is at least "3" (step S4). If the difference is at least "3", the process returns to step S2 via step S6. If the difference is less than or equal to "2", a command to move or change displacement data is issued via a connection 266 to a displacement data generator 265 of each reproduction processing circuit 232 a, 232 b and 232 c (step S5) . The offset data generator 265 generates 2-bit data, for example, which are added in the adder 264 to the two most significant bits of the 3-bit data for the identification addresses. If the offset data are successively changed by "1", the identification addresses Aa, Ab and Ac of the reproduction processing circuits 232 a, 232 b and 232 c are offset by "2". The process then returns to step S2 via step S6, after which the same process is repeated. If (Aa-An) is still less than or equal to "2", the identification addresses Aa, Ab and Ac are offset by "2". Step S6 is a step of waiting until the end of the reproduction.

With the design described above, the timing of the writing of the data from the reprocessing processing circuits 232 a, 232 b and 232 c into the memory 204 , the retrieval of the data by the error correction circuit 206 and the reading of the data by the network interface 202 avoided the problems described above.

Although it was assumed that an offset level of the identification addresses Aa, Ab and Ac of the playback processing circuits 232 a, 232 b and 232 c is "2", the same effect can be expected if the level "1" or "4th""is. However, if the processing unit of the error correction TIC 206 of six tracks two identification addresses comprising (six areas of FIG. 22) and the address that selects the Fehlerkorrek turschaltung, is not displaced, no error correction is possible if the displacement unit or Ver reduction stage " Is 1 ". Therefore, the offset unit for the identification addresses in the respective reproduction processing circuit must be "2" or "4". Similarly must then, when the processing unit of the error correction circuit 206 detects twelve tracks be the displacing unit for the characteristic addresses of each playback processing circuit "4".

Since every second track is a tracking control target in the digital data recorder according to the exemplary embodiment, the settling time for tracking is extraordinarily short and identical reproduction is possible regardless of which target track a respective head is controlled to. It is also possible to freely select the times of the data output from the network interface 202 to the external device in accordance with the request of the external device.

A digital da ten recorder for simultaneous recording or Playback on three channels is described, however, the same effects in general by applying the Design according to the invention in a digital signal re- delivery device achievable, the simultaneous playback executes on n channels, where n is equal to or greater than "2" is.

It becomes a device for the reproduction of digital informa tion of a record carrier with a variety parallel tracks on which the digital informa tion as digital signals for n channels are, where n is greater than or equal to "2". The digital Signals for the n channels are generated with n playback heads decreased. The contained in the picked up signals digital information is stored in a storage device saved. For determining which of the accepted digital signals for the n channels each playback identifying heads, recognition data is generated. Correspond The time of access is based on the identification data an access device that the storage device for Performing predetermined processing in the memory retrieves stored digital signals, with respect to the playback time of the by means of the n playback heads reproduced digital information controlled.

Claims (6)

1. Device for reproducing digital information from a recording medium which has a plurality of parallel tracks on which digital information is recorded as digital signals for n channels, where n is equal to or greater than 2, with
n playback heads (H) for receiving the digital signals for the n channels,
a storage device ( 204 ) for storing the digital information contained in the digital signals picked up by the n playback heads and
a first access device ( 206 ) for access to the storage device for carrying out a predetermined first processing of the digital information stored in the storage device, characterized by
a second access device ( 202 ) for access to the storage device for executing a predetermined second processing of the digital information stored in the storage device,
a comparison device ( 208 ) for comparing write addresses when the digital information taken off by means of the n playback heads is written into the storage device with access addresses for access to the storage device by the second access device and
an address shifter ( 232 , 265 ) for shifting the access addresses for access to the memory device by the access device in accordance with an output signal of the comparison device, the address shifting device shifting the access addresses using a size corresponding to the digital information of n tracks as a unit. 2. Device according to claim 1, characterized in that the first access device contains an error correction circuit ( 206 ) for performing an error correction on the digital information stored in the memory device ( 204 ) and that the second access device ( 202 ) has an interface for outputting the contains digital information stored in the storage device to a remote site. 3. Device according to claim 1 or 2, characterized in that the first access device ( 206 ) queries the storage device ( 204 ) using a size corresponding to the digital information of (n × j) tracks as a unit, j being a unit is an integer that is at least equal to 2, and that the address shifter ( 232 , 265 ) offsets the access addresses for access to the memory device as a unit by specifying the size corresponding to the digital information from the (n × j) tracks. 4. Device according to claim 3, characterized in that the digital information includes image information and that image information recorded on (n × j) tracks correspond to a full screen. 5. Device according to one of claims 1 to 4, characterized featured, that the digital signals for n channels each on n tracks the plurality of tracks are recorded and that the n Playheads are arranged so that adjacent n Scan tracks from the multitude of tracks. 6. Device according to claim 5, characterized by a track control device ( 38 ) for controlling the relative position between the recording medium and the n playback heads, the track control device controlling one of the n playback heads such that it sweeps over one of m adjacent tracks of the plurality of tracks, where m is less than n.