DE3935829C2 - Linearization control loop - Google Patents

Description

The invention relates to a linearization control loop Self-adjustment to correct the frequency response of a voltage-dependent oscillator (VCO) in a frequency mo system according to the preamble of the patent Proverb 1. Such a control loop is from the US PS 4,367,473 already known.

Linearization control loops of the type mentioned are used in used for example in frequency modulated systems. Because of their applicability come in such systems they z. B. in the field of ammunition and in radar systems to use.  

Linearization control loops for linearization of the modulation characteristic of modulators are generally known. For example, from the US Pat. No. 4,593,287, from DE 27 10 841 A1 and from the article by D. R. Bromaghim and J.P. Perry: "A Wideband Linear FM Ramp Generator for the Long-Range Imaging Radar "; in: IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-26, No. 5, May 1978, pages 322-325 Linearization control loops known, in which the target-actual comparison and thus the linearization of the modulation characteristic by means of a run timers is performed.

From the article by B. D. Campbell: "Hig-Resolution, Radar Coherent Linear FM Microwave Source "; in: IEEE Transactions on Aerospace and Electronic Systems, Vol. AES-6, No. 1, January 1970, pages 62-72 a linearization control loop is known in which the linearization of the Modulation characteristic is achieved by comparing the spectra.

In the linearization control loop of the aforementioned US PS 4,367,473 finds both a calibration of the transmission frequency as well the modulation characteristic is linearized. The linearization the modulation characteristic is in this solution with several, on un tuned resonant circuits through different resonance frequencies performed, which in the course of the linearly increasing, for example Modulation characteristic are excited one after the other and the signals for provide the target-actual comparison from which the control signal for the line Arization of the modulation characteristic is derived. Disadvantage of this The solution is that the linearization is only given for certain ones Frequencies occur and the intervals between these frequencies only can be "linearized" by interpolation.

The invention has for its object a Lineari create a control loop of the type mentioned at the outset, which enables preferably non-linear modulation characteristics, for example a frequency-modulated Sy stems, possible in a simple and inexpensive manner linearize as precisely as possible.

The arrangement according to the invention and its corresponding Further training should be easy to manufacture, inexpensive and be implemented in a material-saving manner.

The achievement of the object is in Pa Claim 1 described. In the subclaims are advantageous training and further developments of the invention executed.

A major advantage of the invention is that they operate over a wide temperature range can.

On the basis of this solution concept, a corresponding material-saving, inexpensive and easily producible arrangement according to the invention - which satisfies the task and the solution concept - can be produced. This is characterized in particular by its high linearity error correction (residual error according to the corresponding regulation 0.2%). Other advantages are
that the control loop is self-equalizing, so that a correction of a frequency response, for example in a voltage-dependent oscillator (VCO), it automatically follows,
that the control loop enables phase coherence to be created in the VCO, for example,
that the control loop enables an operating point setting in the VCO, while this VCO is tuned to a reference frequency in the calibration phase.

The invention is explained in more detail below with reference to FIGS. 1 to 5. Show it:

Fig. 1 is a block diagram of an advantageous exporting approximate shape of the inventive arrangement;

Fig. 2 is a VCO with the frequency divider;

Fig. 3 is an FM-CW radar;

Fig. 4 is a modulation signal to the associated control pulses;

Fig. 5 is a circuit diagram of a frequency voltage converter;

Fig. 6, the transfer function of the circuit of Fig. 5.

The control circuit of the invention according to Fig. 1 consists of a phase comparator 21, to whose first input 15, a reference signal is applied. This phase comparator 21 is connected in series with a low-pass filter 22 . Its output is connected to a first input of a sample 23 (gain V = 1). This output is in turn connected to an amplifier 24 , the output of which rests on a first input of a first summation point. The output 10 of the first summation point is connected to the input of a VCO 703 , from whose output 12 or 11 the resulting frequency of the arrangement according to the Invention can be tapped. At the same time, this output 12 is connected to the input of a frequency voltage converter 26 and to a second input of the phase comparator 21 .

The output of the frequency / voltage converter is switched to a low-pass filter 27 and this to an amplifier 28 . The output of this amplifier 28 is connected to a first input of a subtractor 210 and to the first input of a sample 29 . The output of this sample is connected to the second input of the subtractor 210 and to the input of an amplifier 214 . The output of the sub tracer 210 is connected to the first input of a differential amplifier 211 . Its output is connected to a first input of a controller 212 . The output of the controller 212 is connected to a first input of a further summation point. Its output is connected to a modulation signal amplifier. The output of the modulation signal amplifier is switched to the second input of the further summation point. The output of amplifier 214 is connected to a second input of a reference signal generator 216 . A controller 215 consists of an integrated control signal processing and an integrated counter. A clock of a clock generator (not shown) is present at one input 16 of the controller 215 . A starter pulse is preferably present at the other input 17 of the controller 215 .

A first output of the control is connected to the reference signal generator, the output of which is connected to a second input of the differential amplifier. Furthermore, this output is connected to an auxiliary variable processing circuit (V <1), the output of which is connected to a second input of the further summation point. The second output of the controller 215 is connected to a second input of the controller 212 . The third output of the controller 215 is connected on the one hand to a second input of the sample 29 and on the other hand to a second input of the sample 23 .

The first input of the subtractor 210 and the differential amplifier 211 has a positive sign. The associated second input has inverse polarity. The controller 212 consists of a switchable integrator.

Optionally, an arrangement according to FIG. 2 or 3 can also be formed on the connecting terminals 10 , 11 , 12 instead of the VCO 703 .

Fig. 2 shows a VCO with divider, the input of the VCO 701 to terminal 10 and its output to terminal 12 and connected to the input of an N-fold Tei 71 . Its output is connected to terminal 11 .

Fig. 3 shows an FM-CW radar, wherein at terminal 10, a VCO is connected on the input side 702nd The respective VCO 702 is connected to terminal 12 via the respective direct branch of the second coupler ( 720 and 721 ) and a circulator 73 lying in series therewith. The not from closed arms of the couplers 720 and 721 are each connected to a first input of a mixer 741 and 740 a related party. A local oscillator (LO) is connected to the second input of mixer 741 and another output of circulator 73 is connected to the second input of mixer 740 . Via an N-fold divider 75 , the mixer 741 is connected to terminal 11 . The output of the mixer 740 is connected to a further connection terminal 13 .

Fig. 4 shows the timing of the modulation signal and the control signal of the arrangement according to the invention. Curve 31 shows the modulation signal with the modulation phase 302 , period 303 and pause 301 .

Curve 32 shows the start pulses which are at the beginning of the modulation phase 302 .

Curve 33 shows the samples that begin at the end of modulation phase 302 .

At the same time, the control signal integrator of controller 212 starts. This is reset to zero at the end of each break.

In curve 33 , the sample phases have the number 331 and the hold phases have the number 332 .

FIG. 5 shows the structure of the frequency-voltage converter 26 and FIG. 6 the associated transfer function.

The frequency-voltage converter is made of a series scarf tion of n interverters based on an AND gate are switched on. On the complementary entrance the same gate is a connecting line between this input and the input of the first inverter forms.

Analogously, the circuit 602 is only formed with m inverters. The input of this circuit 602 is functionally connected to that circuit 601 described above via a further inverter. The outputs on the circuits 601 and 602 are connected to an output 14 via a NAND gate 603 .

In Fig. 6, the characteristic of the circuit of FIG. 5 is provided. Curve 350 shows the theoretical curve and curve 351 the factual curve. This results in a usable frequency range 360 .

The linearization control loop is shown as a block diagram in FIG. 1. The function of the control loop is divided into two sections, which run sequentially in time. A calibration (self-adjustment) is provided in the second section of the modulation period 303 , while the modulation phase 302 takes place in the first section, in which the frequency-modified oscillator signal is readjusted by closing the control loop. The control and temporal relationships are shown in Fig. 4 Darge.

Calibration (self-alignment) of the PLL:
The upper part of the block diagram ( Fig. 1) represents in principle a phase-locked loop which is to be calibrated to a reference frequency f _Ref = f₀ during the pause time 301 . The special feature is that this phase control loop can be closed via the sample 23 during the pause time 301 . In this way, the VCO 703 can preferably settle to f₀ in the correct phase. Furthermore, this phase locked loop has a summation point into which a modulation signal can be fed. During the calibration phase of the phase control loop, it is ensured that the modulation _voltage U _mod2 = 0 (ideally). In this way it is ensured that at the end of the calibration phase (sample pulse) the operating point (ie U _arb ) of the VCO is adjusted. _Any error _size that is present, ie U _mod2 ≠ 0 (deviating slightly from zero due to e.g. offset voltages of various operational amplifiers 29 , 210 , 212 , 213 ), is also compensated for during the calibration process. The course of U _mod2 is shown in Fig. 4. At the end of the calibration process or at time t₀, a signal locked to the input frequency f₀ is thus present at the output of the VCO. When used in an FM-CW-Ra device, this ensures that a constant initial phase is present at the beginning of the modulation phase (phase coherence).

Linearization control loop:
The actual linearization control loop - as shown in FIG. 1 - initially requires an input voltage U _{f / U (t)} which is proportional to the input frequency. This is generated with the aid of the frequency-voltage converter 26 and a post-screening (module 27 ). The function and mode of operation of these components 26 and 27 are shown in FIGS. 5 and 6 and explained further above. With the help of the amplifier 28 , this voltage U _{f / U (t) is} initially increased to improve the signal-to-noise ratio of this magnitude. Since the voltage U _{f / UV (t)} (see Fig. 5) f O depending on the intended initial frequency = the starting time of the Modulati t₀ onsphase not equal to 0, is determined using the sample amplifier 29 initially during the dead time 301, the output voltage U _{f / U ( t₀)} saved. In this way, U _{f / V (t₀)} = OV is generated for the pause at the output of subtractor 201 by subtraction. For the modulation phase 302 , this measure has the consequence that the characteristic curve was made at the first point, which enables a comparison of the frequency-dependent voltage U _{f / U (t)} with a reference voltage, which is generated in the controller 215 and the reference signal generator 216 is produced.

This first section can be mathematically described as follows when using the designations from FIG. 4

For the synchronism of the two comparison variables, which requires a second adjustment cut (2-point ab equal). The relationships here apply:

for the max. Frequency f _max = f 1 applies

or

 · V₈ · c = · c

Here is a measurable quantity that is pending during the pause time 301 and is stored in the sample 29 . This size can vary with z. B. change the temperature. The factor c is a system constant) in which the max. Frequency swing (f₁ - f₀) is inserted. Two variants are now possible for equalization (2nd adjustment point):

• a) is about a gain variation corrected so that the following applies: = const.
• b) the size (c) is used to readjust the reference (reference value). Here, c practically represents a gain of. Transferred to Fig. 1, this means that V₁₄ = c must be selected.

The possibility b) was applied here, since this solution is simple to implement, if the D / A converter stone in building 216, this voltage is obtained as the operating voltage or Refe rence voltage, so that the variation of this size corresponds to the direction indicated in the block diagram multiplication. In the practical case, variations of A₁₄ (see Fig. 3) can be expected from:

A₁₄ = V₁₄ · = U _nominal (setpoint)
Deviation from the target value:
A₁₄ = U _nominal ± 10%

A change in the gain of amplifier 28 , e.g. B. over temperature, by inexact adjustment, etc., is also corrected in the manner described above by a After equal to the command variable V _FÜ .

In the further course of the control loop, the reference variable U _{FÜ is} compared in the differential amplifier 211 with the processed actual value U _{f (t)} and an error function is formed. In addition, this difference is amplified in the differential amplifier 211 with V₁₁ (control loop gain). The result is the error quantity U _F , which controls the controller 211 , so that a correction voltage U _{corr is} formed in this way. An auxiliary variable is added to the controller 212 so that the required dynamics of the differential amplifier 211 and the controller 212 can be reduced. In this way, the modulation signal U _{mod1 is produced} , which can be fed to the VCO after amplification in the modulation signal amplifier 213 .

In FIG. 2, a variant is shown in which the VCO 701 oscillates at a higher frequency (N · f₀). In Fig. 3 an application is shown, which is connected by mixing down into an intermediate frequency position with subsequent frequency division to the linearization control loop. The basic frequency of the VCO is then:

f _VCO = f _LO + N · f₀.

By designing the invention as described above exercise are the ones already mentioned in the solution Advantages.

Claims (6)

1. Linearization control circuit for linearizing the modulation characteristic of a modulator, which control circuit contains a comparison unit for comparing an actual signal derived from the output signal of the modulator with a predetermined reference signal, which comparison unit is connected to the control input of the modulator, characterized in that

• - That the output of the modulator ( 703 ) is connected to a frequency-voltage converter ( 26 ),
• - That the frequency-voltage converter ( 26 ) on the output side is connected on the one hand to a sample-and-hold amplifier ( 29 ) and on the other hand to the one input of a subtractor ( 210 ),
• - That the sample-and-hold amplifier ( 29 ) is connected on the one hand to the other input of the subtractor ( 210 ) and on the other hand via a amplifier ( 214 ) to the reference signal generator ( 216 ),
• - That the subtractor ( 210 ) is connected on the output side to one input of the comparison unit ( 211 ) and the reference signal generator ( 216 ) is connected on the output side to the other input of the comparison unit ( 211 ),
• - That the sample-and-hold amplifier ( 29 ) is closed on the input side at the beginning of each modulation period and is open on the input side during the remaining time of the modulation period.

2. Linearization control loop according to claim 1, characterized in that the comparison unit ( 211 ) is a differential amplifier, which is followed by an integrator ( 212 ) and a further summer, that the reference signal generator ( 216 ) via an attenuator ( 217 ) with the further summer is connected and that from the two further summers supplied output signals of the integrator ( 212 ; U _corr ) and the reference signal generator ( 216 ; U _auxiliary ), preferably via a downstream additional amplifier ( 213 ) to be amplified, modulation control signal (U _mod2 ) is formed. 3. Linearization control loop according to one of claims 2 or 3, characterized in that the reference signal generator ( 216 ) is a counter ( 215 ) with a downstream D / A converter ( 216 ). 4. Linearization control circuit according to one of the preceding claims, characterized in that the frequency-voltage converter ( 26 ) has a low-pass filter ( 27 ) and an amplifier ( 28 ) is switched downstream. 5. Linearization control loop according to one of the preceding claims, characterized in that the modulation control signal (U _mod2 ) is fed to the control input ( 10 ) of the modulator ( 703 ) via a first summer. 6. Linearization control loop according to one of the preceding claims, characterized in that the modulator ( 703 ) is a voltage-controlled oscillator and the first totalizer is part of a phase-locked loop ( 15 , 21-24 ) for the voltage-controlled oscillator ( 703 ).