DE3926165A1 - Transmitter-receiver arrangement as microprocessor interface - has control logic and register for programmed operation from coupled microprocessor - Google Patents

Abstract

A microprocessor (12) is coupled to an interface (14) in a module that has receiving and transmitting capabilities for communication with system modules. The connector is established by data, address and control bus lines (16,18,20) and the interface is clock driven (22). Receive channels (26,28) connect with a word address decoder, a direct access memory (34,40), receiver control logic, command register for programming the unit and a status register coupled to the microprocessor. The transmitter (42) has a direct access memory (46), control logic, command register and status register. ADVANTAGE - Reduces complexity and cost of system.

Description

Technical field

The invention relates to a transmitter and receiver arrangement as an interface to a microprocessor, via which with Word addresses provided by the microprocessor can be sent out or fed to the microprocessor.

Underlying state of the art

For data exchange between microprocessor-controlled electronic devices are the data words that go through a Bus are transmitted, with word addresses ("labels") verse hen. These word addresses indicate for which electro African device or which devices have the relevant data word is determined. For this data transmission there is in the Aviation technology is a standard called "ARINC 429".

In the case of known devices, the test is carried out to determine whether a specific data word for a specific microprocessor controlled device is determined by the microprocessor itself. That means that all occurring Data words must be fed to the microprocessor. The Microprocessor checks the word address of each one Data word thereupon whether this data word for him is determined. This makes the microprocessor very powerful burdened and disturbed in its actual task. It  is also known for identifying data words to provide separate electronics.

Finally, it is known to provide a module that allows to recognize a single data address and Data words with this data address to a microprocessor forwards.

The microprocessor-controlled device not only receives Data words. It also sends data words to other devices. These data words are also with a word address provided in accordance with the aforementioned ARINC standard. It is known a building block for this purpose a single Word can be passed from the microprocessor. This Word is then sent from the block.

The individual known components need to be used comprehensive control. Receive and transmit channels are mixed differently in individual building blocks. The known modules have no connection with the microprocessor bus is compatible.

The decoding of the word addresses for that by the Blocks received data word on hardware, namely additional electronic circuits is very complex. The additional electronic circuits require a lot of space. In addition, the cost of such is additional Electronic circuits high. In addition, hardware and Software to be manufactured separately. That creates problems in production, because hardware and software work together have to be adjusted. Particular difficulties arise yourself in the event of changes.

The decoding of the word address by the microprocessor requires a lot of additional work for the  Microprocessor. This will make the Mikropro work cessors disturbed. The work of the microprocessor must be done in Intervals between two milliseconds and three hundred Microseconds are interrupted, namely every time a new data word appears. An alternative would be one additional microprocessor with associated peripherals. That is a considerable additional effort.

Disclosure of the invention

The invention is based on the task of an 8 component to create the one that is programmable, the one with the Microprocessor bus is compatible and the microprocessor of the work of sending and receiving data words and relieved of their identification. The block should be in the application does not change the state of hardware and Make software necessary and for the different Requirements of the particular special application be programmable.

According to the invention this object is achieved in that The following elements are integrated in a module (ASIC):

• a) A microprocessor bus interface with Data lines, address lines and control lines,
• b) clock generator means,
• c) several reception channels, each with
  • a word address decoder memory for more than one word address,
  • a direct access memory for double access once from receiving logic or from the microprocessor,
  • -a reception control logic,
  • a command register for the programming of the special mode of operation of the receiving channel in question by the microprocessor and
  • a status register by means of which information about the current working state of the receiving channel can be transmitted to the microprocessor,
• d) several transmission channels with
  • a direct access memory for double access once from the microprocessor and once from a transmission logic,
  • -send control logic,
  • -a command register for programming the special mode of operation of the transmission channel concerned and
  • a status register through which information about the current working state of the transmission channel can be transmitted to the microprocessor,
• e) a command register for the entire module and
• f) a status register for the entire block.

In this way, there is a building block that as Interface to the microprocessor is used and is programmable. The block is still with the  Microprocessor bus compatible. It relieves the Microprocessor largely from processing incoming data words and the identification of their Word addresses. The microprocessor only needs that Access the block's direct access memory. It is no state adaptation between hardware and software required. The block can be used for the respective Programmed requirements of special applications will.

The channels can be designed or programmable so that they work at clock rates in the megahertz range. The module is therefore also suitable for applications outside of ARINC 429 standard suitable. The block can then especially for fast communication between different systems of microprocessors used will.

The microprocessor bus interface can be programmable optionally for data buses with different numbers of Bits can be designed, for example for data buses eight or sixteen bits.

The control signals of the microprocessor bus interface can by PIN programming ("PIN PROGRAMMING") adapted to different types of microprocessors will.

Furthermore, the clock generator means can be programmed in this way be that each of the receive and transmit channels one desired clock rate independent of the other reception and broadcast channels can be issued. For this purpose, the Clock generator means several clock generators with up to contain two external crystals.  

A receiving channel is advantageously for processing of sequences of data words ("STRING WORD") with the same Word address but different data contents set up. When a word address is recognized decoding at a certain place in the word addresses Store the received data word in one Data words long shift register direct access memory ("FIFO") can be entered. In the status register and a corresponding pin can be on a pin of the module Information is generated when the shift register Random access memory is full.

The module can be used to test the module during operation be trained that all reading registers of the block also are writable, each transmission channel from the microprocessor each receiving channel is switchable and the Send function can be prevented from the outside. This can the building block through a program of the microprocessor in its full function can be checked. Until Partial failures can be localized at the channel level. It can error detection can also be checked.

The space required and the number of blocks is reduced. Compared to the known hardware solutions, namely either the Decoding by a separate electronic circuit or decoding by an additional microprocessor, there is a reduction in costs and a reduction decoration of volume and weight. There is also a increased reliability. The building block is easier too test and maintain. The manageability of the interface is simplified.

Two embodiments of the invention are below with reference to the accompanying drawings  explained.

Brief description of the drawings

Fig. 1 shows the configuration of a module with a transmitter and receiver arrangement with two inputs and one output.

Fig. 2 shows the configuration of a module with a transmitter and receiver arrangement with four inputs and two outputs.

Preferred embodiments of the invention

In Fig. 1, 10 is a block (ASIC). The module 10 works together with a microprocessor 12 .

The module contains a microprocessor bus interface 14 with data lines 16 , address lines 18 and control lines 20 . The data lines 16 , address lines 18 and control lines 20 are connected to the microprocessor 12 . The module 10 also contains a clock generator 22 . The clock rate of the clock generator 22 is stabilized by an external quartz crystal 24 . The module 10 has a first receive channel 26 and a second receive channel 28 . The receive channels contain data words and associated word addresses from a demodulator 30 . The first receive channel 26 contains receive logic 32 and a direct access memory 34 for double access once from the receive logic 32 and once via the microprocessor bus interface 14 from the microprocessor 12 . The first receive channel also includes a shift register direct access memory 36 , which is able to hold several data words, namely sixteen data words according to the ARINC standard.

The second receive channel 28 also contains a receive logic 38 . Furthermore, the second receiving channel 28 contains a direct access memory 40 for double access, also once from the receiving logic 38 or from the microprocessor 12 .

A transmission channel 42 sends data words to a modulator 44 . The transmission channel contains a transmission logic 46 . Furthermore, the transmission channel 42 contains a shift register direct access memory 46 . The shift register random access memory 46 is also set up for double access once by the microprocessor 12 and once by a transmission logic 46 .

Specifically, the receive logic 32 of the first receive channel 26 includes a word address decode memory for more than one word address and receive control logic. The first receiving channel 26 further includes a command register for programming the receiving channel 26 by the microprocessor. Finally, the first receive channel contains a status register, by means of which information about the current working state of the receive channel 26 can be transmitted to the microprocessor 14 . This is not shown in detail in Fig. 1.

Similarly, the receive logic 38 of the second receive channel 28 includes a word address decode memory for more than one word address and receive control logic. The second receive channel contains a command register for programming the functioning of the second receive channel 28 by the microprocessor. Finally, the second receiving channel 28 also contains a status register, by means of which information about the current working state of the receiving channel 28 can be transmitted to the microprocessor 12 . This is also not shown in detail in FIG. 1.

The transmission logic 46 of the transmission channel 42 contains a transmission control logic. Furthermore, the transmission channel 42 contains a command register for programming the functioning of the transmission channel by the microprocessor and a status register, by means of which information about the current working state of the transmission channel can be transmitted to the microprocessor.

In addition, module 10 contains a command register for the entire module and a status register, also for the entire module.

The receive channels 26 and 28 and the transmit channel 42 are designed or programmable in such a way that they also operate at clock rates in the range of megahertz.

The microprocessor bus interface 14 is programmable, optionally for data buses with different numbers of bits. Furthermore, the control signals of the microprocessor bus interface 14 can be adapted to different types of microprocessors 12 by pin programming. The clock generator means then represented here by the clock generator 22 are programmable in such a way that each of the receive and transmit channels 26 , 28 and 42 can be given a desired clock rate independently of the other receive and transmit channels. For this purpose, the clock generator means can contain several clock generators with up to two external crystals 24 .

The receiving channel 26 is set up for processing sequences of data words with the same word address but different data contents (“string words”). Upon detection of a word address at a particular location in the word address decoding memory, the received data word is entered into the shift register random access memory 36 . Corresponding information is generated in the status register and on a pin of the block 10 when the shift register random access memory 36 is full.

All test registers of the module 10 can also be written to for testing the module 10 in operation. The transmission channel 42 can be switched on by the microprocessor 14 to each reception channel 26 or 28 . The transmission function is prevented from doing so.

The described transmitter and receiver arrangement with the microprocessor 12 and module 10 works as follows: The microprocessor 12 first configures the command register once for the desired mode of operation. For example, the clock rate of twelve kilohertz, the parity bit as "odd" and the number of bits used to decode the word addresses are set to eight or eleven bits. The word addresses which are to be received are programmed in the word address decoding memory. That can be up to sixteen or thirty-two word addresses per channel. The incoming serial data word is converted into a parallel data word. The receive logic 32 or 38 examines for errors, for example for clock errors, an incorrect number of bits, gap errors or parity errors. The result is entered in an intermediate register. Then the word address, possibly including the "SDI" bits, is compared to those stored in the word address decode memory. If the pattern of the word address is in the word address decoding memory, the word is written to the appropriate location in the random access memory 34 . For example, the third digit in the word address decoding memory corresponds to the third digit in the random access memory. The order corresponds to the order in which the word addresses are stored in the word address decoding memory. If there are no errors, the word address is also transferred to the direct access memory. If an error is found, the error decoding is passed instead of the word address. The previous parity bit is set to "one". Corresponding reception information is given in the status register.

The received and selected data words are available in the direct access memory 34 to the microprocessor 12 for reading out. This reading can take place independently of the receipt of the information, ie "asynchronously". The microprocessor can access the information when it is required for its work. The work of the microprocessor 12 need not be interrupted by the arrival of information.

Information that is not read out is overwritten (updated) at the relevant point in the random access memory when new information with the same word address is received. Reading the information sets the content of the random access memory 34 to zero at the relevant point. This enables an update test.

The receiving channel 28 works in the same way.

The transmission channel 42 works as follows: The microprocessor 12 first configures the command register of the transmission channel 42 once. For example, a transmission clock of 12 kilohertz is specified, the parity bit is specified as straight, etc.

The microprocessor 12 then sends a packet of up to sixteen data words to be transmitted to the transmission channel 42 . The data words are sorted by the microprocessor 12 . The microprocessor 12 also sets the timing to achieve the update rates for the various word addresses. The data words are entered into the shift register random access memory 46 . The transmit control logic sets the "FIFO" not empty in the status register. The transmit control logic then causes the contents of the shift register random access memory 46 to be sent . This is done without control by the microprocessor 12. The parity bit is added during transmission. After this operation has been carried out, the information "FIFO empty" is set in the status register and on a pin of the module 10 .

In the block 10 shown in FIG. 1, the input channel 26 contained a word address decoding memory of 16 data words. The reception channel 26 is set up to receive "string words" with 16 data words. The random access memory 34 stores 15 data words. The shift register random access memory is sixteen data words deep.

At the input channel 28 , the word address decoding memory has a storage capacity of sixteen data words. The direct access memory 40 also has a memory capacity of 16 data words.

The shift register random access memory 46 of the output channel 42 is sixteen data words deep.

A block built in this form has one Complexity of about 10,000 gates and was in 2 µ Technology in an area of 96 square millimeters realized.

The module 48 shown in FIG. 2 has four receive channels 50 , 52 , 54 and 56 and two transmit channels 58 and 60 . The microprocessor is designated by 62 . The device contains a microprocessor bus interface 64 .

The microprocessor bus interface 64 is connected to the microprocessor 62 via data lines 66 , address lines 68 and control lines 70 . With 72 clock generator means are designated.

The first receive channel 50 includes a random access memory 74 corresponding to the random access memory 34 in FIG. 1 and a shift register random access memory 76 which corresponds to the shift register random access memory 36 of FIG. 1. The reception logic of the first reception channel 50 is designated by 78 . The first receive channel 50 works like the receive channel 26 in the module 10 from FIG. 1.

The remaining receive channels 52 , 54 and 56 contain receive logic 80 , 82 and 84 and random access memories 86 , 88 and 90 , respectively. The direct access memories 86 , 88 and 90 , like the direct access memory 74 for double access, are set up once by the reception logic 80 , 82 , 84 or 78 or by the microprocessor 62 . Otherwise, the receive channels 52 , 54 and 56 operate in the same way as the receive channel 28 of FIG. 1. The receive channels 52 , 54 and 56 contain data words from a demodulator 92 .

The two transmission channels 58 and 60 each contain a transmission logic 94 and 96 and a shift register direct access memory 98 and 100, respectively. The two transmission channels 58 and 60 operate in the same way as the transmission channel 42 of FIG. 1. The transmission channels 58 and 60 transmit data words to a modulator 102 .

In the embodiment of Fig. 2, receive channel 50 includes a word address decode memory for sixteen words. The shift register random access memory 76 has a storage capacity of sixteen words. The random access memory 54 has a memory capacity of fifteen words (each according to the Arinc 429 standard).

The word address decoding memory of the receiving channel 52 stores 32 words. The word address decode memories of receive channels 54 and 56 each store sixteen words. The direct access memory 86 of the receive channel 52 has a memory capacity of 32 words, the direct access memory 88 and 90 of the receive channels 54 and 56 each have a memory capacity of sixteen words.

In transmit channels 58 and 60 , shift register random access memories 98 and 100 are sixteen words deep, respectively. A module 48 of this type has a complexity of approximately 30,000 gates and was implemented in 0.7 μ technology on an area of 86 square millimeters.

Claims (10)

1. Transmitter and receiver arrangement as an interface to a microprocessor, via which data words provided with word addresses can be sent by the microprocessor or fed to the microprocessor, characterized in that the following elements are integrated in a module (ASIC):

• a) a microprocessor bus interface ( 14 ) with data lines ( 16 ), address lines ( 18 ) and control lines ( 20 ),
• b) clock generator means ( 22 ),
• c) at least one receiving channel ( 26 , 28 ) with each
  • a word address decoder memory for more than one word address,
  • a direct access memory ( 34 , 40 ) for double access once from a receiver logic ( 32 , 38 ) or from the microprocessor ( 12 ),
  • -A reception control logic
  • a command register for the programming of the special mode of operation of the receiving channel in question by the microprocessor and
  • a status register by means of which information about the current working state of the receiving channel can be transmitted to the microprocessor,
• d) at least one transmission channel ( 42 ) with
  • a direct access memory ( 46 ) for double access once from the microprocessor ( 12 ) and once from a transmission logic ( 46 ),
  • -send control logic,
  • a command register for programming the special mode of operation of the transmission channel in question by the microprocessor and
  • a status register through which information about the current working state of the transmission channel can be transmitted to the microprocessor,
• e) a command register for the entire module and
• f) a status register for the entire block.

2. Transmitter and receiver arrangement according to claim 1, characterized in that the channels ( 26 , 28 , 42 ) are designed or programmable so that they also work with clock rates in the range of megahertz. 3. Transmitter and receiver arrangement according to claim 1, characterized in that the microprocessor bus interface ( 14 ) is programmably designed optionally for data buses with different numbers of bits. 4. Transmitter and receiver arrangement according to claim 3, characterized in that the control signals of the microprocessor bus interface ( 14 ) can be adapted to different types of microprocessors by pin programming. 5. Transmitter and receiver arrangement according to one of claims 1 to 4, characterized in that the clock generator means ( 22 ) are programmable so that each of the receive and transmit channels ( 26, 28 and 42 ) a desired clock rate independently of the other reception - And broadcast channels can be issued. 6. Transmitter and receiver arrangement according to claim 5, characterized in that the clock generator means ( 22 ) contain a plurality of clock generators with external crystals ( 24 ). 7. Transmitter and receiver arrangement according to one of claims 1 to 6, characterized in that a receiving channel ( 26 ) is set up for processing sequences of data words with the same word address but different data contents. 8. Transmitter and receiver arrangement according to claim 7, characterized in that upon detection of a word address at a specific location in the word address decoding memory, the received data word is entered into a shift register direct access memory ( 36 ) which is several data words long. 9. transmitter and receiver arrangement according to claim 8, characterized in that in the status register and on  a corresponding pin of the block Information is generated when the shift register Random access memory is full. 10. transmitter and receiver arrangement according to claim 9, characterized in that for testing the module in operation

• a) all reading registers of the module are also writable,
• b) each transmission channel ( 46 ) from the microprocessor ( 12 ) can be switched to each reception channel ( 26 , 28 ) and
• c) the transmission function can be prevented from the outside.