DE3918475A1 - DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control - Google Patents

DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control

Info

Publication number
DE3918475A1
DE3918475A1 DE19893918475 DE3918475A DE3918475A1 DE 3918475 A1 DE3918475 A1 DE 3918475A1 DE 19893918475 DE19893918475 DE 19893918475 DE 3918475 A DE3918475 A DE 3918475A DE 3918475 A1 DE3918475 A1 DE 3918475A1
Authority
DE
Germany
Prior art keywords
access
logic
page
dram
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19893918475
Other languages
German (de)
Inventor
Christoph Dipl Ing Legutko
Doris Rauh
Erwin Dipl Ing Thurner
Thomas Dipl Ing Niedermeier
Eberhard Dipl Ing Schaefer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19893918475 priority Critical patent/DE3918475A1/en
Priority to JP2147173A priority patent/JPH0325786A/en
Publication of DE3918475A1 publication Critical patent/DE3918475A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

The circuit provides side- or line-bound access to memory cells of a DRAM. On the RAM chip (1) is provided a memory logic (2), extended by a comparison logic (4). The latter contains a comparator (41) and a control (42). The actual line address is compared with a preceding one. The logic of the control decides a page access and a page cycle start on the address coincidence. On the address difference, first the actual access is terminated prior to the following access processing. The resulting access delay is reported by the comparison logic by an access delay marking signal. The latter is transmitted for further processing. ADVANTAGE - Reduction of mean access time by rapid, successive page mode application.

Description

Die vorliegende Erfindung betrifft eine Schaltungsanordnung zur Durchführung des seiten- oder zeilengebundenen Zugriffs (Page-Mode) auf die Speicherzellen eines dynamischen RAM-Bau­ steins (DRAM).The present invention relates to a circuit arrangement to perform page or line access (Page mode) on the memory cells of a dynamic RAM build stone (DRAM).

Um den Page-Mode bei DRAM-Bausteinen anwenden zu können, ist eine Logik nötig, die erkennt, ob eine aktuelle Adresse mit der zeitlich vorhergehenden Adresse identisch ist. Diese Logik muß dann entsprechend die Zeilenadreßauswahl- und Spaltenadreß­ auswahl-Zeitsteuerung (RAS- und CAS-Timing) bewirken. Wegen des damit verbundenen zusätzlichen Logik-Aufwands wird der Page-Mode derzeit nur in wenigen Fällen ausgenützt.In order to be able to use the page mode for DRAM chips, is a logic is necessary which recognizes whether a current address with the previous address is identical. That logic must then the row address selection and column address accordingly effect selection time control (RAS and CAS timing). Because of of the associated additional logic effort is the Page fashion is currently only used in a few cases.

Der vorliegenden Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung zu schaffen, mittels derer eine Verkürzung der mittleren Zugriffszeit dynamischer RAM-Bausteine (DRAMs) bei schnell aufeinanderfolgenden Speicherzugriffen durch Ver­ wendung des "Page-Mode" bei einfachem und flächensparendem Schaltungsaufbau erzielbar ist.The present invention has for its object a To create circuit arrangement by means of which a shortening the average access time of dynamic RAM chips (DRAMs) in the case of rapidly successive memory accesses by Ver Use of "page mode" with simple and space-saving Circuit structure can be achieved.

Die Aufgabe wird durch eine Schaltungsanordnung der eingangs genannten Art und gemäß dem Oberbegriff des Patentanspruchs 1 gelöst, die erfindungsgemäß durch die kennzeichnenden Merkmale bestimmt ist.The task is accomplished by a circuit arrangement of the beginning mentioned type and according to the preamble of claim 1 solved, the invention by the characterizing features is determined.

Durch das Einlesen der vollständigen Adresse läßt sich der Zu­ griff erheblich gegenüber einem Multiplexbetrieb steigern. Das "RAS- und CAS-Timing" wird vollständig von der integrierten Logik übernommen.By reading the complete address, the Zu handle significantly increase compared to a multiplex operation. The "RAS and CAS timing" is fully integrated by the Logic adopted.

Im folgenden wird die Erfindung anhand einer ein bevorzugtes Ausführungsbeispiel betreffenden Figur im einzelnen beschrie­ ben.In the following, the invention is based on a preferred one Described embodiment example in detail  ben.

Die Figur zeigt ein Blockschaltbild, das den Aufbau eines DRAM-Bausteins mit automatischer Page-Mode-Steuerung veran­ schaulicht.The figure shows a block diagram showing the structure of a Initiate DRAM device with automatic page mode control clear.

In der gezeigten Schaltungsanordnung zur Durchführung des sei­ ten- oder zeilengebundenen Zugriffs (Page-Mode) auf die Spei­ cherzellen eines dynamische RAM-Bausteine (DRAM), ist vorgese­ hen, daß die auf dem Chip 1 des RAM-Bausteins angeordnete Spei­ cherlogik 2 in der angegebenen Weise um eine Vergleichslogik 4 erweitert ist, die einen Vergleicher 41 und eine Steuerung 42 enthält. Durch Vergleich einer aktuellen Zeilenadresse mit der dieser zeitlich vorhergehenden Zeilenadresse mittels des Ver­ gleichers 41 wird durch die Logik der Steuerung 42 entschie­ den, daß bei Gleichheit der Zeilenadressen der Page-Zugriff und der Page-Zyklus angewendet werden und bei Ungleichheit der Zeilenadressen zuerst der aktuelle Zugriff beendet wird, bevor der folgende Zugriff abgearbeitet wird. Die Vergleichslogik 4 meldet die daraus resultierende Zugriffsverzögerung durch ein diese Zugriffsverzögerung kennzeichnendes Signal, welches Si­ gnal aus dem Chip zur Weiterverarbeitung ausgegeben wird.In the circuit arrangement shown for carrying out page or line-bound access (page mode) to the memory cells of a dynamic RAM module (DRAM), it is provided that the memory logic 2 arranged on the chip 1 of the RAM module is in a comparison logic 4 , which contains a comparator 41 and a controller 42 , is expanded in the manner indicated. By comparing a current row address with that preceding row address by means of the comparator 41 , the logic of the controller 42 decides that if the row addresses are the same, the page access and the page cycle are used, and if the row addresses are not the same, the current one is used first Access is ended before the following access is processed. The comparison logic 4 reports the resulting access delay by means of a signal which characterizes this access delay and which signal is output from the chip for further processing.

Gemäß dieser Schaltungsanordnung wird die im Multiplexbetrieb erforderliche Zeilenadreßauswahl-(RAS-) und Spaltenadreßaus­ wahl-(CAS-) Zeitsteuerung vollständig von der integrierten Lo­ gik des Bausteins, nämlich "on-chip", durchgeführt.According to this circuit arrangement, it is in multiplex mode required row address selection (RAS) and column address Choice (CAS) time control completely from the integrated Lo gik of the block, namely "on-chip" performed.

Claims (2)

1. Schaltungsanordnung zur Durchführung des seiten- oder zei­ lengebundenen Zugriffs (Page-Mode) auf die Speicherzellen eines auf dynamische RAM-Bausteine (DRAM), dadurch gekennzeichnet, daß die auf dem Chip (1) des RAM-Bausteins angeordnete Speicherlogik (2) um eine Vergleichs­ logik (4) erweitert ist, die einen Vergleicher (41) und eine Steuerung (42) enthält, wobei durch Vergleich einer aktuellen Zeilenadresse mit der dieser zeitlich vorhergehenden Zeilen­ adresse mittels des Vergleichers (41) durch die Logik der Steuerung (42) entschieden wird, daß bei Gleichheit der Zei­ lenadressen der Page-Zugriff und der Page-Zyklus angewendet werden und bei Ungleichheit der Zeilenadressen zuerst der ak­ tuelle Zugriff beendet wird, bevor der folgende Zugriff abge­ arbeitet wird, und daß die Vergleichslogik (4) die daraus re­ sultierende Zugriffsverzögerung durch ein diese Zugriffsver­ zögerung kennzeichnendes Signal meldet, welches Signal aus dem Chip zur Weiterverarbeitung ausgegeben wird.1. Circuit arrangement for carrying out page or line-bound access (page mode) to the memory cells of a dynamic RAM modules (DRAM), characterized in that the memory logic ( 2 ) arranged on the chip ( 1 ) of the RAM module A comparison logic ( 4 ) is added, which contains a comparator ( 41 ) and a controller ( 42 ), by comparing a current row address with the row address preceding this in time by means of the comparator ( 41 ) by the logic of the controller ( 42 ) it is decided that if the row addresses are the same, the page access and the page cycle are used and if the row addresses are not the same, the current access is ended first before the following access is processed, and that the comparison logic ( 4 ) determines the resulting access delay by a signal characterizing this access delay reports which signal is emitted from the chip for further processing is given. 2. Schaltungsanordnung nach Anspruch 1, dadurch gekennzeichnet, daß die im Multiplexbetrieb er­ forderliche Zeilenadreßauswahl-(RAS-) und Spaltenadreßauswahl (CAS-)Zeitsteuerung vollständig von der integrierten Logik des Bausteins, nämlich "on-chip", durchgeführt wird.2. Circuit arrangement according to claim 1, characterized characterized in that he multiplexed Required row address selection (RAS) and column address selection (CAS) time control completely from the integrated logic of the module, namely "on-chip", is performed.
DE19893918475 1989-06-06 1989-06-06 DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control Withdrawn DE3918475A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19893918475 DE3918475A1 (en) 1989-06-06 1989-06-06 DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control
JP2147173A JPH0325786A (en) 1989-06-06 1990-06-04 Circuit equipment for page mode access of dynamic ram module to memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19893918475 DE3918475A1 (en) 1989-06-06 1989-06-06 DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control

Publications (1)

Publication Number Publication Date
DE3918475A1 true DE3918475A1 (en) 1990-12-13

Family

ID=6382200

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19893918475 Withdrawn DE3918475A1 (en) 1989-06-06 1989-06-06 DRAM page mode circuit - has DRAM chip memory logic extended by comparison logic with comparator and control

Country Status (2)

Country Link
JP (1) JPH0325786A (en)
DE (1) DE3918475A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2759195A1 (en) * 1997-02-04 1998-08-07 Sgs Thomson Microelectronics Address changing detection circuit for EPROM cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2759195A1 (en) * 1997-02-04 1998-08-07 Sgs Thomson Microelectronics Address changing detection circuit for EPROM cell
US6104644A (en) * 1997-02-04 2000-08-15 Sgs-Thomson Microelectronics S.A. Circuit for the detection of changes of address

Also Published As

Publication number Publication date
JPH0325786A (en) 1991-02-04

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