DE3916322A1 - Control appts. for microprogrammed data programming system - Google Patents

Abstract

Upon each machine instruction the start addresses of a microinstruction memory and a memory operand address memory are prepd. and made effective depending on a control signal indicating completion of the previous elementary operation.$ If the durations of elementary operations for control processing of successive elementary operations or decision parameter prepn. for the first operation are insufficient, a machine instruction is read from a special memory (PECM-M) immediately on release of the start address and before the preceding instruction's last operation.$

Description

The invention relates to a method and an arrangement for Control of the timely decision process and the parameters provision of microprogrammed machine instruction sequences according to the preamble of claim 1.

The performance of a central unit is u. a. very much dependent on how much time the processor has to execute a machine command needed. When microprogrammed in the usual way Controlled machine instructions are for execution a machine instruction one or more elementary operations needed, with the micro-commands for each Elementary operations successively a corresponding microinstruction memory be removed. A starting point for the increase The performance therefore consists in the shortening of the cycle time for the elementary operations, resulting in the progressive Circuit technology is favored. On the other hand, though through the cable lengths between the individual modules conditional transmission time of the signals less strongly influenced is, result in shortening the cycle time for the Elementary operations are increasingly experiencing difficulties because the remaining times for the derivation of decisions and control signals and dependent thereon response times, for example, to provide the right parameters, no longer sufficient. This is especially true of the end a machine instruction and when operand conflicts occur decisions to be taken and their impact on the Parameter supply.

The result is additional loss elementary operations for time-over, which is the execution of a machine command  lengthen and therefore shorten the cycle time intended performance improvement for the elementary operations pick up again. This is especially true for only one or two elementary operations of existing machine instructions.

The object of the invention is therefore to provide a method and an arrangement to create, despite increasing shortening of the Cycle time for the individual elementary operations the execution times for the individual machine commands not by unnecessary Loss elementary operations are extended, but by timely, tuned to the duration of the elementary operations Decision processes with timely parameter provision to predetermined drain states in a suitable manner is reacted.

This object is in the method according to the invention the principle according to the characterizing features of the patent claim 1 solved.

The starting point for the new procedure is one beside the Microinstruction memory provided control store, like the Micro-command memory each driven with the same starting address but only the ones for the decisions and Parameter deployment necessary parts of the associated microinstruction from the micro-instruction memory. In addition, the control store does not contain all the microinstructions in microinstruction memory entries, but only to the Microinstructions for the first elementary operation of a every machine command immediately by the start address is addressable.

Because of the consequent lower storage capacity for This memory can be used as a memory if necessary with a faster one Access time can be used. In addition, the can It read control information directly for the flow control be made available before this on the off Although read the micro-instruction memory simultaneously, but in the  With regard to the associated elementary operation to be performed normally react later released microinstruction can. Enable the control information from the control store therefore a decoupling from that with regard to the associated Elementary operation predetermined clock-bound treatment the actual microinstructions.

By the very early in the last elementary operation of a Machine command available control information can z. In the execution of only one elementary operation existing machine instructions with memory access these memory accesses already in the run to the corresponding elementary operation be triggered so early that they with the predetermined takeover act received by the memory controller before the parameters are near the end of one Change elementary operation, which in execution only in the associated elementary operation due to the shortening of the cycle time would not be possible and to a loss elementary operation would lead.

Developments for the method according to the invention result from the subclaims 2 to 11:

Thus, for example, the early provision of the control information even if it consists of several elementary operations Machine instructions is possible are in the micro-instruction memory in addition to any microinstruction, also the required control information stored from the respective following microinstruction, so that it can be used in the forerunner.

For memory accesses also the associated memory address In time to the function code available, is in the lead for the first elementary operation immediately provided Memory start address bypassing the address calculator and in the run to subsequent elementary operations then the in Intermediate register of the address calculator available in time Address switched through as memory address.  

Analogously, it is possible to react to operand conflicts earlier and the necessary reading of the operand still in the last Elementary operation of a machine instruction to be executed, so that only a loss elementary operation arises instead of hitherto corresponding to three loss elementary operations in the solution DE-PS 36 03 240.

Switching to the respective competent, already in the flow The available tax information can be as before dependent from a the last elementary operation of a machine instruction characterizing control bit in the read from the micro-instruction memory Micro command done in conjunction with the positive Result of a test that may have been performed actual end of the microinstruction indicating signal in which triggers in each case the last elementary operation.

For a series of possibly necessary control reactions this time is too late. Therefore, in the Advance to the actual end signal already an early end signal before the beginning of the last elementary operation of a machine instruction that creates the initiation of the earlier becoming necessary Control function takes over.

However, the determination of the early end signal is only with machine commands with unconditional end of command or with more than one Element operations existing machine instructions, at which the respective sequence of microinstructions by a the unconditional end characterizing microinstruction is completed, readily possible without delay. This is not true for example, only one or two elementary operations existing machine instructions with conditional command end too. In In this case, the conventional control of the microinstruction sequences via a branch in a microinstruction with microprogrammed unconditional end to additional, the processing power cause mitigating loss element operations. The As a result, power losses are significant, since just the proportion of only one or two elementary operations  existing machine commands is usually particularly large. According to a development of the invention according to claim 9 will therefore be the actual last one in these cases Elementary operation of a machine instruction based on additional Control information from the control store determined directly and the early end signal in time to the last to this EO generated.

A corresponding circuit arrangement according to the invention arises from the features of claim 12, while the further claims 13 to 18 are based on developments refer to this arrangement.

An essential component is the addition to the actual Microinstruction memory provided for the timely control store Providing the required tax information, not just memory starts for operand retrieval can be triggered earlier, but also on the end of machine commands and operand conflicts can be responded in a timely manner, so that despite the Shortening the cycle time for the individual elementary operations Loss elementary operations are largely avoided.

Details of the invention are described below with reference to an in explained in more detail the embodiment shown in the drawing.

In detail show:

Fig. 1 is a block diagram schematically showing the relevant parts of a working according to the invention the data processing system,

Fig. 2 is a flow chart associated,

Fig. 3 is a comparison of the flowcharts in the treatment of operand conflict,

Fig. 4 is a block diagram for deriving the early transmit signal in accordance with the invention,

FIG. 5 shows sequence sequences for machine instructions with a conditional end of instruction consisting of one or two elementary operations, taking into account any possible operand conflicts,

FIG. 6 and FIG. 7 are flowcharts for the block diagram of FIG. 4 for a conditional-end machine instruction consisting of two elementary operations for a satisfied and unsatisfied test in the second elementary operation, taking into account an operand conflict.

The block diagram of Fig. 1 shows on the basis of Fig. 3 of German Patent 36 03 230 parts of a command processing processor PLU and a command execution processor EXU with the essential for the understanding of the invention means. Depending on a not shown clock distribution arrangement and the microprogram control PCM-ST commands are read from the memory system CA / MM in the command buffer IB and successively forwarded to the command register IR from the command execution processor PLU . At the same time, as part of the instruction interpretation, the microprogram start address START-AD for the instruction- conditioning processor EXU is determined from the memory FPCD and subsequently provided in the register PMSA for transfer to the instruction- conditioning processor EXU .

Depending on the type of instruction and the address instructions of the machine instruction temporarily stored in the instruction register IR , the address controller AD-ST determines the possibly required operand addresses and makes them available in the registers PPA / B for the transfer to the instruction execution processor EXU . Likewise, the command contained in the command register IR is forwarded to a sequence register POR and read from the calculated memory operand address an operand of up to 8 bytes in length in advance and provided in a register, not shown, for the acquisition.

Furthermore, in the instruction processing processor PLU an arrangement MCONF-ST is still provided for the monitoring of conflicts, the possibly occurring operand conflicts by comparing the supplied from the address control AD-ST operand read address M / L-AD with the supplied from the command execution processor EXU operand write address M-. AD is determined and reported with the signal OPCONF to the command execution processor EXU . Analogously, it is further monitored whether, if necessary, a wrong command has been read in advance, and this is indicated by the signal PCONF .

The operation in the instruction execution processor EXU is also controlled by a microprogram control ECM-ST in conjunction with a clock distributor (not shown). Within the microprogram control are shown two microprogram memories each having an associated address control register, shown as one unit ECM-A / B and ECA-A / B respectively, and a common read register ECDR . Both address registers are respectively loaded in parallel, either with the start address START-AD from the register PMSA of the command conditioning processor PLU or from the shared read register ECDR , as the control process respectively requires, so that both memories can be controlled simultaneously, but only one of the Memory via the selection switch ECDRMUX the information in the read register ECDR is adopted depending on a corresponding selection signal of the control circuit EC . The read register ECDR is further followed by a buffer register ECDRBF , from which the instruction decoder CDEC is fed for the generation of the function signals for the execution of the respectively associated elementary operation.

In addition to this conventional structure, the microprogram control, which is described, for example, in the Siemens references U 64068-J and U 68002-J, are in effect of the invention, besides the actual microinstruction storage ECM-A / B two further control store PECM N and PECM- C are addressed, which are addressed by a common address control register PECA and each of which a read register PECDR-N and PECDR-C downstream.

Both control memories are constructed substantially the same and contain per machine command an addressable via the address control register PECA with the start address MSA entry as early control information, which is needed for timely decision making and parameter provisioning . This control information therefore consists of corresponding parts of the microinstructions contained in the normal microprogram memory ECM-A / B. In principle, a single control memory, namely the control memory PECM-N , would suffice for the control according to the invention. In the present case, however, a second control memory PECM-C is provided, whose entries are used only in case of an operand conflict for the flow control. The individual entries in the two control memories PECM-N and PECM-C consist, for example, of 16 bits in accordance with the following representation:

The individual entries have the following meaning:

WR : Write RD : Read LA / RA : Right or left alignment of the operand PA / B : Selection of address registers PA or PB of combination PA / B L : Length of the operand TCFEO : Test code for the first elementary operation FEO of a machine instruction TCSEO : Test code for the second elementary operation SEO of a machine instruction CENFEO : Conditional end in the first elementary operation FEO CENDSEO : Conditional end in the second EO SEO

The structure of the entries for both memories differs only in that the entry for a write command WR is missing in the control area PECM-C , since an operand conflict is read exclusively. The control information provided in the read registers PECDR-N or PECDR-C or the corresponding control information from the buffer register ECDRBF are now forwarded as required as a function of the decision of the additional monitoring device TU to the control register PECDRBF via the selection switches MUX 1 and MUX 2 and stand Thus for the further process control available. The choices made by the two selection switches MUX 1 and MUX 2 are made such that the selection switch MUX 1 first makes a selection between the read register PECDR-N of the first control memory or the buffer register ECDRBF , while the other selection switch MUX 2 selects between the output of the read register PECDR-C of the second control memory and the output of the other selector switch MUX 1 hits. This has the great advantage that in conjunction with the second control memory PECM-C, the switching time is shortened until the input of the control register PECDRBF and thus reaction time is obtained. Of course, with sufficient time conditions, the two selection switches MUX 1 and MUX 2 could also be combined in a selector switch.

In the event that the instruction processing processor PLU detects a command conflict in parallel with an operand conflict and reports both conflicts with the signals OPCONF and PCONF the command execution processor EXU , instead of the respectively provided early control information via the selection switches MUX 1 and MUX 2 directly the command RI for the renewed command read to the control register PECDRBF through and thus initiated the necessary command read . The displayed operand conflict is no longer relevant in this case.

In addition to the extended microprogram control ECM-ST of the command execution processor EXU shown , the lower part of FIG. 1 shows the address calculation unit ADW for calculating and providing the respective operand addresses. This address calculation consists in a conventional manner of the actual address register A , an adder ADD , and an intermediate register EADR . The address register A is fed at the beginning of a machine command in the usual way via the register chain PPA / B and PA / B with the operand start address OP-AD . From this start address, the adder ADD of the address calculation unit calculates, by adding a constant K , the optionally required following address, which is buffered in the intermediate register EADR and then forwarded to the address register A. Notwithstanding the usual address calculating operations is in effect of the invention, both the output of the transfer register PA / B and the output of the intermediate register EADR via the selection switch MUX directly to the memory control in the operand reading switched through.

The acquisition of the individual control information by the individual registers takes place in a clocked manner with clock pulses T supplied by the clock distributor arrangements, not shown, at different times of an elementary operation. , ., Wherein, in elementary operations with four clock phases, the clock pulses T 4 for the last clock phase in each case initiate the end of an elementary operation and usually provide as a supply clocks the starting point for the subsequent elementary operation. In the present case, in particular the start addresses in the registers PMSA and PPA / B are provided at the interface to the instruction execution processor EXU with the clocks T 4 from the preparation processor PLU and subsequently further processed with the specified clock pulses by the instruction execution processor EXU .

Fig. 2 shows a corresponding flowchart. The top line shows a sequence of elementary operations for two machine instructions MBn and MB 1 consisting of two elementary operations EOn 1 and EOn 2 or EO 11 and EO 12 and a machine instruction MB 2 consisting of an elementary operation EO 21 , the last elementary operation of a machine instruction marked LEO . All elementary operations EO . , , consist of four clock phases with the associated clock pulses T 1 to T 4 .

The following lines of the flowchart refer to the identically marked registers and line systems of FIG. 1. In each case in the last elementary operation of a machine command, the start addresses MSA . , , and SA . , , provided in the registers PPMSA or PPA / B. Each in the penultimate elementary operation before the start of a new machine command, z. B. in the elementary operation EOn 1 with respect to the first elementary operation EO 11 of the machine instruction MB 1 , then in the clock phase 4 with a delayed clock pulse T 4 ', the start address MSA 1 in the ECA-A / B and PECA registers , so that both the micro-instruction memory ECM-A / B and the control memories PECM-N and PECM-C are newly addressed and the corresponding information is read. Even in the same clock phase, the control information read is taken over into the read registers PECDR-N or PECDR-C with a more delayed clock pulse T 4 ", whereas the associated micro-instruction read from the micro-instruction memory ECM-A / B does not change until the following elementary operation EOn 2 is taken over by the clock pulse T 2 from the read register ECDR . Only with the subsequent clock pulse T 4 '' is the micro-instruction MC 11 available for controlling the associated elementary operation EO 11 in the buffer register ECDRBF . By comparison, due to the phase-shifted clocking of the read registers PECDR-N and PECDR-C of the control memory PECM-N or PECM-C , an elementary operation has already accessed the required control information PFCC 11 earlier and this with the subsequent clock pulse T 2 in FIG common buffer register PECDRBF be provided for the flow control, so that even before the start of the associated elementary operation EO 11 triggered a memory access and the memory access can be initiated in the last clock phase of the same elementary operation.

In machine instructions consisting of only one elementary operation at a time, the required early control information for the control register PECDRBF is successively taken from the control memories PECM-N or PECM-C alone, as the row for this control register with respect to the control information PFCC 21 and PFCC 31 for the machine instructions MB 2 and MB 3 can be seen.

In the case of machine instructions consisting of a plurality of elementary operations, on the other hand, the early control information for the second and further elementary operation of the same machine command, e.g. For example, the control information FCC 12 for the elementary operation EO 12 is derived from the microinstruction in the microinstruction memory ECM-A / B and taken from the buffer register ECDRBF . This requires, however, that the respectively available microinstruction, z. B. MC 11 , in each case additionally the required control information of the subsequent microinstruction, ie z. B. MC 12 , so that it can already be accessed in advance because the micro-command MC 12 with the derived from the micro-command MC 11 subsequent address FA 12 is available later. The command providing the early control information is indicated in brackets in the cell for the buffer register ECDRBF in addition to the actual microinstruction. Sources for the early control information in Steuerinregister PECDRBF are thus in the lead to the respective first elementary operation of a machine command , the control memory PECM-N or PECM-C and for the further elementary operations of a machine command of the micro-instruction memory ECM-A / B , which by corresponding arrows in Fig. 2 is indicated.

In order to provide the necessary memory address at the same time as the Funktioinscode from the buffer register PECDRBF at memory accesses, which is taken only with the phase clock T 2 of an elementary operation of the register PA / B start address, z. B. SA 1 , as the operand address OPAD 11 directly switched through to the address line system ADBUS . This applies to all from just one EO. For the subsequent elementary operations on the other hand, the stored in the register PA / B start address is taken with the following clock pulse T 4 in the register A , so that after increasing by a constant K by the adder ADD of the arithmetic unit ADW with the clock pulse T 2, the following address in Intermediate register EADR is ready and is supplied from here to the address line system ADBUS .

As can be seen from FIG. 1 and indicated by arrows in FIG. 2, the acquisition of the respective new start address MSA takes place . , , for the micro-instruction memory ECM-A / B always independent of that in the micro-instruction MC . , , for the respective last elementary operation LEO of a machine instruction MB . , , control bit contained END, which is tapped at the read register ECDR and is therefore available very early on. This Stuerbit END is then in a conventional manner in conjunction with a predetermined clock pulse of the subsequently executed associated elementary operation to the end of the machine instruction MB. , , characteristic end signal TREND , which can control the switching of the selector switch MUX 1 , MUX and MUX 3 at sufficiently long cycle time of elementary operations, so that the respectively required early control information from the control memory PECM-N or PECM-C and the memory address already very early in of the last elementary operation LEO of a machine instruction in the flow to the associated first elementary operation of the subsequent machine instruction.

In this way, for. B. consisting of an elementary operation machine instructions with memory accesses without loss of performance loss cycles are performed sequentially when a shortening of the cycle time of the elementary operations control alone by the executed micro-instruction from the micro-instruction memory ECM-A / B is no longer possible, because the time to End of the elementary operation would no longer be sufficient for the initiation of the memory start and would have to be prevented by an inserted loss cycle that the memory access parameters change prematurely. The circumvention of such loss cycles is therefore a first significant advantage of the additional control memory.

Operand conflicts can also be solved more favorably with the early control information from the control memories, as shown by the comparison of the flowcharts of FIG . Line A shows, based on Fig. 2 of DE-PS 36 03 240 a sequence of elementary operations in the handling of operand conflicts. For example, if an operand conflict OPCONF is detected in the last elementary operation LEO of a machine instruction, then the next following first elementary operation FEO of the next machine instruction MBn will not be executed, but the execution processor EXU will be braked for the duration of an elementary operation and the microcontroller for conflict resolution in another branch of the micro-instruction memory ECM-A / B addressed and read. Thereafter, the reading of the operand ROP is executed and another elementary operation NOOP is waited until the operand has arrived in the instruction execution processor EXU . Thus, before the actual first elementary operation FEO of the new machine instruction MBn can be executed, three elementary operations occur which entail a considerable reduction in performance. On the other hand, because of the early available control information from the control store, the reading of the operand according to line B of FIG. 3 can already be initiated in the last elementary operation LEO of the machine instruction MBn - 1 , and only an elementary operation NOOP needs to be waited until the instruction execution processor EXU perform the first elementary operation FEO of the new machine instruction MBn . The saving of two loss elementary operations leads to a considerable increase in performance, especially in the case of frequently occurring operand conflicts.

The control information required for the release of the operand can be taken from a uniform control memory PECM-N . However, the control is simpler and requires shorter switching times if a second control memory PECM-C as shown in FIG. 1 is used for the conflict control, since then the selection can be controlled in a simpler manner by the control signal OPCONF indicating the operand conflict . which will be explained in more detail.

The early provision of the required control information from the control memories is only possible if the end of a machine command is detected early. For machine instructions with an unconditional end, the end signal can be derived directly from the control bit END with a subsequent clock pulse still in the same or sufficient cycle time even in the first part of the next, namely the last elementary operation of a machine command .

Decisive here is only the timely availability in the last elementary operation LEO before the start of a new machine command. Depending on the available cycle time of the individual elementary operations, therefore, a different timing of the address and read registers for the microprogram control ECM-ST can be selected. Also, instead of the common provision register PECDRBF in FIG. 1, the read registers PECDR-N and PECDR-C as well as the buffer register ECDRBF may immediately serve as scheduling provision registers all having the same early clock pulse, e.g. B. T 2 , are clocked and their outputs then selected to be switched to the line systems.

In many cases, however, the instruction execution time and thus the number of required for a machine instruction elementary operations is unpredictable, so that in such micro-instructions with parameter-dependent, conditional end only programmatically after fulfillment of predetermined tests in a microinstruction with microprogrammed unconditional control bit END must be transferred. For machine instructions consisting of only one or two elementary operations, this implies additional loss elementary operations for program branching into an unconditional microinstruction.

These caused by machine instructions with conditional machine command end loss cycles can be avoided according to a development of the invention, if the control sequence designed so that the actual end of the machine command detected in time and can be reversed accordingly early on the respectively required first micro-command of the machine command. This decision is made by the additional monitoring device TU shown in FIG. 1 and shown in greater detail in FIG. 4 based on the test information TEST derived from the early control information of the control store, taken respectively into register TURBF and until the next early end of the associated machine instruction End signal TRENDE remain cached . This test information consisting of two control bits CENDFEO and CENDSEO , which characterize the present in the micro-instruction for the first elementary operation FEO or the second elementary operation SEO of a machine command control bit END , and the associated test code TCFEO or TCSEO . With the test code TCFEO for the first elementary operation FEO of a machine instruction, respectively a first test mask TM-FEO is applied and with the test code TCSEO for the second elementary operation SEO of a machine instruction, a second test mask TM-SEO is applied to detect the condition signals TS-FEO or TS -SEO to check the progress conditions displayed. If the given test conditions are fulfilled, the test masks TM-FEO or TM-SEO generate the signals TFEOTR and TSEOTR , respectively , in a logic operation circuit LOGV with the control bits END , CENDFEO and CENDSEO as well as with the signals OFCONF for the display of the operand conflict and 1 , EO to 3 . EO of the number of counting from the beginning of each machine command successively initiated elementary operations counter counter EO-CT are linked. This counter is therefore reset at the beginning of each machine command and advanced with the clock pulse T 2 of each elementary operation.

The control signal V-SIG generated by the logical combination circuit LOGV is then evaluated with the clock pulses T 3 and the bistable flip-flop DK 1 is set to produce the early end signal TRENDE for one cycle duration. From this early end signal is then derived in an analogous manner by setting the downstream bistable multivibrator DK 2 with the subsequent clock pulse T 2 _EO , which is effective only when executing a micro-command, the final signal TREND . In the flow chart of Fig. 2, these signals are reproduced in their timing with respect to the underlying machine instruction sequence in the last line.

The control signal V-SIG of the logic operation circuit LOG-V is determined according to the following logical relationships:

The partial relationships according to Parts I and II refer to machine instructions with unconditional end, ie both control bits CENDFEO and CENDSEO are not set. The occurring control bit END therefore leads directly to the signal V-SIG = 1. The indication of an operand conflict with the signal OPCONF = 1 only causes the control bit leading microinstruction according to FIG. 3, line B , to be executed delayed by one cycle duration.

The further partial relationships according to the lines A to H refer to machine instructions with conditional end in the first or second elementary operation FEO or SEO of a machine instruction . The associated sequences are shown in Fig. 5 and the corresponding cases with the same line character marked. It can thus be seen that, apart from the extension of the machine instruction MBn by an elementary operation in the case of an operand conflict in the case of an unsatisfied condition, there is always an extension by a further elementary operation. A machine instruction consisting of two elementary operations is thus extended by a maximum of two elementary operations to a total of four elementary operations, whereby the actual end of the current machine command MBn is recognized on the basis of the early end signal TRENDEn in time with the required forerun .

FIG. 6 and FIG. 7 show the sequences of operations when the operand conflict is displayed with OPCONF = 1 and the fulfilled or unfulfilled end condition in the second elementary operation SEO according to lines F and H of FIG. 5 corresponding complete flowcharts.

The elementary operation in which the early end signal TRENDEn is generated, results in the logical sub-relationships according to lines A to H from the third link size, while the fourth link size takes into account whether the test conditions are met or not. In this case, if the test condition is not fulfilled, the signal or rather is taken into account, but rather the signal, in order to prevent the early end signal TRENDEn from being triggered too early. Namely, as shown in FIG. 7, the test conditions TESTn for the machine instruction MBn already take effect in the first half of the last elementary operation LEO of the machine instruction MBn - 1 , so that in this last elementary operation, the association condition to be satisfied for the machine instruction MBn could already be satisfied , The simultaneously effective signal TREND (n -1) = 1 in this case prevents the premature triggering of the early end signal TRENDEn .

Line III of the logic equation for the control signal V-SIG ensures that, when transitioned into an error routine or the like during a running machine operation with conditional end caused by the control bits CENDFEO or CENDSEO conditional end identification after expiration of the maximum allowable number of elementary operations, which the interlinkage quantities INHCENDFEO or INHCENDSEO is displayed, canceled and the further control in turn depends solely on the unconditional control bit END of the introduced routine.

The same applies to longer, more than two elementary operations existing machine commands in which the number of required remaining elementary operations until the end of the Machine command in a conventional way with unconditional end microprogrammed in sufficient lead to the last elementary operation is determined.

Depending on the early end signal TRENDE , the selection switches MUX 1 and MUX 2 are then set by the control signals S-MUX 1 or S-MUX 2 according to the following scheme:

In the case of a command prefetch error PFCONF = 1 according to the first combination line, a possibly occurring operand conflict is no longer significant since a wrong command has already been read in advance. In this case, the signal OPCONF is suppressed and the directly applied command code RI for re-instruction read through the selection switch MUX 1 is turned on to the instruction preparation processor PLU , while the instruction execution processor EXU is braked in a conventional manner.

If, on the other hand, only one operand conflict OPCONF = 1 is displayed according to the last combination line, then the bit combination for the control signal S-MUX 1 is uninteresting, and the control information S-MUX 2 = 1 is output directly to the control information at the same end signal TRENDE = 1 the second control memory PECM-C for conflict resolution switched and the associated memory address of the register PB for the address calculation ADW .

The other two combination lines apply to the conflict-free operation, the second line in each case with respect to the respective first elementary operation of a machine command and the third line in each case with respect to all other elementary operations of a machine command, ie the early control information is always for the first elementary operation Control memory PECM-N and derived for all other elementary operations of the micro-instruction memory ECM-A / B. The same applies to the optionally required memory addresses for which first the register PA and then the intermediate register EADT of the address calculation unit ADW serves as a source.

Claims (19)

1. A method for controlling the timely decision process and the parameter provision in microprogram-controlled machine command sequences, in which the machine commands ( MB ... ) each trigger one or more elementary operations ( EO ... ) and with each machine command ( MB Start address ( MSA ... , SA ...) for a micro-instruction memory (ECM) containing the micro-instructions for the individual elementary operations ( EO ...) and for an address storage unit ( ADW) for supplying the possibly necessary memory operand address (M-AD) and depending on a the light of the last elementary operation (LEO) characteristic of the foregoing machine instruction control signal to take effect (eND), wherein on the basis of the start addresses or the derivable therefrom subsequent addresses (FA) (from the micro-instruction memory in each case in the flow to be performed elementary operation of the associated microinstruction ECM) and a givenfa lls required memory operand address (M-AD) is calculated so that they are ready in time for the start of the corresponding elementary operation to be executed for the control, characterized in that when insufficient duration of the elementary operations ( EO . , .) for the timely bringing about of the progress of the control sequence by successive elementary operations affecting decisions or for the provision of required parameters required for the decisions and the parameter preparation part of the micro-instruction for the first elementary operation (FEO) of a machine command (eg MBn ) are read from a separate control memory (PECM-N ) immediately after the release of the start address (MSAn) in each case before the start of the last elementary operation (LEO) of the preceding machine instruction ( MBn - 1 ) and with a sufficiently early phase clock (eg T 2 ). the last elementary operation (LEO) is provided in a buffer register (eg PECDRBF) in advance of the complete micro-instruction for the sequence control read from the micro-instruction memory (ECM) and only later available. 2. The method of claim 1, characterized in that, when consisting of several elementary operations machine instructions of the start address (MSA...) Or subsequent address (FA) driven microinstruction memory (ECM) adjacent to the respective associated microinstruction at the same time the respect of the decisions or the parameter providing required part of the possibly following microinstruction delivers, which regardless of the later only the execution of the associated elementary operations receiving complete microinstruction in advance in the previous elementary operation with the same phase clock (T 2 ) as the corresponding parts from the control memory (PECM- N) is provided in a buffer register (eg PECDRBF) for the flow control. 3. The method according to claim 1 or 2, characterized in that for the timely provision of the memory accesses in addition to the buffer register (eg PECDRBF) ready function code (FCC) from the control memory ( PECM-N) or from the micro-instruction memory (ECM) required memory address (M-AD) after its provision with the corresponding early phase clock (T 2 ) in the address calculation (ADW) feeding register (PA) acquired start address (SA) bypassing the address calculation (ADW) directly and in the run to the first Elementary operation (FEO) of a machine command ( MB . ..) and subsequently for further elementary operations (eg SEO , TEO) of the same machine command, the sequence addresses calculated sequentially by the address calculation value (ADW) and buffered in a timely manner. Method according to one of Claims 1 to 3, characterized in that the early control information read from the control memory (PECM-N) and the micro-instruction memory (ECM) is stored in individual buffer registers clocked at the same early phase clock (eg T 2 ) be provided for selection for the flow control. 5. The method according to any one of claims 1 to 3, characterized in that the respectively required early control information among the read from the control memory ( PECM-N) and the micro-instruction memory (ECM) early control information selected in a common memory for all buffer register (PECDRBF) with an early phase clock (eg T 2 ) to provide for flow control. 6. The method according to claim 4 or 5, characterized in that the selection of the respectively responsible control information and the optionally required memory address (M-AD) by a in the last elementary operation (LEO) of a machine command ( MB ...) End signal generated (TREND ) . 7. The method according to claim 4 or 5, characterized in that the selection of the respectively responsible early control information and the optionally required memory address (M-AD) by an already before the beginning of the last elementary operation (LEO) of a machine command ( MB... ) In Leading to the end signal (TREND) generated early end signal (TRENDE) takes place. 8. The method according to claim 7, characterized in that the early end signal (TRENDE) in machine instructions with unconditional end directly from a in the micro-instruction for the last elementary operation (LEO) containing control bit (END) immediately after reading this micro-instruction from the micro-instruction memory (ECM) in conjunction with a subsequent phase clock in the same elementary operation. 9. The method according to claim 7, characterized in that for machine instructions with parameter-dependent, conditional command end the early end signal (TRENDE) in existing from one or two elementary machine instructions depending on additional control information from the control memory (PECM) for identifying the machine command possibly ending first or second elementary operation (control bit CENDFEO or CENDSEO) and the associated test conditions to be fulfilled (TCFEO or TESEO) when the test is satisfied in conjunction with a subsequent phase clock (T 3 ) of the elementary operation (FEO or SEO) preceding the elementary operation and if not fulfilled Test is generated with the same phase clock (T 3 ) of the designated elementary operation (FEO or SEO) in the run to the subsequent actual last elementary operation, and in contrast, in machine instructions consisting of more than two elementary operations, the number the necessary remaining elementary operations until the end of the machine command in a conventional manner with unconditional end microprogrammed in sufficient lead to last elementary operation determined and the early end signal (TREND) is generated depending on it. 10. The method according to any one of claims 4 to 9, characterized in that at a displayed Operandenkonflikt (OPCONF) based on the available from the control store early control information and the associated memory address (M-AD) causes the reading of the operand from the memory directly and the Subsequent to execution pending first elementary operation (FEO) of the new machine instruction is delayed by one elementary operation. 11. The method as claimed in claim 10, characterized in that, in the case of operand conflicts (OPCONF), the early control information is sent to a second control memory (PECM-C) which is controlled simultaneously with the first control memory (PECM-N) by the respectively provided start address ( MSA . is removed. 12. Circuit arrangement for controlling microprogrammed machine command sequences in data processing systems, consisting

• from two supply registers (PMSA , PPA) for the starting addresses ( MSA , ... , OPAD , ... ) derived from a machine command ( MB .
• from a micro-instruction memory (ECM) with a read register (ECDR) and an address register (ECA) for the optional transfer of the start address ( MSA ..) from the provision register (PMSA) or the following address (FA) from the read register (ECDR)
• - from an address calculation value (ADC), comprising an address register (A) and an adder (ADD) with a downstream intermediate register (EADR) to assume the next address (. Eg OPAD 12), wherein the address arithmetic unit (ADW) (from the staging register PPA) controllable register (PA) upstream of the takeover of the start address (SA) and the address register (A) optionally with the transfer register (PA) or with the intermediate register (EADR) can be coupled,

marked

• by a control memory ( PECM-N) with read register (PECDRN ) containing parallel to the microinstruction memory (ECM) , only the part of the microinstruction of the respective first elementary operations (FEO) of a machine instruction ( MB ...) which is required for the decisions and the parameter provision ) , which can be controlled with the respectively provided and in an associated address register (PECA) also adopted start address (MSA) , and
• by two selector switches (MUX 1 , MUX) which can be reversed in time towards the end of a machine command for forwarding the control information (eg FCC ... ) present in the read register (PECDRN) of the control memory (PECM-N ) instead of that from the micro-instruction memory (ECM) derived from the microinstruction derived control information and for forwarding the present in the transfer register (PA) address instead of from the intermediate register (EADR) of the address calculation (ADW) to the sequencer.

13. Circuit arrangement according to claim 12, characterized in that the read register (ECDR) of the microinstruction memory (ECM), a buffer register (ECDRBF) is connected downstream, which clocked with the same phase clock as the read register (PECDR-N) of the control memory (PECM-N) becomes. 14. Circuit arrangement according to claim 13, characterized in that the same phase clock is an early phase clock (eg T 2 ) of the elementary operation (EO) , which releases the register contents for the sequencer, while the read register of the microinstruction memory (ECM) with a late phase clock (eg T 4 ) is clocked, so that from this the execution of the subsequent associated elementary operation and the end monitoring of the individual machine commands is controlled, while with the early phase clock (T 2 ) already valid for the subsequent microinstruction control information is taken over into the buffer register. 15. Circuit arrangement according to claim 13, characterized in that the same phase clock is a late clock (eg T 4 '') of the elementary operation ( EO .. ) and that the control information of the respectively selected by the selection switch (MUX 1 ) Equally-timed register (ECDRBF or PECDRN) is released by adopting the early phase clock (T 2 ) in a common buffer register (PECDRBF) for the flow control. 16. Circuit arrangement according to one of claims 12 to 15, characterized in that a second control memory (PECM C) with the read register (PECDRC) provided parallel to the control memory (PECM N) (in the same way as the first control memory PECM- N) from the already existing address register (PECA) is addressed, and that for forwarding the control information from the second control memory (PECM-C), a further selection switch (MUX 2 ) is provided, which in the presence of an operand conflict instead of the output via the another control switch (MUX 1 ) supplied from the other memories (PECM-N or PECM) of the second control memory (PECM-N) . 17. Circuit arrangement according to claim 12 or 12 and 16, characterized in that the control information of the control store in addition to the necessary function code (FCC) and test codes for the first two elementary operations (FEO , SEO) include a machine command (MB) with a parameter-dependent command end and that is coupled to the output of the common buffer register (PECDRBF) a monitoring device (TU) for the end monitoring of each machine command, the Umsteuersignale (S-MUX 1 , S-MUX 2 , TREND , TREND) for each affected selection switch (MUX 1 , MUX 2 , MUX) and supplies the signals necessary for the sequence control. 18. The circuit arrangement as claimed in claim 17, characterized in that the end monitoring circuit (TU) consists of two test masks (TM-FEO , TM-SEO) for checking compliance with the conditions prescribed by the test code for the first or second elementary operation (FEO or FEO). SEO) , a counter (EO-CT) for the identification of the first, the second and the third elementary operation (FEO , SEO , TEO) of a machine instruction and a logic operation circuit (LOGV) for the generation of the early end signal (TRENDE) and the thereof Dependent control signals depending on the recognition of a last elementary operation (LEO) and the observance of the test conditions, taking into account possible conflict situations (OPCONF , PFCONF) exists.