DE3869366D1 - METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE. - Google Patents

METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE.

Info

Publication number
DE3869366D1
DE3869366D1 DE8888119598T DE3869366T DE3869366D1 DE 3869366 D1 DE3869366 D1 DE 3869366D1 DE 8888119598 T DE8888119598 T DE 8888119598T DE 3869366 T DE3869366 T DE 3869366T DE 3869366 D1 DE3869366 D1 DE 3869366D1
Authority
DE
Germany
Prior art keywords
memory
zone
pref
erasure
zones
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888119598T
Other languages
German (de)
Inventor
Hartmut Dr Schrenk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE8888119598T priority Critical patent/DE3869366D1/en
Application granted granted Critical
Publication of DE3869366D1 publication Critical patent/DE3869366D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0866—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means by active credit-cards adapted therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Read Only Memory (AREA)
  • Credit Cards Or The Like (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Communication Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The memory is divided into zones of different value for use as a multistage counter. These memory zones are selectively erased, erasure of each zone, only following upon reception of a transfer bit from the adjacent memory zone with the next highest value under control of a logic circuit. Pref. the erasure of the memory zone for the highest value is irreversible, e.g. by destruction of fuse. Each memory cell pref. has a selection transistor (TAZ) and a memory transistor (TS) and is individually addressed via row and column lines (AZ1, AZ2..., AS1..), the control gates of the memory cells coupled to a common control line for each row controlled via a switching transistor (TS1, TS2..TSn).
DE8888119598T 1987-12-17 1988-11-24 METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE. Expired - Lifetime DE3869366D1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE8888119598T DE3869366D1 (en) 1987-12-17 1988-11-24 METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3742894 1987-12-17
DE8888119598T DE3869366D1 (en) 1987-12-17 1988-11-24 METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE.

Publications (1)

Publication Number Publication Date
DE3869366D1 true DE3869366D1 (en) 1992-04-23

Family

ID=6342886

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888119598T Expired - Lifetime DE3869366D1 (en) 1987-12-17 1988-11-24 METHOD AND CIRCUIT FOR THE TAMPERED PROTECTION OF EE-PROM STORAGE.

Country Status (8)

Country Link
US (1) US5001332A (en)
EP (1) EP0321727B1 (en)
JP (1) JP2684606B2 (en)
AT (1) ATE73946T1 (en)
DE (1) DE3869366D1 (en)
DK (1) DK170009B1 (en)
ES (1) ES2029710T3 (en)
FI (1) FI98769C (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2524321Y2 (en) * 1990-08-09 1997-01-29 日本信号株式会社 IC card
US6166650A (en) * 1991-05-29 2000-12-26 Microchip Technology, Inc. Secure self learning system
FR2686989B1 (en) * 1992-01-30 1997-01-17 Gemplus Card Int SECURITY COUNTING METHOD FOR A BINARY ELECTRONIC COUNTER.
DE59308837D1 (en) * 1992-05-20 1998-09-10 Siemens Ag Method and data carrier arrangement for authenticity detection of memory chips
FR2700864B1 (en) * 1993-01-26 1995-04-14 Monetel System for detecting falsification of stored information.
FR2703501B1 (en) * 1993-04-01 1995-05-19 Gemplus Card Int Integrated circuit for memory card and method for counting units in a memory card.
DK0624880T3 (en) * 1993-05-10 1999-06-21 Siemens Ag Procedure and circuit for counting down the value of a debit card
ATE297577T1 (en) * 1994-05-06 2005-06-15 Ipm Internat Sa VALUE CARD WITH BINARY VALUE UNITS AND METHOD FOR MOVING A SIZE REPRESENTED WITH BINARY VALUE UNITS ON THE VALUE CARD
US5841866A (en) * 1994-09-30 1998-11-24 Microchip Technology Incorporated Secure token integrated circuit and method of performing a secure authentication function or transaction
ATE163786T1 (en) * 1994-09-30 1998-03-15 Siemens Ag DATA TRANSMISSION SYSTEM COMPRISING A TERMINAL AND A PORTABLE DATA CARRIER ARRANGEMENT AND METHOD FOR RECHARGING THE PORTABLE DATA CARRIER ARRANGEMENT USING THE TERMINAL
CA2193846C (en) * 1995-05-17 2004-02-17 Bradford L. Farris Rolling code security system
US6980655B2 (en) * 2000-01-21 2005-12-27 The Chamberlain Group, Inc. Rolling code security system
US6690796B1 (en) 1995-05-17 2004-02-10 The Chamberlain Group, Inc. Rolling code security system
GB2321738A (en) * 1997-01-30 1998-08-05 Motorola Inc Circuit and method of erasing a byte in a non-volatile memory
US6108326A (en) * 1997-05-08 2000-08-22 Microchip Technology Incorporated Microchips and remote control devices comprising same
DE19823955A1 (en) 1998-05-28 1999-12-02 Siemens Ag Method and arrangement for operating a multistage counter in one counting direction
WO2000019384A1 (en) * 1998-09-30 2000-04-06 Infineon Technologies Ag Circuit and method for authenticating the content of a memory location
EP1234283B1 (en) 1999-11-29 2004-06-09 Infineon Technologies AG Method and arrangement for operating a multi-stage counter in a counting direction
US8422667B2 (en) 2005-01-27 2013-04-16 The Chamberlain Group, Inc. Method and apparatus to facilitate transmission of an encrypted rolling code
US9148409B2 (en) 2005-06-30 2015-09-29 The Chamberlain Group, Inc. Method and apparatus to facilitate message transmission and reception using different transmission characteristics
US8924633B2 (en) 2011-03-08 2014-12-30 Dust Networks, Inc. Methods and system for erasing data stored in nonvolatile memory in low power applications
US9397500B2 (en) * 2013-06-28 2016-07-19 Solantro Semiconductor Corp. Inverter with extended endurance memory
US10652743B2 (en) 2017-12-21 2020-05-12 The Chamberlain Group, Inc. Security system for a moveable barrier operator
US11074773B1 (en) 2018-06-27 2021-07-27 The Chamberlain Group, Inc. Network-based control of movable barrier operators for autonomous vehicles
US11423717B2 (en) 2018-08-01 2022-08-23 The Chamberlain Group Llc Movable barrier operator and transmitter pairing over a network
US10997810B2 (en) 2019-05-16 2021-05-04 The Chamberlain Group, Inc. In-vehicle transmitter training

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1207227B (en) * 1979-08-09 1989-05-17 Ates Componenti Elettron REPRODUCIBLE. ELECTRONIC CARD WITH OBLITERABLE CELLS WITH KEY OF RECOGNITION NOT REPRODUCABLE FOR EQUIPMENT DISTRIBUTORS OF GOODS OR SERVICES AND METHOD FOR THE REALIZATION OF THAT KEY
JPS5671885A (en) * 1979-11-15 1981-06-15 Nec Corp Semiconductor memory
JPS5943471A (en) * 1982-09-06 1984-03-10 Nippon Telegr & Teleph Corp <Ntt> Payment system
DE3315047A1 (en) * 1983-04-26 1984-10-31 Siemens AG, 1000 Berlin und 8000 München INTEGRATED CIRCUIT WITH AN APPLICATION MEMORY DESIGNED AS A NON-VOLATILE WRITE-READ MEMORY
DE3318123A1 (en) * 1983-05-18 1984-11-22 Siemens AG, 1000 Berlin und 8000 München CIRCUIT ARRANGEMENT WITH A DATA MEMORY AND A CONTROL UNIT FOR READING, WRITING AND ERASING THE MEMORY
DE3318101A1 (en) * 1983-05-18 1984-11-22 Siemens AG, 1000 Berlin und 8000 München CIRCUIT ARRANGEMENT WITH A STORAGE AND ACCESS CONTROL UNIT
JPS61103761U (en) * 1984-12-13 1986-07-02
JPS62239286A (en) * 1986-04-10 1987-10-20 Mitsubishi Electric Corp Ic card system
DE3638505C2 (en) * 1986-11-11 1995-09-07 Gao Ges Automation Org Data carrier with integrated circuit

Also Published As

Publication number Publication date
US5001332A (en) 1991-03-19
FI885844A0 (en) 1988-12-16
FI98769C (en) 1997-08-11
ATE73946T1 (en) 1992-04-15
JPH022099A (en) 1990-01-08
FI885844A (en) 1989-06-18
DK170009B1 (en) 1995-04-24
EP0321727A1 (en) 1989-06-28
JP2684606B2 (en) 1997-12-03
EP0321727B1 (en) 1992-03-18
FI98769B (en) 1997-04-30
DK700988A (en) 1989-06-18
DK700988D0 (en) 1988-12-16
ES2029710T3 (en) 1992-09-01

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Legal Events

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