DE3853673D1 - Automatische Bandmontage-Packung. - Google Patents
Automatische Bandmontage-Packung.Info
- Publication number
- DE3853673D1 DE3853673D1 DE3853673T DE3853673T DE3853673D1 DE 3853673 D1 DE3853673 D1 DE 3853673D1 DE 3853673 T DE3853673 T DE 3853673T DE 3853673 T DE3853673 T DE 3853673T DE 3853673 D1 DE3853673 D1 DE 3853673D1
- Authority
- DE
- Germany
- Prior art keywords
- tape assembly
- automatic tape
- assembly pack
- pack
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Multi-Conductor Connections (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/168,034 US4829405A (en) | 1988-03-14 | 1988-03-14 | Tape automated bonding package |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3853673D1 true DE3853673D1 (de) | 1995-06-01 |
DE3853673T2 DE3853673T2 (de) | 1995-11-23 |
Family
ID=22609814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3853673T Expired - Fee Related DE3853673T2 (de) | 1988-03-14 | 1988-11-09 | Automatische Bandmontage-Packung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4829405A (de) |
EP (1) | EP0332747B1 (de) |
JP (1) | JPH01241140A (de) |
CA (1) | CA1287693C (de) |
DE (1) | DE3853673T2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4015788C2 (de) * | 1990-05-16 | 1994-06-23 | Siemens Nixdorf Inf Syst | Baugruppe |
US20010030370A1 (en) * | 1990-09-24 | 2001-10-18 | Khandros Igor Y. | Microelectronic assembly having encapsulated wire bonding leads |
US5148265A (en) † | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US7198969B1 (en) * | 1990-09-24 | 2007-04-03 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
EP0506225A3 (en) * | 1991-03-26 | 1993-11-24 | Ibm | Integrated circuit chip package |
US5121293A (en) * | 1991-08-08 | 1992-06-09 | Sun Microsystems, Inc. | Method and apparatus for interconnecting devices using tab in board technology |
JP3520186B2 (ja) * | 1996-09-30 | 2004-04-19 | 東芝マイクロエレクトロニクス株式会社 | フィルムキャリアテープの製造方法、フィルムキャリアテープの製造装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3546775A (en) * | 1965-10-22 | 1970-12-15 | Sanders Associates Inc | Method of making multi-layer circuit |
US3684818A (en) * | 1970-10-20 | 1972-08-15 | Sprague Electric Co | Multi-layer beam-lead wiring for semiconductor packages |
US3875479A (en) * | 1973-05-07 | 1975-04-01 | Gilbert R Jaggar | Electrical apparatus |
US4064552A (en) * | 1976-02-03 | 1977-12-20 | Angelucci Thomas L | Multilayer flexible printed circuit tape |
US4405929A (en) * | 1980-06-27 | 1983-09-20 | Ricoh Company, Ltd. | Thermal head device |
JPS5818949A (ja) * | 1981-07-28 | 1983-02-03 | Nec Corp | 半導体装置 |
US4694123A (en) * | 1982-01-13 | 1987-09-15 | Elxsi | Backplane power connector system |
US4495377A (en) * | 1982-12-30 | 1985-01-22 | International Business Machines Corporation | Substrate wiring patterns for connecting to integrated-circuit chips |
JPS6046040A (ja) * | 1983-08-24 | 1985-03-12 | Nec Corp | 半導体装置 |
GB8412606D0 (en) * | 1984-05-17 | 1984-06-20 | Murray J | Printed circuit boards |
-
1988
- 1988-03-14 US US07/168,034 patent/US4829405A/en not_active Expired - Lifetime
- 1988-11-09 EP EP88118644A patent/EP0332747B1/de not_active Expired - Lifetime
- 1988-11-09 DE DE3853673T patent/DE3853673T2/de not_active Expired - Fee Related
- 1988-12-16 JP JP63316583A patent/JPH01241140A/ja active Pending
-
1989
- 1989-01-20 CA CA000588787A patent/CA1287693C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA1287693C (en) | 1991-08-13 |
JPH01241140A (ja) | 1989-09-26 |
EP0332747B1 (de) | 1995-04-26 |
EP0332747A2 (de) | 1989-09-20 |
US4829405A (en) | 1989-05-09 |
DE3853673T2 (de) | 1995-11-23 |
EP0332747A3 (en) | 1990-07-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |