DE3850212T2 - Multiple CPU system with shared memory. - Google Patents

Description

BACKGROUND OF THE INVENTION

The present invention relates to a multiple CPU system having a shared memory in which data information is transferred between a plurality of CPUs using the shared memory. In particular, the invention relates to the control of the shared memory.

A multiple CPU system in which data information is mutually transferred between a plurality of CPUs using a common memory is known in the art. Two typical examples are disclosed in Japanese Patent Application Laid-Open No. 243763/1985 and No. 245063/1985.

Fig. 10 illustrates the multiple CPU system disclosed in Japanese Patent Application Laid-Open No. 243763/1985. In this system, data information is mutually transferred between a word CPU 1 which accesses a common memory 3 having a unit word length and a byte CPU 2 which accesses the same common memory 3 having a unit byte length. The length of one byte is one half the length of one word. The common memory 3 includes two dual-port memories 3₁ and 3₂ each storing data information of one byte. In this multiple CPU system, when data information of one word length is written from the byte CPU 2 to the common memory 3, the first byte of the data information of one word length is stored in one of the dual-port memories, e.g. B. 3₁, and then the second byte of data information is stored in the other dual port memory 3₂. However, during these two operations, an access conflict may occur when the word CPU 1 accesses the shared memory 3 while the byte CPU 2 continues to write the second byte of data information to the same address. This access conflict may destroy the data information of one word to be input from the byte CPU 2 into the shared memory 3, or may cause the word CPU 1 to read incorrect data information in which data of only one byte is renewed. On the other hand, when data information from a When a word is read from the shared memory 3 to the byte CPU 2, the first byte of data information from a word is read out first, and then the second byte of data information is read out. During these two operations, an access conflict may also occur in this case if the word CPU 1 writes new data information to the shared memory 3 while the byte CPU 2 continues reading the second byte of data information at the same address. This access conflict may destroy the data information to be output from the shared memory 3 to the byte CPU 2.

In view of these facts, in this prior art multiple CPU system, the word CPU 1 is prohibited from accessing the shared memory 3 and is kept at least in its waiting state while the byte CPU 2 accesses the shared memory 3 for the data information of one word. The word "at least" means that "at least" the contention problem is avoided by the above method. In fact, in the prior art multiple CPU system, the byte CPU 2 is also prohibited from accessing the shared memory 3 and is kept at its waiting state while the word CPU 1 accesses the shared memory 3. That is, when both the word CPU 1 and the byte CPU 2 access the shared memory 3, access request signals S1 and S2 from the respective CPUs are applied to respective inputs of a latch circuit 20 consisting of a flip-flop circuit. A "NAND" result of output signals from the latch circuit 20 allows either the word CPU 1 or the byte CPU 2 to gain access to the shared memory 3. Herein, the access request signal S2 from the word CPU 1 is subjected to an "AND" operation with an inversion of a word access signal S3 output when the byte CPU 2 accesses the data information of one word, and the AND result is applied to the latch circuit 20. Therefore, while the byte CPU 2 is accessing the shared memory 3 for the data information of one word, the access request signal S2 from the word CPU 1 cannot be input to the latch circuit 20. That is, while the byte CPU 2 continues accessing the shared memory 3 for the second byte, the word CPU 1 cannot access the shared memory 3. Inverted signals of the outputs from the locking circuit 20 and the respective access request signals S1 and S2 are subjected to an AND function to form respective wait signals S4 and S5. By virtue of these wait signals S4 and S5, while one CPU is accessing the shared memory, the other CPU is kept in its wait state. As described above, this type of multiple CPU system saves the data information of one word in the shared memory 3 when the byte CPU 2 accesses this information.

However, in this type of multiple CPU system, while one CPU is accessing a certain address, the other CPU is kept in its waiting state even if it requests access to another address. This results in longer information processing time.

Fig. 11 shows the multiple CPU system disclosed in Japanese Patent Application Laid-Open No. 245063/1985. The purpose of this prior art system is to improve the problem of the prior art system of Fig. 10 that it takes a longer time in data transfer functions. In this multiple CPU system, the times during which the two CPUs 1 and 2 asynchronously access a memory 3 are alternately allocated to the two CPUs. For example, the system allows the CPU 1 to access the shared memory 3 only during the time allotted to the CPU 1 to access the shared memory 3. This multiple CPU system comprises: a pulse generator 21 which generates continuous pulse signals; a flip-flop 22 which is alternately set and reset by an output signal from the pulse generator 21; AND gates 23 and 24 which perform AND functions between respective outputs from the flip-flop 22 and respective access request signals A and B from the CPUs 1 and 2; flip-flops 25 and 26 which are set by respective outputs from the AND gates 23 and 24; and an address selector 27 which allows one of the CPUs to access its designated address depending on which of the flip-flops 25 and 26 is set. That is, when the access request signals A and B are output from the respective CPUs 1 and 2, if one of the outputs Q and of the flip-flop 22 corresponding to the respective CPUs 1 and 2 has a HIGH level value, one of the flip-flops 25 and 26 is set and the corresponding CPU 1 or 2 is allowed to access the designated address. which is stored in CPU 1 or 2. CPUs 1 and 2 have their address memories here as peripheral circuits to store the access address. Further, the inverted output of each of the flip-flops 25 and 26 is applied to an "inhibit" terminal of the AND gate 23 or 24 connected to the other flip-flop 25 or 26 to prevent one CPU from accessing the common memory 3 while the other is accessing it. In addition, when an access is completed, the flip-flops 25 and 26 are reset by respective notification signals E1 and E2 issued from the respective CPU 1 or 2. In this multiple CPU system, since the wait loss time occurs only when the CPU fails to access in the period allotted to that CPU, the data transfer time is shorter than in the previous multiple CPU system. However, also in this multiple CPU system, while one CPU is accessing the common memory 3, the other CPU is kept in its wait state even if the other CPU requests access to another address. There is still a problem of additional processing time.

Another method is disclosed in the prior art multiple CPU system using a shared memory which is a dual port memory including a "busy" terminal as a contention arbitration terminal from which an arbitration signal is output upon the occasion of the access contention to keep one CPU in its waiting state while the other CPU accesses the same address in the shared memory. For this type of shared memory with the busy terminal, for example, the MB8421 of Fujitsu, Ltd. is applicable. In this shared memory for the multiple CPU system, when the addresses and chip select signals (CS) compete with each other, the shared memory gives priority to the CPU which has accessed the shared memory earlier and keeps the other CPU in its waiting state by keeping the corresponding busy signal (Busy) at the low level. Fig. 12 shows an example of a multiple CPU system using this type of shared memory. In this system, the data information is transmitted between CPUs 1 and 2 through a shared memory 3. For the CPUs 1 and 2 mentioned, Intel 8085 and 8086 are used. This type of CPU has a "Ready" input, the state of which is changed to HIGH level when it is able to access. By connecting this Ready terminal to the Busy terminal of the shared memory 3, this system can easily realize the contention decision regarding the shared memory 3. That is, when the CPU 2 requests access to the shared memory 3 while the CPU 1 is accessing the same address thereof, the shared memory 3 makes the busy signal (Busy₂) attain the LOW level, thereby keeping the CPU 2 in its wait state until the access from the CPU 1 is completed. The CPU 2 can access the shared memory 3 after the access from the CPU 1 is completed and the busy signal (Busy₂) has changed to the HIGH level. As described above, the contention decision regarding the same address in the shared memory 3 can be realized. Here, a control signal (Cnt) in Fig. 12 includes signals such as a read signal (RD), a write signal (WT), and a chip select signal (CS).

However, since a so-called "single-chip microcomputer", such as an Intel 8031, does not have a ready connection or an equivalent connection, it cannot carry out the conflict decision described above for the shared memory 3.

In another prior art system, as disclosed in Electronics, Vol. 49, No. 20, Sept. 30, 1976, pages 89-90, data information is transferred between a shared memory and a given computer using a TTL parallel access register controlled by two flip-flops as a buffer stage between a shared memory (FIFO) and a computer. Finally, the use of a timing circuit to control the timing of the data transfer between two processors and a shared memory is known from IBM T.D.B. Vol. 30, No. 5, Rar 163-172, Oct. 1987, which discloses a synchronized system of two 8051 microprocessors with a shared RAM, wherein a clock stretching and synchronization circuit causes the instruction cycles in the 8051s to be 50% out of phase with each other, allowing each processor to access the shared RAM during times when the other processor cannot make such access.

SUMMARY OF THE INVENTION

The present invention is intended to overcome the problems set forth above. It is therefore an object of the present invention to provide a multi-CPU system which can realize contention arbitration for a shared memory even in the case of using a so-called single-chip microcomputer which has no control terminal.

A multiple CPU system according to the invention as claimed in claims 1 and 2 comprises the following elements between a CPU without a control terminal and a common memory: an access arbitration memory for temporarily storing data information and corresponding address information when performing read or write operations between a CPU and the common memory, and a timing control circuit for controlling the timing of data reading or writing between the access arbitration memory and the common memory according to an arbitration signal output from a conflict arbitration terminal of the common memory.

With the above arrangement, when executing the data reading or writing between the CPU without the control terminal and the common memory, the timing control circuit properly executes the timing control of the data reading and writing between the access arbitration memory and the common memory in accordance with a arbitration state with respect to an output of a contention arbitration terminal of the common memory, thereby executing the contention arbitration for the common memory even in the case of using a so-called single-chip microcomputer.

Other and further objects, features and advantages of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a circuit diagram of a multiple CPU system according to an embodiment of the present invention;

Fig. 2 and Fig. 3 are timing charts for explaining the write functions in the embodiment of Fig. 1;

Fig. 4 and Fig. 5 are timing charts for explaining the reading functions in the embodiment of Fig. 1;

Fig. 6 is a circuit diagram of another timing control circuit;

Fig. 7 is a timing chart for explaining an operation of the embodiment of Fig. 1;

Fig. 8 is a circuit diagram of a multiple CPU system according to another embodiment of the invention;

Fig. 9 is a timing chart for explaining an operation of the embodiment of Fig. 8;

Fig. 10 is a circuit of a conventional multiple CPU system;

Fig. 11 is a circuit of another conventional multiple CPU system, and

Fig. 12 is a block diagram illustrating still another conventional system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Version 1

A multiple CPU system using a shared memory according to the first embodiment of the invention will be described with reference to Figs. 1 to 7. In this embodiment, a dual port memory having a contention arbitration terminal is used as a shared memory 3. At the contention arbitration terminal, a arbitration signal is outputted which prohibits CPUs without priority from accessing an address in the shared memory while a CPU is actually accessing the same address. Data information is mutually transferred between a CPU 1 of a so-called "single chip microcomputer" type having no "ready" terminal or the like and a CPU 2 having the "ready" terminal through the shared memory 3. Contention arbitration is required between the CPU 1 and the CPU when data transfer is carried out between the CPU 1 and the shared memory 3. To achieve this conflict decision, the multiple CPU system comprises: an access decision memory for storing the data information to be transferred between the CPU 1 and the common memory 3 and corresponding address information, and a timing control circuit 18 for controlling the timing of data reading and writing between the access arbitration memory and the common memory 3 in accordance with an arbitration signal output from a busy terminal Busy₁ which is a contention arbitration terminal of the common memory 3. The access arbitration memory comprises a memory 4 for storing the address to be accessed in the common memory 3 when the data information is transferred between the common memory 3 and the CPU 1, a D-flip-flop 5 (hereinafter referred to as D-FF) having a three-stage output for latching the data information to be written into the common memory 3, and a D-FF 6 for latching the data information read from the common memory 3. The timing control circuit 18 includes all the negative logic circuits of the "AND" circuits 7 and 8, a "NOR" circuit 9, the "OR" circuits 10 to 14, the resistors R1 and R2, and the capacitors C1 and C2. And it keeps the data transfer between the D-FF 5 or 6 and the common memory 3 in its waiting state until the "Busy" signal (Busy₁) changes to the non-conflict state when a read signal (RD) or a write signal (WT) is output from the CPU 1 and is in conflict with the CPU 2 (the CPU 2 has the access priority).

The function of this embodiment will be explained below. First, an explanation will be made with reference to Fig. 2 for the case where the data transfer from the CPU 1 to the shared memory 3 is not in conflict with the CPU 2 or it has the access priority even if it does not compete with the CPU 2. When the CPU 1 accesses the shared memory 3, a chip select signal CS and the write signal WT of the CPU 1 change to the LOW level, as shown in Fig. 2(a) and 2(b), respectively; an output COWT of the AND circuit 8 as an AND function of the chip select signal CS and the write signal WT changes to the LOW level as shown in Fig. 2(e), and an output CORW of the NOR circuit 9 changes to the HIGH level as shown in Fig. 2(f). The address into which the data information is to be written is stored in the memory 4 by using the leading edge of the output CORW of the NOR circuit 9 as shown in Fig. 2(h). The data information itself to be written is stored in the D-FF 5 by using the leading edge of the output COWT of the AND circuit 8.

Next, an actual write operation to the shared memory 3 will be described. This operation is performed using an output DWT of the OR circuit 13 in Fig. 2(g). In this case of description, since there is no conflict between the CPUs 1 and 2 or the CPU 1 has the priority to access the shared memory 3, the busy signal (Busy₁) is in the HIGH level and the output DWT of the OR circuit 13 therefore changes to the LOW level at the moment when the output COWT of the AND circuit 8 changes to the LOW level. Consequently, the voltages of a write terminal WT₁ of the shared memory 3 and an output enable OE of the D-FF 5, both terminals supplied with the output DWT of the OR circuit 13, change to the LOW level. At the same time, since an output of the OR circuit 14 to which the output DWT of the OR circuit 13 is applied as an input changes to the LOW level and the chip select terminal CS₁ of the common memory 3 to which the output of the OR circuit 14 is applied changes to the LOW level as shown in Fig. 2(j), the write operation into the common memory 3 becomes possible at the moment when the write signal WT is input from the CPU 1. The output COWT of the AND circuit 8 changes to the HIGH level when the write signal WT of the CPU 1 changes to the HIGH level, so that the data information itself is stored in the D-FF 5. Since at this moment the busy signal Busy₁ and the output of the AND circuit 8 change to the HIGH level, both of which are input to the OR circuit 12, the output of the OR circuit 12 changes to the HIGH level. However, the output signal DWT of the OR circuit 13 is maintained at the LOW level for a period τ₂ which is the time constant determined by the resistor R2 and the capacitor C2. The actual writing of the data information into the common memory 3 is carried out by means of the output signal DWT of the OR circuit 13 which is changed to the HIGH level after the delay time τ₂. The time constant τ₂ is set herein to the period required to write the data information into the common memory 3. In the case where an access from the CPU 2 to the shared memory 3 occurs while the memory 3 is being written by the CPU 1, the voltage of the busy terminal Busy₂ of the shared memory 3, which is directly connected to the ready terminal of the CPU 2, changes to the LOW level, and the CPU 2 is thereby kept in its wait state until the write operation has been completed by the CPU 1. When there is no conflict, the busy signal Busy₂ is maintained at the HIGH level as shown by a dashed line in Fig. 2(k). The period τ₁ in Fig. 2(k) is a delay time used to cancel the conflict state of the shared memory 3.

Next, another case will be explained where the CPUs 1 and 2 are in conflict and the CPU 2 has the access priority to access the shared memory 3. In this case, since the busy signal Busy₁ changes to the LOW level as shown in Fig. 3(g) with the address information being read from the memory 4 into the shared memory 3, the output DWT of the OR circuit 13 does not change to the HIGH level even if the output COWT of the AND circuit 8 changes to the HIGH level as shown in Fig. 3(e). The CPU 1 is thus prevented from writing the data information until the access from the CPU 2 is completed. When the busy signal Busy₁ changes to the HIGH level as shown in Fig. 3(g), the data information that has been stored in the DFF 5 is written into the common memory 3 in response to the rise of the output DWT of the OR circuit 13 occurring after the delay time τ₂ in the same manner as described above.

Next, the operation of reading out the data information from the shared memory 3 will be described. First, the case where there is no conflict or where the CPU 1 has the access priority in the case of the conflict will be described with reference to Fig. 4. When reading out the data information from the shared memory 3, as shown in Figs. 4(c) and 4(b), the read signal RD and the chip select signal CS change to the LOW level, and the output CORD of the AND circuit 7 therefore changes to the LOW level as shown in Fig. 4(e). At the same time, since the output CORW of the NOR circuit 9 changes to the HIGH level as shown in Fig. 4(f), the address of the data information to be read out is stored in the memory 4. Since the output signal CORD of the AND circuit 7 is applied to an output enable terminal OE of the D-FF 6 in which the read-out data information is stored, the data stored in the D-FF 6 is read out to the CPU 1 in response to the output CORD of the AND circuit 7. Since the D-FF 6 stores the data information read out in the previous access to the common memory 3, the the previous access is provided to the CPU 1 in the read operation set out above. As a result, the data information is read from the common memory 3 into the CPU 1 by accessing the common memory 3 twice. When the output CORD of the AND circuit 7 changes to the HIGH level as shown in Fig. 4(e), the output DRD of the OR circuit 11 changes to the HIGH level after a delay time τ₁ which is a time constant determined by the resistor R1 and the capacitor C1 as shown in Fig. 4(g). In response to the input of the signal DRD to a clock terminal of the D-FF 6, the data information from the common memory 3 is written into the D-FF 6. The time constant τ₁ is set herein to the time taken to read data from the common memory 3. The output signal DRD of the OR circuit 11 is applied to the output enable terminal OE₁ of the common memory 3, and the output signal of the OR circuit 14 is applied to the chip select terminal CS₁. When the conflict with the CPU 2 occurs, the busy terminal Busy₂ changes to the LOW level as shown in Fig. 4(1) in the same manner as in the previous write operation.

On the other hand, in case of the conflict with the CPU 2 having the access priority, the data information is read from the shared memory 3 and is sent to the D-FF 6 after a period τ1 from the rise of the busy signal Busy1 as shown in Fig. 5(g).

As described in the preceding pages, in the first embodiment of the invention, in order to carry out the data transfer between the shared memory 3 and the CPU 1 without the ready terminal, the aforementioned timing control circuit 18 controls the timing of the data transfer between the memory 4 and the shared memory 3 in accordance with the access contention with reference to the output signal from the busy terminal of the shared memory 3. The contention decision of the memory 3 can therefore be realized even in the case where a so-called "single-chip microcomputer" is used.

A modified circuit shown in Fig. 6 can achieve the same result. The timing control circuit 18 comprises a D-FF 15 which is preset by each output signal COWT of the AND circuit 8. and is cleared by the output CORD of the AND circuit 7. The AND functions between the busy signal Busy₁ and respective output signals Q and are performed in the respective AND circuits 16 and 17, and the AND results are applied to respective OR circuits 10 and 12. In the data reading or data writing operation of the CPU 1, the busy signal Busy₁ is applied only to the corresponding one of the reading or writing side of the subsequent circuit. The output timing of the AND circuits 16 and 17 is the same as that of the busy signal Busy₁. It is therefore agreed that the function of this modification is the same as that of the previous embodiment of Fig. 1 except that the busy signal Busy₁ is replaced by the output signal of the AND circuits 16 and 17.

The above description applies to the case where the contention decision for the shared memory 3 is carried out between the CPU 1 without the control terminal (e.g., the ready terminal) and the CPU 2 with the control terminal. It is noted, however, that the invention is also applied to the case where the contention decision is carried out between a plurality of CPUs without the control terminal. In this case, the timing control circuit 18 is arranged between each CPU without the control terminal and the shared memory 3.

Version 2

A multiple CPU system using a shared memory according to another embodiment of the invention is shown in Figs. 8 and 9. The following are sentences of a program for the write operation from the CPU 1 to the shared memory 3 of the first embodiment. This program is for use of the Intel 8031. Step 1

That is, the program works as follows: Determine the data to be written DATA1 in step 1; Determine an address to which the data is to be written in step 2; Write the data DATA1 to the address Add.1 in step 3; determining the next data DATA2 to be written in step 4; determining an address Add.2 into which the data DATA2 is to be written in step 5, and writing the data DATA2 to the address Add.2 in step 6.

In the first embodiment of Fig. 1, the program of which is listed above, in the case as shown in Figs. 7(a) and 7(e) where the CPU 2 accesses an address in the shared memory 3 before the CPU 1 executes writing to the same address in the step 3, the busy output Busy1 of the shared memory 3 changes to the LOW level. When the access by the CPU 1 has been completed, the signal Busy returns to the HIGH level after a delay time t1. Then, by means of the aforementioned timing control circuit 18, the outputs of the write terminal WT1 and the chip select terminal 751 are returned to the HIGH level after a delay time τ2, i.e., the time required to write data into the shared memory 3.

However, in the step 6, if the next write operation starts before the voltages of the write terminal WT1 etc. return to the HIGH level as shown by a broken line in Fig. 7(a), the write terminal WT1 and the chip select terminal CS1 are held in the LOW level as shown by broken lines in Figs. 7(b) and 7(c), and in this situation, the CPU 1 goes to the write operation of the next data DATA2. This means that the CPU 1 cannot write the previous data information DATA1. The condition under which such a problem will occur is given by: T2 + t1 + τ2 > T1. Usually, various CPUs can be used as the CPU 2. If a CPU with the long access time T2 is used, the CPU 1 and the chip select terminal CS1 are kept ... when the CPU 2 is used, the above formula is satisfied, and the writing operation from the microprocessor 1 cannot be guaranteed. The same problem may also occur in the reading operation.

In the embodiment shown in Fig. 8, therefore, the CPU 1 detects the completion of the transfer of the data information whose corresponding address information is stored in the memory 4 into the common memory 3 by using the output signal CS₁ of the OR circuit 14 in the timing control circuit 18, and the next address is blocked until the above-mentioned writing or reading operation is completed. For this purpose, a control device is provided which is constructed in a software manner in logic circuits of the CPU 1 and has functions for detecting the completion of the writing by applying the output signal CS₁ of the OR circuit 14 in the timing control circuit 18 to an input terminal Port1 of the CPU 1 and blocking the next access until the completion of the writing or reading of the data with the address stored in the memory 4 into or from the common memory 3.

The following are sentences of a program for writing from the CPU 1 to the shared memory 3 of this embodiment. Step 1

Step 6

Step 7

In this program, steps 1 to 5 correspond to those of the first execution. In step 6, access is stopped until the previous data writing (Add.1) is completed. In step 7, the data DATA2 is written to the address Add.2.

In this program, the CPU 1 detects the completion of the previous access (step 3) before starting the next access (step 7), that is, it detects the change of the output CS1 of the OR circuit 14 to the HIGH level (Fig. 9(c)) by the input signal state of the input port Port1 to which the output CS1 is applied, and executes the next access after the end of the writing as shown in Fig. 9(a). With this arrangement, the problem of the first execution, that is, the access error of the DATA1, can be solved.

As described in the preceding pages, in the multiple CPU system of the present invention, the contention decision for the shared memory can be achieved even in the case of using the so-called single-chip microcomputer.

Claims (4)

1. A system having multiple CPUs using a shared memory in which data information is mutually transferred between a plurality of CPUs, the system comprising: a first CPU having a control terminal that interrupts its access to the shared memory in response to an arbitration signal applied to the control terminal; a second CPU without the control terminal; wherein the shared memory outputs the arbitration signal to the CPUs without priority when a same address of the shared memory is accessed by the plurality of CPUs; an access decision memory arranged between the second CPU and the shared memory for temporarily storing data information transferred between the second CPU and the shared memory and corresponding address information; and a timing control circuit arranged between the second CPU and the shared memory for controlling the timing of data transfer between the access arbitration memory and the shared memory in accordance with the arbitration signal. 2. System with multiple CPUs using a shared memory in which data information is mutually transferred between a plurality of CPUs, whereby the large number of CPUs do not have a control connection and cannot interrupt their access to the shared memory on their own initiative; wherein the shared memory outputs an arbitration signal to the CPUs without priority when a same address of the shared memory is accessed by the plurality of CPUs; and the system comprises: an access decision memory arranged between each CPU and the common memory for temporarily storing data information transferred between the CPUs and the common memory and corresponding address information; and a timing control circuit disposed between each CPU and the common memory for controlling the timing of data transfer between the access arbitration memory and the common memory in accordance with the arbitration signal. 3. A system according to claim 1, wherein the second CPU includes a control means for recognizing the address information corresponding to the data stored in the access decision memory from an output signal of the timing control circuit when the transfer of data information has been completed and for preventing the next access to the shared memory until the transfer is completed. 4. A system according to claim 2, wherein the CPUs include a control means for recognizing the address information corresponding to the data stored in the access decision memory from an output signal of the timing control circuit when the transfer of data information has been completed, and for preventing the next access to the shared memory until the transfer is completed.