DE3842758A1 - Process for etching a three-layer interconnection level in the production of integrated semiconductor circuits - Google Patents
Process for etching a three-layer interconnection level in the production of integrated semiconductor circuitsInfo
- Publication number
- DE3842758A1 DE3842758A1 DE19883842758 DE3842758A DE3842758A1 DE 3842758 A1 DE3842758 A1 DE 3842758A1 DE 19883842758 DE19883842758 DE 19883842758 DE 3842758 A DE3842758 A DE 3842758A DE 3842758 A1 DE3842758 A1 DE 3842758A1
- Authority
- DE
- Germany
- Prior art keywords
- etching
- titanium
- alloy layer
- tungsten alloy
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000005530 etching Methods 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910001080 W alloy Inorganic materials 0.000 claims abstract description 24
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000000460 chlorine Substances 0.000 claims abstract description 6
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229960000909 sulfur hexafluoride Drugs 0.000 claims abstract description 5
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 33
- -1 aluminum-silicon-titanium Chemical compound 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910018503 SF6 Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 abstract description 6
- 239000010936 titanium Substances 0.000 abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 235000010678 Paulownia tomentosa Nutrition 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Die Erfindung betrifft ein Verfahren zum Ätzen einer dreilagigen Verdrahtungsebene bestehend aus einer unteren Titan-Wolfram-Le gierungsschicht, einer Aluminium-Legierungsschicht und einer oberen Titan-Wolfram-Legierungsschicht durch reaktives Ionen ätzen bei der Herstellung einer integrierten Halbleiterschal tung.The invention relates to a method for etching a three-layer Wiring level consisting of a lower titanium-tungsten Le alloy layer, an aluminum alloy layer and one upper titanium-tungsten alloy layer by reactive ions etching in the manufacture of an integrated semiconductor scarf tung.
Die Verdrahtungsebenen von Halbleiterbauelementen einer inte grierten Halbleiterschaltung bestehen häufig aus sandwichartig übereinander angeordneten Schichten, die unterschiedliche Metall-Legierungen enthalten können. Bei der Herstellung der Metalli sierungsstrukturen der Verdrahtungsebenen müssen dabei in der Regel unterschiedliche Ätzprozesse mit unterschiedlichen Chemi kalien für die jeweiligen Schichten durchgeführt werden, wobei die jeweiligen Selektivitäten zur Ätzmaske und zum Untergrund möglichst gut sein müssen. Dreilagige Verdrahtungsebenen aus Titan-Wolfram-Legierung/Aluminium-Legierung/Titan-Wolfram-Le gierung werden z.B. für bipolare Hochgeschwindigkeits-Gatearrays benötigt. Ein solches dreilagiges Metallisierungssystem ist z.B. im Band 15 der Siemens Forschungs- und Entwicklungsberich te 1986, Nr. 2, auf den Seiten 64 bis 67 beschrieben.The wiring levels of semiconductor components of an integrated semiconductor circuit often consist of sandwiched layers, which can contain different metal alloys. In the production of the metallization structures of the wiring levels, different etching processes with different chemicals must generally be carried out for the respective layers, the selectivities for the etching mask and the substrate having to be as good as possible. Three-layer wiring levels made of titanium-tungsten alloy / aluminum alloy / titanium-tungsten alloy are required, for example, for bipolar high-speed gate arrays. Such a three-layer metallization system is described, for example, in Volume 15 of the Siemens Research and Development Reports 1986, No. 2, on pages 64 to 67.
Aufgabe der Erfindung ist es, ein Ätzverfahren zur Herstellung einer dreilagigen Verdrahtungsebene aus einer Titan-Wolfram- Legierungsschicht, einer Aluminium-Legierungsschicht und einer weiteren Titan-Wolfram-Legierungsschicht durch reaktives Ionen ätzen anzugeben, das sich durch Metallisierungsstrukturen mit hoher Maßhaltigkeit und hoher Selektivität auszeichnet.The object of the invention is to produce an etching process a three-layer wiring layer made of a titanium-tungsten Alloy layer, an aluminum alloy layer and one another titanium-tungsten alloy layer through reactive ions etching to indicate that by using metallization structures high dimensional accuracy and high selectivity.
Ein Ätzverfahren zum Ätzen von dreilagigen Verdrahtungsebenen aus einer Titan-Wolfram-Legierungsschicht, einer Aluminium-Sili zium-Legierungsschicht und einer Titan-Wolfram-Legierungsschicht durch reaktives Ionenätzen ist aus Semiconductor International May 1987, Seite 256 bis Seite 259 bekannt. In einem dreistufigen Ätzprozeß wird dabei zum Ätzen der oberen und unteren Titan-Wol fram-Schicht ein fluorhaltiges Plasma und zum Ätzen der dazwi schen angeordneten Aluminium-Silizium-Schicht ein chloridhaltiges Plasma verwendet.An etching process for etching three-layer wiring layers made of a titanium-tungsten alloy layer, an aluminum sili zium alloy layer and a titanium-tungsten alloy layer through reactive ion etching is from Semiconductor International May 1987, page 256 to page 259. In a three-stage Etching process is used to etch the upper and lower titanium tungsten fram layer a fluorine-containing plasma and for etching the dazwi arranged aluminum-silicon layer a chloride-containing Plasma used.
Die erfindungsgemäße Aufgabe wird durch ein Verfahren der ein gangs genannten Art gelöst, das dadurch gekennzeichnet ist, daß ein mehrstufiger Ätzprozeß zum Ätzen der unterschiedlichen Le gierungsschichten durchgeführt wird, wobei zum Ätzen der Titan- Wolfram-Legierungsschichten ein Sauerstoff und Schwefelhexa fluorid enthaltendes Plasma, ein Ätzdruck von 5 bis 20 mTorr und eine Biasspannung von kleiner als 200 V verwendet wird, zum Ätzen der Aluminium-Legierungsschicht ein Chlor enthaltendes Plasma, ein Ätzdruck von 20 bis 40 mTorr und eine Biasspannung von kleiner als 300 V verwendet wird und nach dem Ätzen der oberen Titan-Wolfram-Legierungsschicht ein Nachrei nigungsschritt zum Entfernen der beim Ätzen entstandenen Bar riereschicht durchgeführt wird. Es liegt außerdem im Rahmen der Erfindung, daß zusätzlich zu den Ätzschritten der jeweiligen Legierungsschichten Ätzschritte zur Überätzung und Passivierung durchgeführt werden.The object of the invention is achieved by a method of solved type mentioned, which is characterized in that a multi-stage etching process for etching the different Le Gierschichten is carried out, for etching the titanium Tungsten alloy layers an oxygen and sulfur hexa plasma containing fluoride, an etching pressure of 5 to 20 mTorr and a bias voltage of less than 200 V is used to Etch the aluminum alloy layer with chlorine containing plasma, an etching pressure of 20 to 40 mTorr and a Bias voltage of less than 300 V is used and after Etching of the upper titanium-tungsten alloy layer afterwards cleaning step to remove the bar formed during the etching barrier layer is carried out. It is also in the frame the invention that in addition to the etching steps of the respective Alloy layers etching steps for overetching and passivation be performed.
Weitere Ausgestaltungen und Weiterbildungen der Erfindung gehen aus den Unteransprüchen sowie aus der anhand eines Ausführungs beispiels mit drei Figuren gegebenen Beschreibung hervor.Further refinements and developments of the invention go from the subclaims and from an execution example with three figures given description.
Fig. 1 zeigt in schematischer Darstellung eine zu strukturierende dreilagige Verdrahtungsebene aus Titan-Wolfram 1/Aluminium-Si lizium-Titan 2/Titan-Wolfram 3 auf einem stufigen Halbleiterkör per 6, der zu verdrahtende integrierte Bauelemente (nicht in der Figur dargestellt) enthält und eine Oberfläche aus einer Oxid schicht (nicht in der Figur dargestellt) aufweist. Die dreila gige Verdrahtungsebene ist zur Strukturierung durch reaktives Ionenätzen mit einer Ätzmaske 4 aus Fotolack versehen. Fig. 1 shows a schematic representation of a three-layer wiring level to be structured from titanium-tungsten 1 / aluminum-Si-silicon-titanium 2 / titanium-tungsten 3 on a step semiconductor body by 6 , which contains integrated components to be wired (not shown in the figure) and has a surface of an oxide layer (not shown in the figure). The three-level wiring level is provided with an etching mask 4 made of photoresist for structuring by reactive ion etching.
Fig. 2 zeigt das Ergebnis eines für die in Fig. 1 dargestellte Dreilagenmetallisierung ungeeigneten Ätzverfahrens. Der als Ätz maske dienende Fotolack 4 ist sowohl vertikal als auch lateral, insbesondere aufgrund der bei der Strukturierung des Fotolacks entstehenden abgeschrägten Lackflanken 5, stark angegriffen. Da durch ist die Maßhaltigkeit besonders der oberen Titan-Wolfram- Legierungsschicht 3 nicht gewährleistet. Eine optimale Struktu rierung muß dagegen sowohl eine gute Maßhaltigkeit als auch eine gute Selektivität der Ätzung der Dreilagenmetallisierungsschicht zur Oxidunterlage (größer als 1) aufweisen. Prozesse mit besseren Selektivitäten liefern aber meist isotrope Ätzungen, wodurch es im Falle von Titan-Wolfram zu Unterätzungen (nicht in der Figur dargestellt) kommen kann. Der laterale Lackschwund 7 führt zu flachen Titan-Wolfram-Flanken 8. FIG. 2 shows the result of an etching process unsuitable for the three-layer metallization shown in FIG. 1. The photoresist 4 serving as an etching mask is severely attacked both vertically and laterally, in particular due to the beveled lacquer flanks 5 that arise during the structuring of the photoresist. Since the dimensional accuracy, especially of the upper titanium-tungsten alloy layer 3, is not guaranteed. Optimal structuring, on the other hand, must have both good dimensional stability and good selectivity for the etching of the three-layer metallization layer to the oxide base (greater than 1). However, processes with better selectivities mostly provide isotropic etching, which can lead to undercutting (not shown in the figure) in the case of titanium tungsten. The lateral paint shrinkage 7 leads to flat titanium-tungsten flanks 8 .
Fig. 3 zeigt das Ergebnis eines erfindungsgemäßen Ätzverfahrens, das den vertikalen und insbesondere lateralen Fotolackschwund stark verringert und daher zu anisotropen Titan-Wolfram-Flanken 9 führt. In Tabelle 1 sind Prozeßparameter für das erfindungsge mäße Verfahren angegeben, das z.B. in einer Ätzanlage vom Typ AME 8331 (Hexodenätzsystem, Batchanlage) der Firma AMT, Santa Clara, CA, USA durchgeführt werden kann. Durch die Verwendung des fluorhaltigen Ätzgemisches für die Titan-Wolfram-Ätzung bildet sich an der Grenzfläche zur Aluminium-Silizium-Titan-Le gierungsschicht eine Barierreschicht aus, die in einem separatem Prozeßschritt (Initialisierungsschritt) vor dem eigentlichen Ätzen der Aluminium-Silizium-Titan-Legierungsschicht entfernt werden muß. Das Ätzverfahren besteht daher aus mindestens 4 Pro zeßschritten. Fig. 3 shows the result of an etching method according to the invention, which greatly reduces the vertical and especially lateral photoresist shrinkage and therefore leads to anisotropic titanium-tungsten flanks 9. Table 1 shows process parameters for the method according to the invention, which can be carried out, for example, in an etching system of the type AME 8331 (hexode etching system, batch system) from AMT, Santa Clara, CA, USA. The use of the fluorine-containing etching mixture for the titanium-tungsten etching forms a barrier layer at the interface with the aluminum-silicon-titanium alloy layer, which in a separate process step (initialization step) before the actual etching of the aluminum-silicon-titanium Alloy layer must be removed. The etching process therefore consists of at least 4 process steps.
Tabelle 2 gibt ein Ausführungsbeispiel mit konkreten Prozeßpara metern wieder, bei dem zwischen den Ätzschritten der jeweiligen Legierungsschichten 1, 2, 3 zusätzliche Ätzschritte durchgeführt sind.Table 2 shows an embodiment with specific process parameters, in which additional etching steps are carried out between the etching steps of the respective alloy layers 1 , 2 , 3 .
Typische Ergebnisse des erfindungsgemäßen Verfahrens sind:
Ätzrate für die Titan-Wolfram-Legierungsschicht 30 bis 50 nm/min,
typischer Overetch 50% bei 1000 nm Stufen in der Oxidschicht,
Oxidabtrag 50 nm bei 100 nm Titan-Wolfram-Schichtdicke als worst
case bei voller Beladung,
Selektivität des Ätzschrittes oberes Titan-Wolfram
(3)/Aluminium-Silizium-Titan (2) größer als 10 : 1
und des Ätzschrittes Titan-Wolfram (1)/Oxidoberfläche größer als
3 : 1,
Selektivität des Ätzschrittes Aluminium-Silizium-Titan
(2)/unteres Titan-Wolfram (1) von ca. 3 : 1 bis 10 : 1 bei einer
Biasspannung von 150 V bis 300 V.Typical results of the method according to the invention are:
Etching rate for the titanium-tungsten alloy layer 30 to 50 nm / min,
typical overetch 50% at 1000 nm steps in the oxide layer,
Oxide removal 50 nm at 100 nm titanium-tungsten layer thickness as worst case when fully loaded,
Selectivity of the etching step upper titanium-tungsten (3) / aluminum-silicon-titanium (2) greater than 10: 1 and of the etching step titanium-tungsten (1) / oxide surface greater than 3: 1,
Selectivity of the etching step aluminum-silicon-titanium (2) / lower titanium-tungsten ( 1 ) from approx. 3: 1 to 10: 1 at a bias voltage of 150 V to 300 V.
Das erfindungsgemäße Verfahren zieht zur Ätzung der Titan-Wolfram- Legierungsschichten die Verwendung eines Gemisches aus Schwefel hexafluorid, Sauerstoff und evtl. Chlor vor. Dadurch kann die Ätzzeit für die Titan-Wolfram-Legierungsschicht deutlich ver kürzt werden. Dadurch und durch Verwendung einer relativ niedri gen Biasspannung ist es möglich, das Auftreten eines lateralen Fotolackabtrag stark zu reduzieren. Der niedrige Ätzdruck macht es möglich, die Titan-Wolfram-Legierungsschicht anisotrop und mit guter Maßhaltigkeit zu ätzen. Das Verfahren liefert eine gute Lack- und Untergrundselektivität sowie gute Ätzratenhomo genitäten.The method according to the invention draws for etching the titanium tungsten Alloy layers the use of a mixture of sulfur hexafluoride, oxygen and possibly chlorine. This allows the Etching time for the titanium-tungsten alloy layer clearly ver be shortened. This and by using a relatively low against bias voltage it is possible the occurrence of a lateral Greatly reduce photoresist removal. The low etching pressure makes it is possible to make the titanium-tungsten alloy layer anisotropic and to etch with good dimensional accuracy. The process provides one good paint and substrate selectivity as well as good etch rate homo genities.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19883842758 DE3842758A1 (en) | 1988-12-19 | 1988-12-19 | Process for etching a three-layer interconnection level in the production of integrated semiconductor circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19883842758 DE3842758A1 (en) | 1988-12-19 | 1988-12-19 | Process for etching a three-layer interconnection level in the production of integrated semiconductor circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3842758A1 true DE3842758A1 (en) | 1990-06-21 |
Family
ID=6369553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19883842758 Withdrawn DE3842758A1 (en) | 1988-12-19 | 1988-12-19 | Process for etching a three-layer interconnection level in the production of integrated semiconductor circuits |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE3842758A1 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998001900A1 (en) * | 1996-07-09 | 1998-01-15 | Lam Research Corporation | Method for etching layers on semiconductor wafers |
| EP0824269A2 (en) * | 1996-08-06 | 1998-02-18 | International Business Machines Corporation | Method for etching an Al metallization by a C12/HC1 based plasma |
| US5883007A (en) * | 1996-12-20 | 1999-03-16 | Lam Research Corporation | Methods and apparatuses for improving photoresist selectivity and reducing etch rate loading |
| EP0936666A2 (en) * | 1998-01-06 | 1999-08-18 | International Business Machines Corporation | Method of reducing metal voids in semiconductor device interconnection |
| US6004884A (en) * | 1996-02-15 | 1999-12-21 | Lam Research Corporation | Methods and apparatus for etching semiconductor wafers |
| US6087266A (en) * | 1997-06-27 | 2000-07-11 | Lam Research Corporation | Methods and apparatus for improving microloading while etching a substrate |
| US6090304A (en) * | 1997-08-28 | 2000-07-18 | Lam Research Corporation | Methods for selective plasma etch |
| EP1077481A2 (en) * | 1999-08-16 | 2001-02-21 | Applied Komatsu Technology, Inc. | Etching aluminium over refractory metal with successive plasmas |
-
1988
- 1988-12-19 DE DE19883842758 patent/DE3842758A1/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6004884A (en) * | 1996-02-15 | 1999-12-21 | Lam Research Corporation | Methods and apparatus for etching semiconductor wafers |
| US5846443A (en) * | 1996-07-09 | 1998-12-08 | Lam Research Corporation | Methods and apparatus for etching semiconductor wafers and layers thereof |
| WO1998001900A1 (en) * | 1996-07-09 | 1998-01-15 | Lam Research Corporation | Method for etching layers on semiconductor wafers |
| EP0824269A3 (en) * | 1996-08-06 | 1998-02-25 | International Business Machines Corporation | Method for etching an Al metallization by a C12/HC1 based plasma |
| EP0824269A2 (en) * | 1996-08-06 | 1998-02-18 | International Business Machines Corporation | Method for etching an Al metallization by a C12/HC1 based plasma |
| US5883007A (en) * | 1996-12-20 | 1999-03-16 | Lam Research Corporation | Methods and apparatuses for improving photoresist selectivity and reducing etch rate loading |
| US6087266A (en) * | 1997-06-27 | 2000-07-11 | Lam Research Corporation | Methods and apparatus for improving microloading while etching a substrate |
| US6090304A (en) * | 1997-08-28 | 2000-07-18 | Lam Research Corporation | Methods for selective plasma etch |
| EP0936666A2 (en) * | 1998-01-06 | 1999-08-18 | International Business Machines Corporation | Method of reducing metal voids in semiconductor device interconnection |
| EP0936666A3 (en) * | 1998-01-06 | 2003-05-21 | International Business Machines Corporation | Method of reducing metal voids in semiconductor device interconnection |
| EP1077481A2 (en) * | 1999-08-16 | 2001-02-21 | Applied Komatsu Technology, Inc. | Etching aluminium over refractory metal with successive plasmas |
| EP1077481A3 (en) * | 1999-08-16 | 2002-01-09 | AKT, Inc. | Etching aluminium over refractory metal with successive plasmas |
| US6472329B1 (en) | 1999-08-16 | 2002-10-29 | Applied Komatsu Technology, Inc. | Etching aluminum over refractory metal with successive plasmas |
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