DE3831903A1 - Multiplexer/demultiplexer for a data transmission system - Google Patents

Abstract

In data transmission systems, it is necessary to obtain different bit clocks for the data transmission. According to the invention, a clock generator (O) is used for this purpose, which supplies a high-frequency clock (HT) which is supplied to a divider chain (TK). The divider chain (TK) is synchronised by a highly accurate reference clock (RT) which is available, for example, as central clock in data exchanges. <IMAGE>

Description

The invention relates to a multiplexer / demultiplexer for a data transmission system according to the preamble of Claim 1.

Such multiplexers / demultiplexers are part of one Data network in which for the data exchanges DVST and converter places DUST central clock are needed, of which the time division and Switching systems are supplied with clocks. At the Master-slave synchronization process becomes more central Make a clock with high accuracy (master) used the downstream of the clock Network node (slave) controls. Operates on this principle the Deutsche Bundespost has a normal frequency network. The The central clock is therefore set to 75 Hz, so at the envelope formation of data signals (i.e. in the Integration of data bits into a block with one Status and an alignment bit) frequencies of 600 Hz or 750 Hz can be generated as integer multiples that have an envelope format according to the CCITT recommendation X.51 of 8 + 2 bits with a gross clock of 750 Hz and a net clock of 600 Hz.  

From "Instruction sheets of the Deutsche Bundespost, Edition B, Fernmeldewesen ", 38 (1985), p. 197 ff known the required bit clocks from the frequency of one derived crystal oscillator to divide by division and via a, especially digital, Phase locked loop (PLL) towards the reference clock synchronize.

As a result of complex control of variable divider stages, that is upstream of the phase locked loop is a high expenditure on components required. At a High-quality reference clocks can use phase locked loops Disadvantage that they are the unwanted Even phase modulation (jitter) of the reference clock increase.

The object of the invention is therefore a simpler Circuit for extracting multiples of one To provide reference clock.

The object is achieved as in claim 1 indicated, further training results from the Subclaim.

Compared to conventional PLL circuits, the invention has the advantage that it synchronizes the bit clock at the longest after a period of the reference clock (RT) and also generates a bit clock with the accuracy of an oscillator contained in the circuit according to the invention even after it has failed, whereby the data traffic in certain cases can be maintained until the fault is remedied.

The invention will now be described with reference to the figures, for example explained. It shows

Fig. 1 is a block diagram of the circuit according to the invention,

Fig. 2 shows the circuit with coincidence monitoring.

In Fig. 1, an oscillator 0 shown, in particular a quartz oscillator can be. It generates a high-frequency clock HT , which is an integer multiple m of a bit clock BT that is to be generated.

The clock HT is fed to a divider chain TK , which has a divider factor m and generates the desired bit clock BT at the output. A reference clock RT (the central clock of 75 Hz at Deutsche Bundespost, which has an accuracy of 10 ^-11 ) is fed to an edge detector F.

If the reference clock RT has a pulse-pause ratio of exactly 1: 1, the edge detector can generate an actuating pulse SI on every or every nth clock edge, otherwise only on every second or every 2nth clock edge. The actuating pulses SI are fed to an asynchronous reset input of the divider chain TK , and thus the divider chain TK generating the bit clock BT is synchronized by the reference clock RT .

The following is from using every other Clock edge out; when calculating the maximum The phase shift results in double Accuracy if every clock edge is used.  

Depending on the accuracy of the clock pulse HT , a maximum phase offset Δ a results with respect to the reference clock pulse RT if its inaccuracy is neglected:

GH mean the accuracy of the clock HT and f _RT the frequency of the reference clock RT .

The asynchronous resetting of the divider chain can result in an additional error Δ b of at most one period of the cycle HT :

f _HT is the frequency of the HT clock.

This results in a maximum total phase error of
Δ = Δ a + Δ b.

The maximum percentage jitter p , based on the bit clock BT, is then:
p = Δ × f _BT × 100%.

A numerical example shows which error in

f _RT = 75 Hz,
f _HT = 6144 kHz,
GH = 10 ^-4 ,
f _BT = 24 kHz
to be expected:

Δ a = Δ a + Δ b = 1.5 µs

p = Δ f · _BT · 100% = 3.6%

As this example shows, the invention is also with an oscillator with rather low accuracy in Data transmission systems applicable.

Common quartz oscillators have a ten to hundred times greater accuracy, so that is still essential better values are achievable. That way generated bit clocks ensure data output and -evaluation, which then also the CCITT recommendation V.24 and the EDS guidelines of the Deutsche Bundespost, the one Prescribe bit center sampling corresponds to if the Data have a data jitter up to a maximum of 50%.

In addition to the parts shown in FIG. 1, the circuit shown in FIG. 2 also contains a coincidence monitor K , which is also supplied with the reference clock RT , and a counter evaluation circuit ZS , which is connected to the divider chain TK . This counter evaluation circuit ZS then, when the divider chain reaches the counter reading that it should have as the last counter reading before the clock edge of the reference clock that normally arrives, sends a signal Zx to the coincidence monitor K , which then determines whether the edge of the signal is simultaneously with the signal Zx Reference clock arrives. The coincidence circuit normally gives an enable signal to the edge detector for each signal ZT , i.e. each time the counter reading is reached, which only works as described above when this enable signal is received, that is to say, when there is a clock edge of the reference clock, it gives an actuating pulse SI to the divider chain.

If the clock edge of the reference clock RT does not coincide with the signal Zx , ie if there is no coincidence, then no enable signal appears and therefore no actuating pulse SI . If this is the case, for example, three times in succession, the coincidence circuit emits a single release signal when the next clock edge of the reference clock RT occurs and thus ensures that the divider chain TK is reset, although the coincidence is not present. Therefore, this process can be described as a forced reset. This is followed by the normal operation described above, in which coincidence is a prerequisite for the release signal.

In other words: In the event of a brief fault (the multiple non-coincidence is considered a fault in the reference clock RT .), The synchronization of the bit clock BT with the reference clock is interrupted. This creates an effective filter against interference.

Claims (2)

1. Multiplexer / demultiplexer for a data transmission system with a circuit for generating a bit clock (BT) with the aid of a high-precision reference clock (RT) of lower frequency, characterized in that a freely oscillating oscillator ( 0 ) is present which has a high-frequency clock (HT) generates that a divider chain (TK) is present, which generates the bit clock (BT) from the high-frequency clock (HT) and which is synchronized by the reference clock (RT) . 2. Multiplexer / demultiplexer according to claim 1, characterized in that a device for detecting faults in the reference clock (RT) is present, which interrupts the synchronization with the reference clock (RT) when it has faults.