DE3828871A1 - NON-VOLATILE, ELECTRONIC COUNTERS - Google Patents

Abstract

A non-volatile electronic counter is divided into three sub-counters 14, 15 and 16 the sum of whose count values provides the total counter value and which are incremented cyclically. There exist therefore three relations between the possible count-values of the sub-counters for correct values. By comparing the count-values of the sub-counters after every incrementation; the relation between the count-values is checked and, if an error is detected, it is corrected before the next incrementation. Any such single error may be corrected to within a maximum uncertainty of 1 count-value. The counter may be used in an odometer. <IMAGE>

Description

This invention relates to an electrical meter, the electrically variable, non-volatile memory used. Such counters are increasingly used to mechanical counters to replace because they have lower costs, higher reliability and offer greater adaptability.

Electronic counters contain a number of digits that represent the respective meter reading display, each digit being encoded by a group of one or more bits, which are arranged in special places in the memory.

However, current solid-state technology has so far not offered any non-volatile memory that work without restrictions on the maximum number of write cycles that each memory location can be suspended, that is, how often each bit goes from 0 to 1 and can be changed back to 0. If only a small number of storage spaces is available on an integrated switching element, it becomes extremely important the cheapest way to find out how often each bit is changed.

A proposed method that uses the number of write cycles in a binary counter can be reduced by using a Gray-encoded counter. In a realization of a gray-coded counter, each digit is represented by encodes a large number of bits, the values of which at the parallel outputs of a particular one Shift register, at the input of which the reciprocal of its current output is located, to Will be provided. With each counting step, the information in each bit is changed by one Bit shifted so that actually only one bit is changed with each count and each bit on each count cycle of the shift register is subjected to only one write cycle becomes. The parallel outputs of each shift register thus provide a "Gray" encoded "display of the counter value for each special digit of the counter.

There is a known method for detecting and correcting a counter error in using multiple full counters and using majority logic to ensure the correct count when an error occurs. An odd one The number of counters is therefore desirable and three counters are often used. However, repeating the full counter is not economical and it can Limit the maximum counter display of a non-volatile counter.

In addition, to replace bad bits, the redundancy of a memory cell usually accomplished through addressing, lookup tables, and the like, to logically replace one memory bit with another. These procedures require  all that information about the address links in the non-volatile Memory are included, but the same error possibilities as the memory bits itself is exposed.

Accordingly, the present invention provides a non-volatile counter the at least three sub-counters, the sum of which provides a total counter value, and which are arranged so that they increase cyclically step by step, and a comparator that compares the values of the sub-counters, errors in any of the sub-counters detects and corrects such errors before the next step of the counter.

According to a preferred embodiment of the invention, the counter comprises three sub-counters which increase cyclically step by step, as a result of which the following relationships between the correct count values A, B and C of the corresponding sub-counters are successively fulfilled within a complete cycle of the counter:

A = B = C
A = B + 1 = C + 1
A = B = C + 1

The comparator preferably compares the counter readings of the sub-counters after each incrementally increase the counter to determine if any of the relationships above is met, and to correct the value of a sub-counter if an error is detected becomes.

The counter reading of each sub-counter is particularly convenient due to the number of Determines bits that are set in the sub-counter regardless of their position.

It is desirable that each sub-counter have a plurality of redundant bits contains, some of which are initially set and some of which are initially be reset.

The invention will now be described in more detail using an example, reference being made to the drawing, which is a realization of a not volatile electronic counter according to the invention shows how in a odometer is used.

The task of a non-volatile counter in a odometer is to collect the Store distance as determined by the number of input pulses received is shown. To achieve this, an EEPROM is used to store the information and this is usually updated every time Stand when a pulse arrives after every kilometer. The non-volatile Counter minimizes the amount of EEPROM required by the Erase / write cycle given restrictions and ensures high reliability with an error correction if possible.  

The counter is equipped with a linear address space that only requires normal bit decoding, but is divided into three sub-counters 14, 15 and 16 . Each of the three sub-counters is further divided into 6 rows of counters which contain a modulo 32 counter, three modulo 8 counters, a modulo 4 counter and a modulo 6 counter as indicated. This results in a total of eighteen logical counter groups in a complete counter 1.

The counter reading of the complete counter 1 is the sum of the values in the three sub-counters 14, 15 and 16 . The complete counter is incremented by incrementally increasing one of the three sub-counters in a cyclical manner, that is, with counter value 'N' , sub-counter 14 is increased in order to maintain counter reading A , with counter value 'N +1', sub-counter 15 is increased, to get the counter reading B , and at the counter value 'N +2', the sub-counter 16 is incremented to get the counter reading C. Therefore, there are only three relationships for casual counter values.

A = B = C (1)
A = B + 1 = C + 1 (2)
A = B = C + 1 (3)

The values of the sub-counters A, B and C are compared by means of a comparator which forms part of the control unit 12 in order to ensure that one of the above relationships is valid after each increase in the counter 1. If an error is detected, it will be corrected before the next increment of the counter.

Assuming for individual errors that the only time period in which an error can occur is that in which an increase in the counter was "intended" and that all errors are corrected before the next increase, the correct state of the sub-counter can be can be determined from the values of the other two sub-counters. This is due to the fact that the sub-counters are always incremented in the same order (first A , then B and then C) . Malfunctions that occur in this way can be corrected without counting errors occurring.

If a malfunction occurs with an accidental increase, then one can result in maximum error of one unit. This can be seen from the following examples:

• 1. If (1) B is falsified in the above case, the value can be corrected without resulting error. However, if A is falsified, the value can only be restored with one uncertainty from one unit, because it is not possible to distinguish between cases (1) and (2). If C is falsified, the value can only be restored with an uncertainty of one unit, because it is no longer possible to differentiate between cases (1) and (3).
• 2. In case (2), a falsified value C can be restored exactly. A or B have one unit uncertainty.
• 3. In case (3), a falsified value A can be restored exactly. B or C have one unit uncertainty.

This way, the detection and correction of an error after each step by step Increase the counter carried out. Having used a microprocessor core to tabulate the value of the odometer, it is advantageous to use a binary Counting system to use. It is also important that the EEPROM bits that the Save the meter reading, not the recommended maximum number of write / delete cycles Exceed (10,000). Taking these two criteria into account, the counter in be able to count to one million (1,000,000).

The counter is constructed in such a way that for each sub-counter each modulo counter contains a counting step which is a multiple of the capacity of the modulo counter in the previous rows. Therefore, if each modulo counter contains a maximum numerical value, ie a binary number, then the total numerical value for each sub-counter (A, B or C) is the product of the respective numerical values in the modulo counter that is to be increased, times a binary number. This number is the sum of the status of the first modulo counter plus the product of the counter readings of the first time that of the second modulo counter plus the product of the counter values of the first time that of the second times that of the third modulo counter and so on up to the count of the last modulo counter times the product of all previous modulo counters and finally times the total number of bits in the first modulo counter.

To keep the number of bits required in the counter to a minimum, the number of write / erase cycles for each bit must be kept small. This is done with a scheme in which only the number of ones (1's) stored in a modulo counter is significant. According to this criterion, the number of ones in a modulo counter is increased in the first phase of a counting cycle. In the second phase of the counting cycle, the number of ones is reduced, ie the bits are deleted, but the counter value is evaluated in such a way that the maximum counter value is less the number of ones. As a result, each bit experiences only a write / erase load during two counting cycles (one up, one down). It must therefore obviously be possible to determine in which phase of the counting cycle a modulo counter (N) is currently. This is done by looking at the value of the next modulo counter (N +1), ie looking in the next row. If that modulo counter is even, the counting cycle of the modulo counter N is in the first phase. If it is odd, the count cycle is in the second phase. Only the last modulo counter in each sub-counter is incremented.

With three sub-counters, each sub-counter must be capable of at least 333 334 Accumulate counting steps. Since the three modulo meters in row one mark the kilometers, these modulo counters experience the greatest number of write / erase loads. Out for this reason, a value of 31 bits was selected for these modulo counters, which one Counting range from 32 (0-31) results. The first row becomes a write / delete cycle all 64 kilometers exposed. On 333 334 kilometers, it is only 333 334/64 times or with less than 5300 write / erase cycles. All rows will be above the first exposed to even fewer cycles. The counter reading thirty-one (31) in the first row also meets the criterion of the maximum binary counter reading.

This counter scheme provides improved redundancy over simple bit duplication. Since only the number of ones in a modulo counter is important for the correct counter reading and not which special ones are, every redundant bit can replace every faulty bit. Therefore, if there are N true bits and N redundant bits, the first bad bit has N possible spare bits, the second bad bit (N -1) has possible spare bits and so on. If a redundant bit proves to be faulty, it is simply omitted and the next bit address is used.

Although the normal error mode of the EEPROM's is that a bit is not open a one can be programmed, it is possible that the reverse can happen. To allow this, a fixed number of bits are programmed to the 'one' state, which is a deviation from the 'zero' state. In the event that a bit is not can be deleted, a replacement bit is used instead.

It is therefore obvious that the invention represents a counter that is not that much Space used like previous counters, because each of the sub-counters for the count value is used and is not only used for the majority logic.

It will also be appreciated that counters according to the invention are also available in four or even more sub-counters can be divided if desired.

Claims (8)

1. A non-volatile electronic counter, characterized by at least three sub-counters, the sum of which provides a total counter reading and which are arranged in such a way that they are increased cyclically, and by a comparator which compares the values of the sub-counters, detects errors in any of the sub-counters and which corrects such errors before the counter is incremented the next time. 2. A non-volatile electronic counter according to claim 1, characterized by three sub-counters which are incremented cyclically, whereby the following between the correct counter readings A, B and C of the three corresponding sub-counters over a complete count cycle of three increments of the counter Relationships are fulfilled: A = B = C
A = B + 1 = C + 1
A = B = C + 1 3. A non-volatile electronic counter according to claim 2, characterized in that that the comparator increments the counts of the sub-counters after each Increase the counter compares to determine if any of the said relationships is satisfied, and to correct the value of one of the sub-counters, if one Error is detected. 4. A non-volatile electronic counter according to claim 2 or 3, characterized in that that each of the sub-counters has a modulo 32 counter, three modulo 8 Counter, a modulo 4 counter and a modulo 6 counter. 5. A non-volatile electronic counter according to any of the preceding claims, characterized in that each of said sub-counters has a plurality of counter bits and that the count of each sub-counter by the Number of bits is determined in the sub-counter regardless of their location are set. 6. A non-volatile electronic counter according to claim 5, characterized in that each sub-counter contains a plurality of redundant bits. 7. A non-volatile electronic counter according to claim 6, characterized in that that errors are corrected by omitting a bit that is considered to be incorrect was recognized, and by programming a redundant bit. 8. A non-volatile electronic counter according to claim 7, characterized in that that each sub-counter initially contains a plurality of redundant bits that are set and a variety of redundant bits that are reset  around erroneous bits found either as set or reset were to replace.