DE3807934B4 - Selective residual current device - Google Patents

Abstract

Residual Current Device with a summation current transformer and a trigger whose excitation winding (14) with an upstream controllable electronic valve (30) to the secondary winding of the summation current transformer via an electronic trigger circuit connected, which is a rectifier bridge circuit, an immediate at the output terminals connected charging capacitor (46) and a delay capacitor (50) contains wherein the charging capacitor (46) as a memory for the required for actuating the trigger Energy as well as the power supply of the electronic circuit (16) is dimensioned and the delay capacitor (50) Part of a charge capacitor (46) parallel to the electronic Valve (30) and the excitation winding (14) of the trigger switched RC element (48), characterized in that the residual current circuit breaker a selective residual current device is a CMOS logic (60) on the the electronic valve (30) when charging the charging capacitor (46) delayed increasing voltage of the delay capacitor (50) is controllable, wherein the CMOS logic (60) consists of several consecutive switched AND or NAND gates (64, 66, 68) with interconnected inputs exists that ...

Description

The The invention relates to a selective residual current device with a summation current transformer and a trigger whose excitation winding with an upstream controllable electronic valve to the secondary winding of the summation current transformer via an electronic trigger circuit connected, which is a rectifier bridge circuit, an immediate at the output terminals connected charging capacitor and a delay capacitor contains wherein the charging capacitor as memory for operating the shutter required energy as well as the power supply of the electronic Circuit is dimensioned and the delay capacitor part of a to the charging capacitor in parallel with the electronic valve and the excitation winding of the trigger switched RC element is.

selective Residual current circuit breakers have as a special version the task, due their triggering delay in branched plants in which both the main distribution and the subdistribution and the intervening plant parts in the fault current protection circuit are involved, a power off all consumers connected to the main distribution in case to prevent an insulation fault behind the subdistribution. For this purpose must The selective residual current circuit breakers in each country Regulations such as in the Federal Republic of Germany satisfy the VDE 0664. There are upper and lower limits for the tripping time, which are increasing Size of fault current in relation to decrease to nominal fault current.

at a known selective residual current device (Siemens magazine 42, 1968, No. 6, pp. 492-494), the tripping delay is provided by an RC element, to the output terminals of a rectifier bridge circuit in the secondary circuit of Summation current transformer is connected. Due to the spreading area such time delay circuits with pure RC elements has the known residual current circuit breaker a certain inaccuracy in the response of the downstream trigger.

Another known residual current circuit breaker ( DE 27 45 464 B1 , which is of the type mentioned, avoids this defect in that the circuit for charging the delay capacitor is designed as an electronic switching element whose main component is a consisting of a transistor and a Zener diode Konstantstromreglerkreis. This circuit provides a limited and constant current, with which the delay capacitor, to which the exciter winding of the trigger is directly connected, is charged. The result is a constant delay time regardless of the magnitude of the fault current, which does not satisfy the above conditions for selective residual current devices.

From the DE 31 27 331 C2 an electronic trigger circuit for a fault current protection circuit is known, in which the exciter winding of the trigger is preceded by a threshold switch, the response of which is stored in the delay capacitor energy of the exciter winding of the trigger is supplied. In this circuit too, the charging of the delay capacitor takes place via a constant current regulator, which keeps the tripping time substantially independent of the magnitude of the fault current constant.

The US 4,441,134 A describes a residual current circuit breaker whose control circuit is dependent on external energy from the feed network and whose natural fluctuations subject.

From the FR 2 044 475 A5 is a residual current circuit breaker of the type described above known. Since the charging process of the capacitor follows an E-function in this solution, the response of the downstream valve in the longer times of selective switching is very inaccurate and the VDE 0664 can not be maintained.

Of the Invention is based on the object, a selective residual current circuit breaker to create, with the simple and independent of External energy from the supply network or another source of energy a compliance with the increasing fault current in relation to Nominal residual current falling limit values according to the applicable Provisions becomes.

Based on a residual current circuit breaker of the type mentioned above, this object is achieved in that the residual current circuit breaker a selective residual current circuit breaker is, which comprises a CMOS logic, via which the electronic valve is controlled by the delaying when charging the charging capacitor voltage of the delay capacitor, wherein the CMOS logic consists of a plurality of series-connected AND or NAND gates with interconnected inputs, the inputs of the first gate are connected via a third ohmic resistor to a connection between the delay capacitor and a first ohmic resistance in the RC element and the output of the last gate is passed via a fourth ohmic resistance to the control electrode of the electronic valve.

Of the Charging capacitor of the residual current circuit breaker according to the invention thus forms together with the impedance of the secondary winding of the summation current transformer and the rectifier bridge circuit a first Integrator in which the on when a fault current occurs the secondary winding the summation current transformer generated voltage to provide the Energy for the trigger as well as the CMOS logic is stored. The occurring at the charging capacitor Voltage is at the delay capacitor integrated a second time to the tension build up at the entrance of the Delay CMOS logic. This works like a comparator and switches on reaching one Threshold voltage approximately equal to half the operating voltage of usually 5 volts from a logical O signal to a logical I signal or reversed at its output, causing the electronic valve controlled and the trigger is energized with the energy available in the charging capacitor.

ever bigger the Residual current is, the faster also the delay capacitor charged, and the sooner the CMOS logic will be switched. This one has a very small one Energy consumption and works with extremely low dispersion of Threshold voltage. Since the release of the stored in the charging capacitor Energy to the exciter winding of the trigger by that of the CMOS logic controlled electronic valve takes place abruptly, holding magnet releases can be used who, whose trigger energy fluctuates within wide limits. Because at nominal fault current only a small Current in the secondary winding to flow, can be many turns even with small dimensions of the toroidal core for the secondary winding install on the toroidal core, so that on the one hand the required Tension for the electronic circuit ensures On the other hand, the production costs are kept small can.

To In another feature of the invention, the CMOS logic consists of several one behind the other connected UND or NAND gates with themselves connected entrances, the inputs the first gate over a third ohmic resistance to the connection between the delay capacitor and the first ohmic resistor are connected in the RC element and the output of the last gate via a fourth ohmic Resistor is guided to the control electrode of the electronic valve. there contains the CMOS logic is expedient three NAND gate. By using such gates in particular Triple series connection is a particularly precise control ensured by the electronic valve.

In Advantageous embodiment of the invention is within the RC element to a first, with the delay capacitor in series ohmic resistance, the series connection of a second ohmic resistor and a zener diode connected in parallel, the second ohmic resistance when reaching their breakdown voltage connecting them. this leads to for larger fault currents in desired Way to a steeper course of the time-current characteristic between the delay time and the fault current, thereby ensuring compliance with the prescribed Borders continue to favor becomes.

To another feature for advantageous embodiment of the invention a Zener diode is connected in parallel with the charging capacitor, their breakdown voltage at least approximately at 5 times the nominal residual current occurring output voltage at the rectifier bridge circuit equivalent. This not only prevents the electronic Switching at higher fault currents with unacceptably high Tension is applied, but at the same time it ensures that that at higher Fault currents as 5 times the nominal residual current, the tripping time of the selective residual current circuit breaker continues to sink.

The electronic valve can in a further embodiment of the invention be a thyristor. However, it is particularly advantageous instead to use a PNP and an NPN transistor in cascade connection, by connecting their collectors and bases alternately where the output of the CMOS logic is at the base of the PNP transistor brought is. Such use is more common Transistors instead of a thyristor is much cheaper and cheaper let yourself easier to realize.

To re-operate the residual current circuit breaker after its response as soon as possible To make ready, provides a special embodiment feature of the invention that the CMOS logic is connected in parallel with a diode over which the delay capacitor can discharge again.

One embodiment The invention will be explained in more detail below in conjunction with the drawing. It demonstrate:

1 the circuit diagram of the electronic trip circuit in a two-pole selective residual current circuit breaker according to the invention,

2 a voltage-time diagram for illustrating the charging processes to the charging capacitor and the delay capacitor of the circuit according to 1 when the fault current occurs,

3 a time-current diagram with the course of the tripping time as a function of the size of an AC residual current in a circuit after 1 and

4 same diagram as in 3 with the course of the tripping time as a function of the size of a pulsating DC residual current at the different control angles provided for the testing of such switches.

In 1 are denoted by P and N of the phase conductors and the neutral of a single-phase low-voltage distribution network, via the switch contacts 10 a fault current circuit breaker, not shown in detail in its mechanical structure are performed. Among other things, this mechanical structure includes a switching mechanism that is indicated only symbolically 12 that when unlocking the switch contacts 10 opens under the action of a (not shown) Ausschaltfeder and thereby interrupts the power supply of the consumers connected to the network. The illustrated switch is a selective residual current circuit breaker for use in the main distribution, with further residual current circuit breakers of ordinary design in the subdistribution connected downstream of the loads.

For mechanical unlocking of the switching mechanism is a (not shown) trigger, which is useful in connection with the invention, a holding magnet release. His excitation winding is at 14 shown. The excitation winding 14 is about having one in their entirety 16 designated electronic trip circuit to the secondary winding 18 a summation current transformer 20 connected, whose only indicated schematically toroidal core 22 from the conductors P and N on the consumer side of the switching contacts 10 is enforced.

The electronic circuit operates in the illustrated embodiment with positive polarities and contains one to the secondary winding 18 of the summation current transformer 20 connected rectifier bridge circuit 24 with four diodes 26 , at whose positive output terminal an insulated bus bar 28 connected. The negative output terminal of the rectifier bridge circuit 24 is connected to ground. The bus conductor 28 ends at the entrance of an electronic valve 30 , that of the exciter winding 14 of the trigger and an antiparallel-connected freewheeling diode 32 immediately upstream. The secondary connections of the exciter winding 14 and the freewheeling diode 32 are grounded.

The electronic valve 30 can be a thyristor. In the embodiment, however, it consists of a PNP transistor 34 and an NPN transistor 36 in cascade, adding the collectors and bases through lines 38 . 40 alternately connected. The emitter of the NPN transistor 36 is to the excitation winding 14 or, the Zener diode 32 connected. Between the manifold 28 and the base of the PNP transistor 34 there is also an ohmic resistance 42 for biasing the base of the transistor 34 together with the resistance 70 ,

• – eine Zenerdiode 44,
• – ein Speicherkondensator 46,
• – ein RC-Glied 48.

Otherwise, lie between the manifold 28 and mass the following electronic switching components:

• - a zener diode 44 .
• - a storage capacitor 46 .
• - an RC element 48 ,

The storage capacitor 46 is sized so that when a fault current occurs, it can store both the energy required to energize the trigger and the power to supply the components of the electronic circuit.

The RC element 48 contains a delay capacitor 50 , which is a first ohmic resistance 52 and in parallel to this, the series connection of a Zener diode 54 and a second ohmic resistance 56 upstream.

The breakdown voltage of the Zener diode 44 is approximately matched to that voltage at 5 times the nominal residual current (5I _n ) at the output terminals of the rectifier bridge circuit 24 occurs. It prevents on the one hand overvoltages on the circuit components of the electronic circuit 16 On the other hand, it ensures that at fault currents greater than 5I _n from the charging of the delay capacitor 50 via the parallel-connected ohmic resistors 52 . 56 certain trip time is not further reduced.

To the connection point 58 between the resistances 52 . 56 and the delay capacitor 50 is a CMOS logic 60 connected, which consists of an input resistor 62 , three consecutive NAND gates 64 . 66 . 68 and an output resistance 70 consists. The second connection of the output resistance 70 is in one place 72 with the base of the PNP transistor 34 , the collector of the NPN transistor 36 leading line 40 and the resistance 42 connected. All inputs of each NAND gate 64 . 66 . 68 are connected together and connected together to the output of the preceding circuit component.

Between the joints 58 and 72 runs parallel to the CMOS logic 60 a line 74 with a forward biased diode 76 , whose function will be explained later, and parallel to the resistance 42 is a capacitor 78 low capacity switched to dissipation of parasite currents.

The operation of the above-described trigger circuit is the following:
As long as no fault current flows on the load side of the residual current circuit breaker, the flux of the toroidal core is 22 of the summation current transformer 20 "Zero", and in the secondary winding 18 of the summation current transformer 20 no voltage is induced.

Now occurs on the load side of the residual current circuit breaker on a fault current, which may be an AC residual current or a pulsating DC fault current or both, the balance of the oppositely flowing currents in the conductors P and N is disturbed. The resulting flooding of the toroidal core 22 induced in the secondary winding 18 a voltage equal to one in the rectifier bridge circuit 24 rectified current flow over the bus bar 28 to the condenser 46 causes the capacitor 46 charging. This charging takes place as the curve V ₁ in 2 shows, after an e-function and is essentially determined by the impedance of the secondary winding 18 and the rectifier bridge circuit 24 in conjunction with the capacitance of the capacitor 46 ,

The height of the potential reached on the line 28 depends first on the size of the fault current and will eventually reach the breakdown voltage of the zener diode 44 limited by this.

The itself at the storage capacitor 46 Anabolic voltage is above the busbar 28 also on the RC element 48 and causes also the delay capacitor 50 charging.

However, this charging takes place as the course of the voltage V2 on the delay capacitor 46 in 2 shows, compared to the storage capacitor further delayed. This delay is initially due to the resistance 52 whose resistance value together with the capacitance of the delay capacitor 50 provides a first delay constant T1. Only when with correspondingly large charging voltage of the storage capacitor 46 the breakdown voltage of the Zener diode 54 is reached, this switches the ohmic resistance 56 to the resistance 52 parallel, and the charging of the delay capacitor 50 occurs with a second time constant T2, which is smaller than T1 and consequently the charging of the delay capacitor 50 accelerated.

The itself at the delay capacitor 50 Ancillary voltage is also at the input of the CMOS circuit 60 at. The first NAND gate 64 acts as a comparator and switches when reaching a certain voltage level at its inputs, the output signal from 1 level to 0 level. Accordingly, the NAND gates 66, 68 also switch, namely the NAND gate 66 from 0-level to 1-level and the NAND gate 68 again from 1-level to 0-level, with the gate-to-gate switching becoming more and more pronounced. The last switch through the NAND gate 68 from 1 level to 0 level causes at the base of the connected transistor 34 in that first this transistor and as a result, the transistor 36 be turned on, ie the electronic valve 30 opens, causing the storage capacitor 46 about the excitation winding 14 to unload. This discharge actuates the trigger that holds the switch lock 12 unlatched and the switch contacts 10 opens.

The switching of the potential at the output of the NAND gate 68 and thus at the junction 72 from 1 level to 0 level has the further consequence that the delay capacitor 50 over the diode 76 able to unload immediately. This ensures that the delay capacitor is discharged when the residual current circuit breaker is re-energized.

wobei I_Δn der Nennfehlerstrom des Schalters ist, und sind in den beiden Diagrammen durch dünne Verbindungslinien t_{A min} bzw. t_{A max} veranschaulicht. Ferner sind mit i die Fehlerstromgrenzen bezeichnet, bis zu denen gemäß Ziff. 11.2 Fehlerstromschutzschalter nicht auslösen dürfen. Sie betragen bei Wechsel-Fehlerstrom (3) 0,5I_Δn und bei Gleich-Fehlerstrom (4) je nach dem Steuerwinkel α α = 0° el i₀ = 0,35 I_Δn α = 90° el i₉₀ = 0,25 I_Δn α = 135° el i₁₃₅ = 0,11 I_Δn The 3 and 4 show as the results of measurements on the same fault current circuit breaker, that the prescribed in the example of the German VDE regulation 0664 tolerance limits for the tripping times in fault alternating current ( 3 ) and with error control currents with different control angles of 0 °, 90 ° and 135 ° ( 4 ) be respected. These limits are in accordance with para. 25, Table 4 of that provision

where I _{Δn is} the nominal fault current of the switch, and are illustrated in the two diagrams by thin connecting lines t _{A min} and t _{A max} . Furthermore, the residual current limits are designated by i, up to those according to Ziff. 11.2 Do not trip the residual current circuit breaker. They amount to with alternating fault current ( 3 ) 0.5I _Δn and at _DC fault current ( 4 ) depending on the control angle α α = 0 ° el i ₀ = 0.35 I _Δn α = 90 ° el i ₉₀ = 0.25 I _Δn α = 135 ° el i ₁₃₅ = 0.11 I _Δn

problemlos eingehalten werden können.The measured tripping times are related by thick lines t _A - for DC residual currents with different control angles through them as index addition differences - and show that the above limits are within the full range of

can be easily complied with.

The resistance 52 is preferably adjustable and is set so that at nominal fault current, a time delay of 250 ms is obtained.

Claims (7)

Residual current circuit breaker with a summation current transformer and a trigger whose exciter winding ( 14 ) with an upstream controllable electronic valve ( 30 ) is connected to the secondary winding of the summation current transformer via an electronic triggering circuit, which comprises a rectifier bridge circuit, a charging capacitor connected directly to its output terminals ( 46 ) and a delay capacitor ( 50 ), wherein the charging capacitor ( 46 ) as memory for the energy required to actuate the trigger and the power supply of the electronic circuit ( 16 ) and the delay capacitor ( 50 ) Part of one to the charging capacitor ( 46 ) parallel to the electronic valve ( 30 ) and the excitation winding ( 14 ) of the trigger RC element ( 48 ) is there characterized in that the residual current circuit breaker is a selective residual current device having a CMOS logic ( 60 ), via which the electronic valve ( 30 ) from charging the charging capacitor ( 46 ) delayed rising voltage of the delay capacitor ( 50 ) is controllable, wherein the CMOS logic ( 60 ) of a plurality of AND or NAND gates connected in series ( 64 . 66 . 68 ) with interconnected inputs, the inputs of the first gate ( 64 ) via a third ohmic resistor ( 62 ) to a connection ( 58 ) between the delay capacitor ( 50 ) and a first ohmic resistance ( 52 ) in the RC element ( 48 ) and the output of the last gate ( 68 ) via a four ohmic resistance ( 70 ) to the control electrode of the electronic valve ( 30 ) is guided. Residual current circuit breaker according to claim 1, characterized in that within the RC element ( 48 ) to the first, with the delay capacitor ( 50 ) in series ohmic resistance ( 52 ) the series connection of a second ohmic resistor ( 56 ) and a zener diode ( 54 ) is connected in parallel. Residual-current circuit breaker according to Claim 1 or 2, characterized in that the CMOS logic consists of three NAND gates ( 64 . 66 . 68 ) consists. Residual current circuit breaker according to one of the preceding claims, characterized in that the electronic valve ( 30 ) is a thyristor. Residual current circuit breaker according to one of claims 1 to 4, characterized in that the electronic valve of a PNP and an NPN transistor ( 34 respectively. 36 ) is formed in cascade, whose collectors and bases are mutually connected to each other, wherein the output ( 72 ) of the CMOS logic ( 60 ) is brought to the base of the PNP transistor. Residual-current circuit breaker according to one of the preceding claims, characterized in that the CMOS logic ( 60 ) a diode ( 76 ) is connected in parallel. Residual-current circuit breaker according to one of the preceding claims, characterized in that parallel to the charging capacitor ( 46 ) a zener diode ( 44 ) whose breakdown voltage is at least approximately equal to the output voltage at the rectifier bridge circuit occurring at 5 times the nominal fault current ( 24 ) corresponds.