DE3807329A1 - Integrated analog/digital converter (n-bit parallel converter having only 2<n-1> digital sampling circuits and any output code) - Google Patents

Abstract

Parallel converters are among the fastest analog/digital converters because in this case the analog signal is compared simultaneously with 2<n> threshold voltages (including overflow) and an n-bit output word is already available only after one conversion step. The disadvantage of these converters is the large number of comparators and of the downstream digital sampling circuits. Converters are known which combine a number of comparators to form a multiple comparator having an alternating output characteristic. The output of a multiple comparator can no longer be unambiguously allocated to one code word transition which is why these converters are restricted to the Gray code. The novel converter uses double comparators, the output signals of which can be unambiguously allocated to one code word transition and thus any code can be generated by connecting an emitter-follower matrix downstream. For this purpose, the individual signals of the difference signal of a double comparator are applied to AND gates so that, with an output signal or code word change, the AND produces a logical '1' belonging to the new code word. The other AND input signal ensures that only one AND is ever a logical '1' (Figure 1, 3-bit binary converter). Fast analog/digital conversions, for example for digital signal processing. <IMAGE>

Description

Due to advancing digitization, e.g. B. the digital signal processing, analog / digital converter become the key element as a link between the analog side and the digital area. For the digitization of fast analog signals, fast parallel converters in particular are required. Parallel converters have a minimal conversion time, because here the analog signal is compared simultaneously with 2 ⁿ threshold voltages (including overflow) and the digital output word is already available after one conversion step. This converter also has the advantage that, because of its parallel structure, there is no need for upstream sample-and-hold circuits. The comparators quantize the analog signal continuously and the sample and hold function is performed by digital sampling circuits which are connected downstream of each comparator.

The disadvantage of the parallel converter arises from the large number of 2 ⁿ comparators plus sampling circuits and the associated high circuit complexity and the high power loss. For this reason, attempts are made to find clever converter circuits that retain the advantages of the parallel converter, but at the same time reduce the effort. Such solutions exist if it is taken into account that with a parallel converter only the comparator applies to:

U _an ≈ U _s (i)

(U _an = analog input voltage, U _s (i) = threshold voltage of the i th comparator)
contains the essential information for the analog / digital implementation. All the comparators below this comparator are 'switched on', all the comparators above them in the comparator chain are 'switched off' and can therefore be regarded as redundant. Under this condition, several comparators can now be combined to form a multiple comparator, the output voltage of which alternately changes its polarity when threshold voltages belonging to this multiple comparator are exceeded. Analog / digital converters are known in which comparators are suitably combined to form multiple comparators, so that the alternating transfer functions of the multiple comparators are brought into line with the periodic Gray code, Figure 1 and Table 1. The multiple comparators used realize the double function of comparison and the coding (analog coding). At first, multiple comparators only make sense with Cray code converters, because only because of the property of the Gray code applies: 2 ⁿ threshold voltages = 2 ⁿ bit changes, see Table 1. This means that multiple comparators isolate the bit positions of an n- bit code word from others Can encode bit positions, see Figure 1 (multiple comparator for bit position 0 with U _s (1), U _s (3), U _s (5) and U _s (7), multiple comparator for bit position 1 with U _s (2) and U _s (6) and multiple comparator for bit position 2 with U _s (4) and U _s (8)). From this follows: With Gray code analog coding, the total number of individual comparators combined into multiple comparators is exactly the same as the number of 2 ⁿ threshold voltages.

The same principle, e.g. B. applied to the binary code, but would require (2 ⁿ -1) · 2 single comparators, since (2 ⁿ -1) · 2 bit transitions occur in the binary code, compare table 1 binary code (multiple comparator for bit position 0 with U _s (1), U _s (2), U _s (3), ..., U _s (8), multiple comparator for bit position 1 with U _s (2), U _s (4), U _s (6) and U _s (8) and multiple comparator for bit position 2 with U _s (4) and U _s (8)). This would almost double the already critical input capacity of the analog / digital converter.

The invention provides a method and a circuit solution for the use of multiple comparators with any output codes, the number of individual comparators being limited to 2 ⁿ .

Here, the multiple comparators are reduced to double comparators with only two combined single comparators and the final coding to an n- bit code word of any code is produced using a simple digital coding method. This means that only 2 ^{n -1} digital sampling circuits are required, which leads to a significant saving in circuit complexity and power loss compared to the typical parallel converter. The double comparators work in a nested manner so that their two threshold voltages are separated by half the analog output range. This measure is necessary to limit the frequency multiplication of the analog input signal by the analog coding function (alternating transmission function) to a minimum, see Figure 2.

The function of a double comparator is given by:

where A is the differential output voltage of the double comparator and Δ U is the differential output voltage in the saturation range of the double comparator.

The method on which the invention is based uses the existing differential signal of the double comparator in conjunction with the monotony of the converter. Monotony means that with increasing input voltage, polarity changes occur at the double comparators, in the order: polarity change associated with U _s (1), U _s (2), U _s (3), etc.

This method differs from the typical parallel converter, where monotony by comparators on, d. H. e.g. B. positive output voltage is represented, thereby that now the monotony only about polarity changes, immediately in which direction is represented.

The mode of operation is explained using a 3-bit converter, Figure 3, and the associated time diagrams, Figure 4. For the sake of simplicity, only the double comparator with U _s (2) and U _s (6) is considered. For all others, the coding works in the same way. The digital sampling circuits shown in Figure 3 sample the output voltage A of the double comparators, regenerate them to a digital value and record this in time. These functions are called Z. An alternating differential signal A (2,6) appears at the output of the double comparator with polarity changes at U _s (2) and U _s (6), Figure 4a. The signal Z (A (2,6)) is obtained behind the sampling circuit. The individual signals at the inverted and non-inverted output of the sampling circuit are Z (A (2.6) _- ) or Z (A (2.6) ₊ ), Figure 4 b, c. A closer look at these individual signals reveals that the rising edges can be assigned to the threshold voltage or the code word transition. I.e. the falling edges must be eliminated by blocking the signal in front of the falling edge. An AND operation of Z (A (2.6) _- ) with Z (A (3.7) ₊ ) or Z (A (2.6) ₊ ) with Z (A (3.7) _- ) provides this function, see Figure 4 d, e, f, g. Furthermore, this AND operation ensures a 1 out of 2 ⁿ selection, so that only the AND gate which is assigned to the most significant polarity change shows a logical 1 at the output. The signal of the previous change is blocked by the higher polarity change, see U _s (2) in Figure 4 c, e, g.

So far there are only single signals behind the AND operation to disposal. However, these individual signals can be in one of van de Plasche, ESSCIRC 86, Digest of Technical Papers special emitter follower matrix again to differential Signals are merged. This will be Single signal of the AND gate on inverting and non-inverting Inputs of the bit positions are distributed so that the Code word associated with AND gate is generated so that the AND to inverting bit position inputs at '0' bits and on non-inverting inputs are switched at '1' bits.  

With each bit change, this leads to a differential signal change at the bit position inputs, e.g. B. code word change from 2 to 3, ie AND gate 2 from logic 1 to logic 0 and gate 3 from logic 0 to logic 1, all other AND gate outputs remain at logic 0. The bit position change is so noticeable in bit position 2⁰ that the inverted input switches to logic 0 and the non-inverted input switches to logic 1. All other bit positions must remain unchanged, which is guaranteed by the connected emitters of gates 2 and 3 at bit position inputs 2 1 and 2 2, see Figure 3 Emitter follower matrix.

Figure 5 shows the circuit diagram of the circuit arrangement required for the thresholds U _s (i) and U _s (i +2 ^{n -1} ). These include the double comparator, the digital sampling circuit and the digital coding with two AND functions. First a brief description of the circuit. The digital coding is then discussed in more detail. The double comparator consists of two non-negative feedback amplifiers, the upper differential amplifier T 2 , T 2 ' to the lower T 1 , T 1' is cross-coupled. Both differential amplifiers have the same current I 1 , I 2 . In order to provide the common transmission characteristic with an offset, a current source I 3 is connected to R 1 ' , the current around the base current is less than I 2 and I 1 . When the analog voltage rises, the lower differential amplifier switches over, then the upper one. If the voltage drops, the order is reversed. The resulting alternating output voltage is passed on to the sampling circuit via the emitter followers Ef 1 , Ef 1 ' . The sampling circuit consists of two switched differential amplifiers. T 3 , T 3 ' is responsible for the signal transfer, the differential amplifier T 4 , T 4' coupled via Ef 2 , Ef 2 ' forms the sampling function and the holding function. These amplifiers are switched depending on the scanning signal via T 5 , T 5 ' .

The sampled signal is regenerated in a second circuit. This second circuit T 8 , T 8 ' , T 9 , T 9' , T 10 , T 10 ' is basically identical to the sampling circuit, but is operated in phase opposition to the sampling circuit, see sampling signal in Figure 5.

The digital coding is also integrated in this second coupled circuit. For this purpose, the collector currents of T 8 and T 9 ' or of T 8' and T 9 via R 3 and R 4 or R 3 ' and R 4' are divided into two equal current components. A current component (R 4 , R 3 ' ) goes to the AND gate i -1 or i +2 ^{n -1} -1 and forms the AND function there. How the AND function is implemented, be at the AND gates i and i +2 ^{n -1} , consisting of R 5 ' , T 6' and the current component from T 7 in the circuit unit with U _s (i +1) and U _s (i +2 ^{n -1} +1) or R 5 , T 6 and the current component from T 7 ' in the above circuit unit, explained. For this purpose, only AND gate i is considered, gate i +2 ^{n -1} works in the same form. At the collector of T 6 ' , a logical 1 only occurs if there is no voltage drop at R 5' . I.e. the current through T 6 ' and the current through T 7 from the circuit unit with U _s (i +1) and U _s (i +2 ^{n -1} +1) is zero. This corresponds to a high potential at T 8 ' and T 9 , ie at the non-inverted output of the sampling circuit (i, i +2 ^{n -1} ) Z (A (i, i +2 ^{n -1} ) +) is logically equal to 1 and inverted output of the sampling circuit (i +1, i +2 ^{n -1} +1) with the transistors T 8 , T 9 ' , Z (A (i +1, i +2 ^{n -1} +1) -) is also logically the same 1. For all other combinations, either a current flows through T 6 ' or through T 7 from the circuit unit (i +1, i +2 ^{n -1} +1) or even through both transistors, so that in these cases there is always a voltage drop across R 5 ' occurs, and thus there is a logical 0. The AND function is thus fulfilled. It should be noted that when T 6 ' and T 7 are simultaneously conductive, a double voltage drop occurs at R 5' . It only occurs on one AND and is no longer noticeable in the emitter follower matrix, see Figure 3 , because the higher potential of an emitter follower dominates at common emitter points.

Figure 6 shows a circuit arrangement for the differential control of the input differential amplifiers with U _{an +} , U _{an -} , R ₊ , R _- and two resistor chains of eight resistors each for a 4-bit example. On the relationship between signal change speed and bandwidth,

the advantage of differential control can be seen (f = analog frequency, = analog modulation range). becomes

this leads to the doubling of f . Low-resistance and low-capacitance resistors are a prerequisite for a symmetrical resistor chain, because the entire resistor chain now works dynamically. The resistors, along with the direct current flowing through them, maintain the direct voltage between adjacent threshold voltages. Figure 7 shows a favorable arrangement of circuit units (double comparator, sampling circuit, AND gate), so that the length of the resistor chain, which is realized from interconnects, remains minimal. The circuit units are arranged in two rows, and the resistor chains have the shape of a 'rectangular' spiral.

The following are two more advantages of differential Analog control described. For parallel converters with digital Sampling is a synchronism of the distributed sampling and analog signal important. Under the justified assumption that runtime differences only for the currently switching double comparator are of interest:

( Δ T _i = transit time difference individual comparator i , t _Ab (x _i ) = transit time scanning signal of the individual comparator at point x _i , t _at (x _i , U _s (i)) = transit time of the analog signal at point x _i , depending on U _on and U _on = U _s (i)).

Since two single comparators are combined at one point to form a double comparator, which in turn is sampled at this point by the associated sampling circuit, one can write: x _i = x _{i +2} n -1, ie there is only one runtime for the sampling signal. Because of the voltage dependency, there are runtime differences in the analog signal. But this only with non-differential analog control. The following applies to differential control for reasons of symmetry:

t _an (x _i , U _s (i)) = t _an (x _i , U _s (i + 2 ^{n -1} )),

and thus Δ T _i =. There are no longer any runtime differences between U _s (i) and U _s (i + 2 ^{n -1} ), so that runtime compensation of the scanning and analog signals becomes easier.

The second advantage is the inherent static linearity of the symmetrical voltage divider chain. Loads on the voltage divider generally result in linearity errors, and the voltage division characteristic curve is bent downwards. In order to recognize the linearity, the error voltages at U _s (9) and U _s (10) are calculated. Requirements are R 1,. . ., R 8 and R 1 ' ,. . ., R 8 ′ is equal to R , Figure 6. For reasons of symmetry, the current distribution is I _bi = I _bi = I _{b 2} n _-1 . I.e. the voltage drops across the resistors of the chain, which are generated by comparators symmetrical to U _s (8) "switched on" or "switched off", do not form a differential voltage and are therefore not taken into account (I _b = differential amplifier, input current or base current).

The linearity error Δ U _s (10) - 2 · Δ U _s (9) goes towards zero for R ′ » R. This condition is for small resistance chains, e.g. B. Figure 6, always met.

Figure 8 shows another digital coding principle. It shows the coding of bit position zero of the Gray code using a 3-bit example. As already mentioned before, the bit positions of the Gray code can be coded separately from each other, which simplifies the emitter follower matrix in comparison to the binary code. Figure 8 shows how the sampled outputs of two double comparators Z (A (1.5)) and Z (A (3.7)) via AND gates, which logically '1' the gate output which corresponds to the most significant polarity change 'switch and digitally code using a simple emitter follower matrix. The principle is the same as the coding in Fig. 3 and Fig. 4. As shown in Fig. 5, the AND gates can be implemented in terms of circuitry.

Claims (5)

1. Integrated analog / digital parallel converter as a converter in bipolar technology can be integrated monolithically with digital scanning, characterized in that

• a) in the case of an n -bit converter, the analog signal (including overflow) is distributed to 2 ⁿ parallel differential amplifiers which are assigned to 2 ⁿ threshold voltages or code word transitions,
• b) whereby two differential amplifiers, whose threshold voltages differ exactly by half an analog modulation range, are interconnected to form a double comparator such that when the threshold of each individual differential amplifier is exceeded, a polarity change takes place at the common differential output of the double comparator (analog coding),
• c) so that with a total of 2 ^{n -1} double comparators whose output differential voltage is digitally sampled with only 2 ^{n -1} parallel sampling circuits,
• d) whereby, in the downstream coding stage, however, both polarity changes of the output differential voltage of a double comparator can be distinguished, so that just like in a typical parallel converter, each individual polarity change can be uniquely assigned to one of a total of 2 ⁿ code word transitions
• e) and a 1 out of 2 ⁿ selection and an emitter follower matrix can be used to generate any output code.

2. Integrated analog / digital parallel converter according to 1, characterized in that

• f) the converter, including the analog control, is operated entirely with differential signals.

3. Integrated analog / digital parallel converter according to 1, characterized in that

• g) in conjunction with f) a favorable arrangement of the scanning circuits in the chip design, low-capacitance resistors in the resistor chain, made possible by minimal interconnect lengths and
• h) in connection with f) enables a runtime compensation between analog and scanning signal.

4. Integrated analog / digital parallel converter according to 1, characterized in that

• i) the coding stage from d) is constructed in such a way that, for unique, non-redundant codes, identical parallel signal paths for each output of the 2 ^{n -1} sampling circuits (from the 1 out of 2 ⁿ selection via the emitter follower matrix to the n bit code word) consist.

5. Integrated analog / digital parallel converter according to 1, characterized in that

• j) the coding stage from d) with Gray code coding can be changed so that in separate sub-coding stages all bit positions of a code word can be coded independently of one another.