DE3784424D1 - Seitenaustauschsupervisor. - Google Patents

Seitenaustauschsupervisor.

Info

Publication number
DE3784424D1
DE3784424D1 DE8787108182T DE3784424T DE3784424D1 DE 3784424 D1 DE3784424 D1 DE 3784424D1 DE 8787108182 T DE8787108182 T DE 8787108182T DE 3784424 T DE3784424 T DE 3784424T DE 3784424 D1 DE3784424 D1 DE 3784424D1
Authority
DE
Germany
Prior art keywords
supervisor
side replacement
replacement
replacement supervisor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787108182T
Other languages
English (en)
Other versions
DE3784424T2 (de
Inventor
O'quin, Iii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3784424D1 publication Critical patent/DE3784424D1/de
Publication of DE3784424T2 publication Critical patent/DE3784424T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8787108182T 1986-06-27 1987-06-05 Seitenaustauschsupervisor. Expired - Fee Related DE3784424T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US87967586A 1986-06-27 1986-06-27
US4412187A 1987-05-04 1987-05-04

Publications (2)

Publication Number Publication Date
DE3784424D1 true DE3784424D1 (de) 1993-04-08
DE3784424T2 DE3784424T2 (de) 1993-09-23

Family

ID=26721201

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787108182T Expired - Fee Related DE3784424T2 (de) 1986-06-27 1987-06-05 Seitenaustauschsupervisor.

Country Status (3)

Country Link
EP (1) EP0262301B1 (de)
JP (1) JPS6325747A (de)
DE (1) DE3784424T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US7017008B2 (en) * 2000-12-29 2006-03-21 Intel Corporation Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
EP2540684A1 (de) 2011-06-30 2013-01-02 L'AIR LIQUIDE, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Poröses Material auf Silizium- und Portlanditbasis zur Hinterfüllung von Dämmziegeln mit kontrollierter Struktur, und entsprechendes Herstellungsverfahren
JP2016048502A (ja) 2014-08-28 2016-04-07 富士通株式会社 情報処理装置及びメモリアクセス処理方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414644A (en) * 1981-04-03 1983-11-08 International Business Machines Corporation Method and apparatus for discarding data from a buffer after reading such data

Also Published As

Publication number Publication date
JPH0564817B2 (de) 1993-09-16
EP0262301B1 (de) 1993-03-03
DE3784424T2 (de) 1993-09-23
EP0262301A2 (de) 1988-04-06
JPS6325747A (ja) 1988-02-03
EP0262301A3 (en) 1990-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee