DE3780526D1 - SYNCHRONIZATION DEVICE FOR THE INTERRUPT-LEVEL CHANGE MULTIPROCESSORS. - Google Patents

SYNCHRONIZATION DEVICE FOR THE INTERRUPT-LEVEL CHANGE MULTIPROCESSORS.

Info

Publication number
DE3780526D1
DE3780526D1 DE8787109194T DE3780526T DE3780526D1 DE 3780526 D1 DE3780526 D1 DE 3780526D1 DE 8787109194 T DE8787109194 T DE 8787109194T DE 3780526 T DE3780526 T DE 3780526T DE 3780526 D1 DE3780526 D1 DE 3780526D1
Authority
DE
Germany
Prior art keywords
multiprocessors
interrupt
level change
synchronization device
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787109194T
Other languages
German (de)
Other versions
DE3780526T2 (en
Inventor
James W Keeley
George J Barlow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Publication of DE3780526D1 publication Critical patent/DE3780526D1/en
Application granted granted Critical
Publication of DE3780526T2 publication Critical patent/DE3780526T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
DE8787109194T 1986-06-27 1987-06-26 SYNCHRONIZATION DEVICE FOR THE INTERRUPT-LEVEL CHANGE MULTIPROCESSORS. Expired - Fee Related DE3780526T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/879,858 US4802087A (en) 1986-06-27 1986-06-27 Multiprocessor level change synchronization apparatus

Publications (2)

Publication Number Publication Date
DE3780526D1 true DE3780526D1 (en) 1992-08-27
DE3780526T2 DE3780526T2 (en) 1992-12-17

Family

ID=25375026

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787109194T Expired - Fee Related DE3780526T2 (en) 1986-06-27 1987-06-26 SYNCHRONIZATION DEVICE FOR THE INTERRUPT-LEVEL CHANGE MULTIPROCESSORS.

Country Status (9)

Country Link
US (1) US4802087A (en)
EP (1) EP0251234B1 (en)
JP (1) JPH0786865B2 (en)
AU (1) AU597674B2 (en)
CA (1) CA1286415C (en)
DE (1) DE3780526T2 (en)
ES (1) ES2033742T3 (en)
MX (1) MX168705B (en)
YU (1) YU121287A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126751A (en) * 1987-11-11 1989-05-18 Fujitsu Ltd Grouping device
EP0357075A3 (en) * 1988-09-02 1991-12-11 Fujitsu Limited Data control device and system using the same
US5072365A (en) * 1989-12-27 1991-12-10 Motorola, Inc. Direct memory access controller using prioritized interrupts for varying bus mastership
FR2680591B1 (en) * 1991-08-22 1996-01-26 Telemecanique PROGRAMMABLE INTERRUPTION CONTROLLER, INTERRUPTIVE SYSTEM, AND INTERRUPTION CONTROL METHOD.
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
JP2008018340A (en) * 2006-07-13 2008-01-31 Trinc:Kk Apparatus for collecting floating material and apparatus for repelling floating material

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848233A (en) * 1971-11-01 1974-11-12 Bunker Ramo Method and apparatus for interfacing with a central processing unit
GB1448866A (en) * 1973-04-13 1976-09-08 Int Computers Ltd Microprogrammed data processing systems
US3999165A (en) * 1973-08-27 1976-12-21 Hitachi, Ltd. Interrupt information interface system
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
US4023143A (en) * 1975-10-28 1977-05-10 Cincinnati Milacron Inc. Fixed priority interrupt control circuit
US4035780A (en) * 1976-05-21 1977-07-12 Honeywell Information Systems, Inc. Priority interrupt logic circuits
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver
US4459665A (en) * 1979-01-31 1984-07-10 Honeywell Information Systems Inc. Data processing system having centralized bus priority resolution
NL7907179A (en) * 1979-09-27 1981-03-31 Philips Nv SIGNAL PROCESSOR DEVICE WITH CONDITIONAL INTERRUPT UNIT AND MULTIPROCESSOR SYSTEM WITH THESE SIGNAL PROCESSOR DEVICES.
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
JPS5827243A (en) * 1981-08-08 1983-02-17 Nippon Telegr & Teleph Corp <Ntt> Data processing system
US4464717A (en) * 1982-03-31 1984-08-07 Honeywell Information Systems Inc. Multilevel cache system with graceful degradation capability
JPS6115260A (en) * 1984-06-29 1986-01-23 Nec Corp Data processor

Also Published As

Publication number Publication date
MX168705B (en) 1993-06-04
EP0251234A2 (en) 1988-01-07
CA1286415C (en) 1991-07-16
YU121287A (en) 1990-06-30
JPH0786865B2 (en) 1995-09-20
JPS6332648A (en) 1988-02-12
AU597674B2 (en) 1990-06-07
EP0251234B1 (en) 1992-07-22
ES2033742T3 (en) 1993-04-01
DE3780526T2 (en) 1992-12-17
US4802087A (en) 1989-01-31
AU7478787A (en) 1988-01-07
EP0251234A3 (en) 1988-07-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL HN INFORMATION SYSTEMS INC., BILLERICA, MASS.

8339 Ceased/non-payment of the annual fee