DE3729333A1 - SURFACE WAVE CONDUCTOR - Google Patents

Description

The invention relates to surface acoustic waves forming monolithic surface wave spiral conductor a thin piezoelectric layer and a semiconductor, hereinafter referred to as the SAW spiral conductor.

In Figs. 14 and 15 of the accompanying drawings are cross sectional views of two different known monolithic spiral conductors high with a semiconductor substrate 1 concentration, an insulator 2, a thin piezoelectric layer 3, inputs 4 and 4 ', comb-shaped electrodes 5 and 5', an output 6 , a counter electrode 7 , a control electrode 8 and a thin semiconducting epitaxial layer 9 .

The configurations shown in FIGS. 14 and 15 differ in the semiconductor structure. In FIG. 14, a solid semiconductor substrate serves as the semiconductor, while in the embodiment shown in FIG. 15 a substrate is provided which is formed by epitaxial growth of a thin semiconducting layer on a semiconductor substrate with a high concentration, ie a substrate with a high impurity density. The various characteristics of this training are shown in the following publications:
1. BT Khuri - Yakub and GS Kino "A Detailed Theory of the Monolithic Zinc Oxide on Silicon Convolver", IEEE Trans. Sonics Ultrason., Vol. SU - 24, No. 1, January 1977, pages 34- 43,
2. JK Elliott, et al. "A wideband SAW convolver utilizing Sezawa waves in the metal - ZnO - SiO₂ - Si configuration", Appl. Phys. Lett. 32, May 1978, pages 515-516,
3. JE Bowers, et al. "Monolithic Sezawa wave Storage Correlators and Convolvers", IEEE Proc. Ultrasonics Symposium, 1980, pages 118-123,
4. S. Minagawa et al. "Efficient ZnO - SiO₂ - Si Sezawa wave Convolver", IEEE Trans. Sonics Ultrason., Vol. SU - 32, No. 5, September 1985, pages 670-674.

The documents 1, 2 and 3 show the properties of the spiral conductor shown in FIG. 14, while the document 4 describes the properties of the spiral conductor shown in FIG. 15.

A comparison of these reports shows that the configuration shown in FIG. 15 tends to show a higher value than the configuration shown in FIG. 14. In this regard, the use of a substrate with a thin epitaxial layer, as shown in FIG. 15, is more advantageous as a spiral conductor. However, no detailed theoretical or experimental studies have yet been carried out. There is therefore no information on the most favorable nature of such an epitaxial layer and no spiral conductor with the most favorable design has been developed to date.

The invention is therefore a SAW spiral conductor with the cheapest training considering the result the detailed analysis of the effects of a thin semiconducting Epitaxial layer are created.

In particular, the invention is intended to create a spiral conductor with the most favorable relationship between the thickness and the impurity density of the thin semiconducting epitaxial layer in the embodiment shown in FIG. 15.

For this purpose, the monolithic spiral conductor according to the invention comprises a highly concentrated semiconductor substrate, a thin semiconducting epitaxial layer which is formed by epitaxial growth on a surface of the semiconductor substrate, an insulator which is provided on the epitaxial layer, and a thin piezoelectric layer which is provided on the insulator, wherein the thin semiconducting epitaxial layer has a thickness L that satisfies the following relationship:

W _max < L W _max + 2 µm

where W _{max is} the maximum depletion width, which is expressed as:

where N denotes the impurity density of the thin epitaxial layer, n _i the intrinsic charge carrier density of the thin epitaxial layer, e _s the dielectric constant of the thin epitaxial layer, k the Boltzmann constant, e the elementary charge and T the absolute temperature.

The semiconductor preferably consists of silicon Si and the impurity density N is in the following range:

1 × 10¹³ cm ^-3 N 1 × 10¹⁶ cm ^-3

If a monolithic SAW spiral conductor is a highly concentrated one Semiconductor substrate, a first thin semiconducting layer on the substrate, a second thin semiconducting layer the first thin semiconducting layer, an insulator the second thin semiconducting layer and a thin piezoelectric Layer, then the first and second semiconducting thin layer semiconducting epitaxial layers from  opposite conductivity type and lies the overall strength the thin semiconducting epitaxial layers in the following area:

l ₂ < L l ₂ + W _m + 2 µm

where l ₂ is the thickness of the thin second semiconducting layer and W _{m is} expressed as:

where N ₁ the impurity density of the first thin semiconducting layer, n _i the intrinsic charge density of the thin first semiconducting layer, ε _s the dielectric constant of the first thin semiconducting layer, k the Boltzmann constant, e the size of the elementary charge and T the absolute temperature.

The semiconductor is preferably made of silicon Si and the impurity density N 1 of the thin epitaxial layers is in the following range:

1 × 10¹³ cm ^-3 N ₁ 1 × 10¹⁶ cm ^-3

The semiconductor can consist of GaAs. The insulator can essentially missing or consist of SiO₂. The thin piezoelectric Layer consists of ZnO or AlN and a Sezawawelle is a type of propagation of surface acoustic waves prefers.

The surface orientation of the Si is ( 110 ) with a direction of propagation [ 100 ] of the surface acoustic waves. The surface orientation of the Si can also be ( 100 ) with a direction of propagation [ 110 ] of the surface acoustic waves.

Fig. 1 shows an enlarged view of the design below the control electrode in Fig. 15. In Fig. 1, the same reference numerals as in Fig. 15 denote identical or corresponding components. In Fig. 1 may also be a depletion zone end 10, the end of the maximum depletion 11, the donor density in the thin epitaxial layer Nd, the acceptor density of the thin epitaxial layer Na, the strength of the thin epitaxial layer L, the maximum depletion width W _max, the depletion width W Thickness of the thin piezoelectric layer h , the frequency of a surface acoustic wave f , the wavelength of the surface acoustic wave λ and the bias voltage V _B are shown. With this configuration, the thickness L and the impurity concentration N of the thin semiconducting epitaxial layer are set in the following manner.

(A) The thickness L of the thin semiconducting epitaxial layer is determined to the following value with respect to the maximum depletion width W _max , which is given by the impurity density of the thin epitaxial layer (donor density for an N-type semiconductor and acceptor density for a P-type semiconductor).

W _max < L W _max + 2 µm (1)

where W _{max is} the maximum depletion range at room temperature (23 ° C) and the values L and W _{max are given} in µm. W _max can be expressed as:

where N is the impurity density of the thin epitaxial layer, which is equal to the donor density Nd if the epitaxial layer is an N-semiconductor or the acceptor density Na if the epitaxial layer is a P-semiconductor.

T is the absolute temperature:

T = 296 (K) (3)

ni is the intrinsic charge carrier density of the semiconducting layer, ε _s is the dielectric constant of the semiconducting layer, k is the Boltzmann constant and e is the elementary charge.

If silicon Si in particular is used as a semiconductor, the impurity density is preferably in addition to that Condition for the thickness of the thin epitaxial layer in the chosen the following way.

(B) If the semiconductor is made of Si, the thickness L of the thin epitaxial layer is selected so that it satisfies the expression (1) and the impurity density N is selected from the following range:

1 × 10¹³cm ^-3 N 1 × 10¹⁶cm ^-3 (4)

For comparison, FIG. 2 shows the relationship between the maximum depletion width W _max of Si and the impurity density Nd . In FIG. 2, N-type Si is shown. However, when P-type Si is used, the relationship is identical except that the donor density is replaced by the acceptor density. The following preferred values for the thickness of the thin epitaxial layer result from FIG. 2 and expression (1):

2.4 µm < L 4.4 µm
if N = 1 × 10¹⁴ cm ^-3
and 0.9 µm < L 2.9 µm
if N = 1 × 10¹⁵ cm ^-3 .

According to the invention, the ratios of the thin epitaxial layer in Fig. 15 as described in (A) and (B) above are chosen for the following reasons:

F _T (spiral conductor efficiency) of the spiral conductor can be expressed as:

F _T = 20 log γ ₂ - 10 log R _B - α Lg - 30 + L _e (5)

where γ ₂ is the nonlinear efficiency, R _B denotes the output resistance of the control part of the spiral conductor, α is the propagation loss of the surface acoustic waves and Lg denotes the control electrode length. Le is exposed to a fixed expression regardless of the proportions of the thin epitaxial layer and influences of the electromechanical coupling coefficient, the transducer losses, the strength and the dielectric constant of the thin piezoelectric layer, the frequency and wavelength of the acoustic surface waves, etc. Since Le is independent of influences from the thickness of the thin epitaxial layer, the corresponding expression or equation is missing. F _T (dBm) is determined in the following way with regard to the two inputs Pi ₁ and Pi ₂ and the output P ₀:

F _T = P ₀ - Pi ₁ - Pi ₂ (Pi ₁, Pi ₂ and P ₀ in µm)

The nonlinear constant γ ₂ has the following relation to the impurity density N of the thin epitaxial layer when the semiconductor surface of the spiral conductor is in an impoverished state or in an inverted state:

F _T shows a large value when the semiconductor surface is in a depleted or weakly inverted state. It can therefore be assumed that expression (6) is valid when the spiral conductor is activated. However, expression ( 6 ) is only valid if the thickness L of the thin epitaxial layer is greater than the depletion width W. If L is less than W , then the depletion end connects to the interface between the thin epitaxial layer and the highly concentrated semiconductor substrate (breakdown), which obviously prevents oscillation of the depletion end. In this case, the non-linear constant γ ₂ drops rapidly and this constant cannot be represented by expression (6). On a decrease of γ ₂ also F _T drops sharply due to the relationship of expression (5). Therefore, the following relationship is needed for the thickness of the thin epitaxial layer:

W < L (7)

The depletion width W changes with the bias voltage V _B at the control electrode, but does not exceed a maximum processing width W _max , which is shown in FIG. 1. The expression (7) is therefore practically not valid unless the thickness L of the thin epitaxial layer is greater than the maximum depletion width:

W _max < L (8)

That is one of the reasons for setting the bottom Limit of expression (1).

The following explains why the upper limit for the thickness L of the thin epitaxial layer is set in expression (1).

If L satisfies the expression (8), the non-linear constant γ ₂ is expressed by the expression (6) and this constant γ ₂ becomes independent of the thickness L of the thin epitaxial layer. The elements that provide F _T influences of the thickness L of the thin epitaxial layer are therefore the expressions of the output resistance R _B and the SAW propagation loss in expression (5). The following relationships result from expression (5):

• (i) F _T increases with decreasing R _B.
• (ii) F _T increases with decreasing reproductive loss.

Regarding the above result (i), when using a semiconducting epitaxial substrate as shown in FIG. 15, R _B can be reduced more than when using a solid semiconductor substrate as shown in FIG. 14. The reason for this is that the resistance of the highly concentrated semiconductor substrate under the thin epitaxial layer is extremely small. In this regard, the use of the epitaxial substrate is therefore more advantageous than the use of the solid substrate. This is also the result of publications 1) and 4). In practice, however, the resistance of the thin epitaxial layer, if it has a thickness below a given value, has almost no influence on F _T. The following Table 1 shows the numerical values of Δ F _T calculated according to expression (5) when N-type Si is used and the thickness of the thin epitaxial layer is selected in the following manner:

L = Wmax and L = Wmax + 2 µm

Table 1

In this case, the control electrode width is 1 mm and the control electrode length is 20 mm and the sum of the resistance of the highly concentrated semiconducting substrate, the resistance of a fixed connecting line and the ohmic resistance 1 Ω × Δ F _{T also} results from the calculation of the influences of the expression R _B in expression (5). However, as will be described later, it turns out that in practice, the value F _T changes by a few dB or more with a small change of about 2 µm in the thickness of the thin epitaxial layer. Under the influence of the thickness of the thin epitaxial layer, the propagation loss α thus has a greater influence on F _T than R _B.

The dependence of the propagation loss α on the thickness of the thin epitaxial layer was carefully analyzed and the influence of the dependence on F _{T was found to be} remarkable and the desired conditions regarding the thickness of the thin epitaxial layer were found. Such a dependency of the loss of propagation on the thickness of the thin epitaxial layer was previously unknown, so that the condition for the thickness of the thin epitaxial layer was determined for the first time on the basis of this dependency.

The following are special with the accompanying drawing preferred embodiments of the invention described in more detail. It shows

Fig. 1 is a schematic sectional view of a monolithic SAW helical conductor,

Fig. 2 is a graph showing the relationship between the donor density and the maximum depletion width,

Fig. 3 is a graph showing the relationship between the maximum depletion width, and the propagation loss,

FIGS. 4 to 12, the characteristics of an embodiment of the invention in monolithic graphs SAW helical conductor,

Fig. 13 is a cross-sectional view of another embodiment of the monolithic SAW helical conductor according to the invention and

FIGS. 14 and 15 different in cross-sectional views of two known monolithic helical conductor.

Fig. 3 shows an example of the dependence of the SAW propagation loss on the thickness of the thin epitaxial layer, wherein the surface acoustic wave propagates along a spiral conductor, which has a ZnO / SiO₂ / N-Si structure. The difference between the thickness of the thin epitaxial layer and the maximum depletion width is plotted on the abscissa and the loss of reproduction is plotted on the ordinate (dB / cm). This example is based on the following relationships: frequency of the surface acoustic wave f = 215 MHz, wavelength of the surface acoustic wave λ = 24 µm, thickness h of the thin piezoelectric layer (ZnO) = 5 µm, type of propagation of the surface acoustic waves is the Sezawa wave.

Nd is the donor density. The propagation loss is a value corresponding to a bias voltage V _B across the control electrode to maximize F _T. As shown in the drawing, the loss of reproduction is influenced not only by the impurity density, but also by the thickness of the thin epitaxial layer. The propagation loss increases with the thickness of the thin epitaxial layer and sometimes changes by several dB / cm or more with a change of approximately 2 µm in the thickness of the thin epitaxial layer. In comparison with the value in Table 1, it can be seen that with respect to the changes in F _T over the thickness of the thin epitaxial layer, the loss of propagation has a more significant influence than the initial resistance in this area of the thickness of the thin epitaxial layer.

In this connection, changes in F _{T were} measured under various conditions and the best conditions for the thin epitaxial layer were obtained by carefully considering the above-mentioned influences of reproductive loss. The results are shown graphically in FIGS. 4 to 12. Each graphic representation is based on a ZnO / SiO₂ / N-Si arrangement. In the graphs, f denotes the frequency of a surface acoustic wave, λ the wavelength of the surface acoustic wave, h the thickness of the thin ZnO layer, Nd the donor density and Na the acceptor density. The thickness of the thin SiO₂ layer is 0.1 µm.

Figs. 4 to 12 show the following relationships:

Fig. 4: Relationship between the thickness of the thin epitaxial layer and F _T at f = 215 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of 23 ° C.

Fig. 5: Relationship between the thickness of the thin epitaxial layer and the dynamic range at f = 215 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 23 nm and a temperature of 23 ° C.

Fig. 6: Relationship between the thickness of the thin epitaxial layer and F _T at f = 100 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of 23 ° C.

Fig. 7: Relationship between the thickness of the thin epitaxial layer and F _T at f = 400 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of 23 ° C.

Fig. 8: The relationship between the thickness of the thin epitaxial layer and F _T at f = 215 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of -20 ° C.

Fig. 9: The relationship between the thickness of the thin epitaxial layer and F _T at f = 215 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of -80 ° C.

Fig. 10: The relationship between the thickness of the thin epitaxial layer and F _T at f = 215 MHz, a Sezawa wave, an N-type semiconductor, a gate or control electrode length of 40 mm and a temperature of 23 ° C.

Fig. 11: The relationship between the thickness of the thin epitaxial layer and F _T at f = 200 MHz, a Rayleigh wave, an N-type semiconductor, a gate or control electrode length of 20 mm and a temperature of 23 ° C.

Fig. 12: The relationship between the thickness of the thin epitaxial layer and F _T at f = 215 MHz, a Sezawa wave, a P-type semiconductor, a gate or control electrode length of 20 mm and a temperature of 23 ° C.

In the graphs, the difference between the thickness of the thin epitaxial layer and the maximum depletion width at room temperature of 23 ° C. is plotted on the abscissa. The value of F _T corresponds to a bias voltage on the control electrode to maximize F _T.

From FIGS. 4 and 12 it is seen that F _T is markedly influenced by the thickness of the thin epitaxial layer and that F _T decreases with increasing thickness of the thin epitaxial layer. In this regard, there is a qualitatively similar tendency at different frequencies of the surface acoustic waves ( Figs. 4, 6 and 7), at different temperatures ( Figs. 4, 8 and 9), at different gate or control electrode lengths ( Figs. 4 and 10) Different types of propagation of the surface acoustic wave ( Fig. 4 and 11) and different conductivity types of the semiconductor ( Fig. 12) can be seen. Quantitatively, the effects of the thickness of the thin epitaxial layer are remarkable when the gate or the control electrode is long.

It follows from these results that the thickness of the thin epitaxial layer should be as small as possible in order to increase F _T. However, as shown in Fig. 5, F _T sometimes drops rapidly at low temperature when the epitaxial layer is so thin. The reason for this is that the depletion width tends to expand further at low temperature than at normal temperature and the depletion end directly connects to the interface of the thin epitaxial layer and the highly concentrated semiconductor region (breakdown) and is prevented from vibrating. These influencing factors represent another reason why the condition of expression (8) is required. The thin epitaxial layer must therefore be somewhat thicker than the maximum depletion width. In addition, the thickness of the thin epitaxial layer need not invite a large decrease in F _T.

According to the invention, the suitable thickness L of the thin epitaxial layer is selected within a range of 2 μm above the maximum depletion width Wmax :

L Wmax + 2 µm (9)

The reason for this is that if L is larger than Wmax +2 µm, F _T may drop 10 dB or more below the maximum value, as shown in Figs. 4 to 12. A comparison of FIGS. 8 and 9 also shows with respect to the temperature response that F _{T changes} strongly with the temperature when L is greater than Wmax +2 μm. In this regard too, the condition of Expression (9) is reasonable. From Fig. 5 it can be seen that there is no difficulty in this regard, since the dynamic range has a practically sufficient value even under the conditions of expression (9).

This is one reason why the upper limit of the thickness L for the thin epitaxial layer is set as indicated in Expression (1).

With regard to the influences of the impurity density of the thin epitaxial layer, it can be seen from FIGS. 4 to 12 that F _{T increases} with decreasing impurity density within the range of the thickness of the thin epitaxial layer according to expression (1). With regard to the dynamic range, however, it can be seen from FIG. 5 that this range decreases with the impurity density. If N <1 × 10 13 cm ^-3 , the dynamic range becomes approximately 30 dB, which is sufficient in practice.

On the other hand, F _T falls as N increases and F _T becomes about -60 dB or less when N <1 × 10¹⁶ cm ^-3 . In view of the arrangement of the thin piezoelectric layer and the semiconductor, which is expected to show a high F _T value, this value is too low. The impurity density is therefore preferably selected within the following range:

1 × 10¹³ cm ^-3 N 1 × 10¹⁶ cm ^-3

That is one reason why the impurity density is so determined is as indicated in expression (4).

In the above, the conditions (A) and (B) for the thin Epitaxial layer according to the invention explained.

The following is the use of the basic idea of the invention described for a SAW spiral conductor, which has a structure with a semiconducting epitaxial substrate. The conditions for the thin epitaxial layer for this case described below.

As described above, conditions (A) and (B) determine the conditions for the thickness of the thin epitaxial layer in a spiral conductor having the configuration shown in FIG. 15. The spiral conductor shown in FIG. 15 can be further developed into a spiral conductor which has the configuration shown in FIG. 13. It has been found that the spiral conductor with the design shown in FIG. 13 can work without pretensioning (Japanese Patent Application No. 60-202845) and that this design is extremely useful in its practical use.

The thin semiconductor epitaxial layer consists of a first thin semi-type epitaxial layer 9-1 and a second thin semi-type epitaxial layer 9 - 2. The first thin semiconductor epitaxial layer 9 - 1 is a semiconductor of the same conductivity type as that of the high-concentration semiconductor substrate 1, the thin second semiconducting epitaxial layer 9 whereas - 2, a semiconductor of the opposite conductivity type. When the first thin semiconductive epitaxial layer 9-1 from the N-type conductivity, then the second thin semiconductive epitaxial layer 9 - 2 P-conductivity type. In contrast, when the first thin semiconductive epitaxial layer 9-1 of the P-type conductivity, then the second thin semiconductive epitaxial layer 9-2 from the N-conductivity type. . The difference compared to the embodiment in Figure 15 is that the second thin semiconductive epitaxial layer 9 - 2 is provided by a different conductivity type in the epitaxial layer. In most cases, the second thin semiconductor epitaxial layer is 9 - formed by injecting ions 2 and has the thickness at the portion a value smaller than the considerably the strength of the first thin semiconductor epitaxial layer 9 - 1. Further, the impurity density and the thickness of the second thin semiconductor epitaxial layer are selected such that a depletion of the entire portion of the second thin semiconducting epitaxial layer 9 - 2 is effected when the bias voltage applied to the gate electrode 8 is zero. This design is intended to work best with zero bias. This configuration can therefore be viewed as if the depletion end in the first semi-conductive thin epitaxial layer 9 during the operation of the helical conductor - 1.

As described above, F _{T is} mainly determined by the non-linear constant γ ₂ and the propagation loss α , and the influences of the thickness of the thin epitaxial layer are reflected in particular by the propagation loss α . . During the work of a helical conductor with the training shown in Fig 13 on the other hand, the depletion end is located in the first thin semiconductor epitaxial layer 9-1, as described above. The non-linear constant γ ₂ is determined by the impurity density N at the point of depletion and is represented by expression (6). The propagation loss of the surface acoustic waves is further determined mainly by the internal energy loss in the semiconductor beyond the end of depletion, ie in the depletion region or in the weakly converted region. Considering the above-mentioned influencing factors can therefore be assumed that F _T mainly through the first thin semiconductive epitaxial layer 9 - is determined 1 well at in Fig training illustrated 13, and that the dependence of F _T of the thickness of the thin epitaxial layer also. is determined 1 and by the relationship between the position of the depletion end therein and the thickness of the epitaxial layer - by the impurity concentration of the first thin semiconductor epitaxial layer. 9

It is therefore reasonable to determine the conditions for the thickness of the thin epitaxial layer relative to the maximum depletion width using the same expression (1) as for the configuration shown in FIG. 15.

It should be noted, however, that the maximum processing width in the embodiment shown in Fig. 13 is represented by an expression different from the expression (2) because, unlike the embodiment shown in Fig. 15, the second thin semiconducting epitaxial layer 9 - 2 is present. When the second thin semiconductive epitaxial layer 9 - 2 a thickness l ₂ has Wmax is in the following range:

l ₂ < Wmax l ₂ + Wm (10)

where W is the maximum processing width in case that only the first thin semiconductive epitaxial layer 9-1 is present and is represented by the following expression:

wherein the impurity concentration of N ₁ first thin semiconducting epitaxial layer 9 - 1 and the other parameters are identical to those of the expression (2).

It is therefore reasonable to set the conditions for the thickness of the thin epitaxial layer in the configuration shown in Fig. 13 in the following manner.

(C) The thickness L of the thin epitaxial layer in the configuration shown in Fig. 13 is determined as follows:

l ₂ < L l ₂ + Wm + 2 µm (12)

wherein l ₂, the strength of the second thin semiconducting epitaxial layer 9 - 2, and Wm is given by the expression (11).

Further, since mainly through the first thin semiconductive epitaxial layer 9 in the embodiment shown in Figure 13 training F _T -. Is determined 1, it is reasonable to define the conditions for the impurity concentration of the thin epitaxial layer in the same manner as in the expression (4) as is given below.

(D) When Si is used as a conductor in the configuration shown in Fig. 13, the thickness L of the thin epitaxial layer is selected to satisfy the expression (12) and the impurity density N 1 of the first thin semiconducting epitaxial layer 9 - 1 selected from the following range:

1 × 10¹³ cm ^-3 N ₁ 1 × 10¹⁶ cm ^-3 (13)

The above conditions (A), (B), (C) and (D) are provided for the configurations shown in FIGS. 15 and 13. Among the designs shown in FIGS. 13 and 15, a design that does not contain an insulator 2 is also possible. Since the isolator 2 is very thin in most cases, no major changes occur either in the mode of propagation of the surface acoustic waves or in the potential loss in the semiconductor in the absence of the isolator 2 . The use of conditions (A), (B), (C) and (D) is therefore also expedient in the absence of the insulator 2 in the configurations shown in FIGS. 15 and 13.

As described above, by the invention monolithic SAW spiral conductor with good efficiency and good temperature response created.

The spiral ladder according to the invention can not only in all Devices that use a SAW spiral conductor, but also with other devices such as correlators, SSC communication devices, radar devices, Video processing devices, Fourier transformers etc. are applied.

Claims (18)

1. Monolithic surface wave spiral conductor with an arrangement of a thin piezoelectric layer, an insulator, a thin semiconducting epitaxial layer and a highly concentrated semiconducting substrate, characterized in that the thin semiconducting epitaxial layer has a thickness L in the following range: W _max < L W _max + 2 µm, where W _{max is} the maximum depletion width, which is given by: where N denotes the impurity density of the thin epitaxial layer, n _i the intrinsic charge carrier density of the thin epitaxial layer, ε _s the dielectric constant of the thin epitaxial layer, k the Boltzmann constant, e the elementary charge and T the absolute temperature. 2. spiral conductor according to claim 1, characterized in that the semiconductor is silicon (Si), and that the impurity density N of the thin epitaxial layer is in the following range: 1 × 10¹³ cm ^-3 N 1 × 10¹⁶ cm ^-3 3. spiral conductor according to claim 1, characterized in that the semiconductor is GaAs. 4. spiral conductor according to claim 1, characterized in that the insulator is SiO₂. 5. spiral conductor according to claim 1, characterized in that the thin piezoelectric layer is made of ZnO exists. 6. spiral conductor according to claim 1, characterized in that the thin piezoelectric layer is made of AlN exists. 7. spiral conductor according to claim 2, characterized in that the mode of reproduction of the acoustic Surface waves is the Sezawa wave. 8. spiral conductor according to claim 7, characterized in that the surface orientation of the Si ( 110 ), and that the direction of propagation of the surface acoustic waves is [ 100 ]. 9. spiral conductor according to claim 7, characterized in that the surface orientation of the Si ( 100 ), and that the direction of propagation of the surface acoustic waves is [ 110 ]. 10. monolithic surface wave spiral conductor with an arrangement of a thin piezoelectric layer, an insulator, a second semiconducting layer, a first semiconducting layer and a highly concentrated semiconducting substrate, characterized in that the first and second semiconducting layers are thin semiconducting epitaxial layers, the Conductivity type is opposite, and that the thickness L of the thin semiconducting epitaxial layer is in the following range: l ₂ < L l ₂ + W _m + 2 µm, where l ₂ is the thickness of the second semiconducting layer and W _{m is} given by: where N ₁ the impurity density of the first semiconducting layer, n _i the intrinsic charge density of the first semiconducting layer, e _s the dielectric constant of the first semiconducting layer, k the Boltzmann constant, e the size of the elementary charge and T the absolute temperature. 11. spiral conductor according to claim 10, characterized in that the semiconductor is silicon (Si), and that the impurity density N ₁ of the thin epitaxial layer is in the following range: 1 × 10¹³ cm ^-3 N ₁ 1 × 10¹⁶ cm ^-3 12. spiral conductor according to claim 10, characterized in that the semiconductor is GaAs. 13. spiral conductor according to claim 10, characterized in that the insulator is SiO₂. 14. spiral conductor according to claim 10, characterized in that the thin piezoelectric layer is made of ZnO exists. 15. spiral conductor according to claim 10, characterized in that the thin piezoelectric layer is made of AlN exists. 16. spiral conductor according to claim 11, characterized in that the mode of reproduction of the acoustic Surface waves is the Sezawa wave. 17. spiral conductor according to claim 16, characterized in that the surface orientation of the Si ( 110 ), and that the direction of propagation of the surface acoustic waves is [ 100 ]. 18. spiral conductor according to claim 16, characterized in that the surface orientation of the Si ( 100 ), and that the direction of propagation of the surface acoustic waves is [ 110 ].