DE3636234A1 - Thin-film field-effect transistor employing amorphous silicon - Google Patents

Abstract

A thin-film FET employing amorphous silicon is doped and structured in such a way that it is particularly usable in liquid-crystal display circuits. Critical FET dimensions which permit an optimum reduction in the source-gate capacitance and at the same time prevent large contact voltage drops occurring are specified, along with doping values and positions. The critical dimensions comprise the active channel length (L), the source-gate overlap (d) and the thickness (t) of the amorphous silicon. A critical mutual relationship is also specified for these parameters and the doping values of the amorphous silicon. <IMAGE>

Description

The invention relates generally to doped contact structures for field effect transistors (FETs) with amorphous Silicon. In particular, the invention relates to an FET device with an n-doped amorphous silicon layer that the intrinsic source and gate capacity reduced and the Performance of the device not by inducing of voltage drops at the source or gate contact deteriorated. The resulting FET device is special usable in matrix addressed liquid crystal displays (LCDs).

Amorphous silicon FETs are an attractive choice for high contrast flat panel television displays. These displays typically contain liquid crystal material which is arranged between electrically conductive electrodes which are arranged in a horizontal and in a vertical matrix, so that a large number of picture elements (pixels) result. The application of voltages to the electrodes orients the liquid crystal material so that the transmission of light through the material is affected. Since at least one set of electrodes (and their corresponding substrate) is transparent, a visible image is displayed. In this process, each pixel element works very much like an electrical capacitor. In fact, an effective liquid crystal capacitance C _LC is assigned to each pixel element. In the case of an FET addressed liquid crystal display (LCD), ideally, when an FET is switched on, the liquid crystal pixel capacitor C _LC charges to the data or drain line voltage. When the FET is turned off, the data voltage is stored on C _LC . However, there are many parasitic capacitances in the display structure that are not negligible compared to C _LC . Two important parasitic capacitances are the source-drain capacitance C _SD and the source-gate capacitance C _SG . The source gate capacity is of particular interest here.

The effect of the source-drain capacitance C _{SD is} considered. The worst case is when one element in one column of the display is turned off and all other elements in the column are turned on. In this case, the desired voltage C _LC on the pixel element capacitor should be zero, while the voltage V _LC on all other pixel elements in the column should be V ₀. The effective voltage on the data line is then approximately V ₀ and the voltage which is induced on the pixel element which is switched off is w V _LC = V ₀ C _SD / C _LC . In order for the pixel element to remain switched off, the sum of the induced voltages from this and all other parasitic capacitances must be less than the threshold voltage C _{th of} the liquid crystal material. The effect of C _SD on a gray scale display is critical, because if V _LC is set at a pixel to an intermediate value (V _th <V _LC <V _max), the value of V _LC to w V _LC can vary, depending on the State of the other items in the column.

The effect of the gate-source capacitance C _GS is similar, with the exception that the voltage waveforms on the gate line are coupled through C _GS and generate an additional undesirable voltage on the pixel electrode. Only the portion of the gate line waveform for which the gate voltage is less than the threshold voltage is looped through since the FET is sufficiently conductive above the threshold voltage to maintain the pixel voltage at the data line voltage.

The parasitic capacitances in an LCD display can be in two groups are divided: those by the FET structure are dependent and those that depend on the whole Matrix structure are dependent. The parasitic capacities, that depend on the FET structure include the source-drain capacitance and the source gate capacitance. The parasitic Capacities that depend on the matrix structure comprise the capacitances between the pixel electrode and the Gate and data lines. The latter will be capacities minimized by using structures with suitable address line widths, suitable distances between the address lines, more suitable Cell thickness and suitable liquid crystal material to get voted. The FET capacities are of primary interest here are minimized by the area of the gate, Source and drain electrodes made as small as possible becomes. This leads to FET designs with a small overlap area between the gate terminal and the electrode that the Touched indium tin oxide (ITO) pixels.

Conventional thin film FET structures in which the Contact on the side facing away from the induced electron channel Side of the silicon have many processing advantages. With LCD devices, they have the extra Advantage that data and scan line crossover isolation is achieved without extra processing. This structure can lead to reduced drain currents and to a Contact voltage drop result in what use in gray scale displays complicates. The nature of this contact structure also requires a larger contact area, the undesirably increases parasitic capacities, which occur with such FET devices.

Plots of drain currents versus drain voltage for conventional FET devices generally show non-ideal properties at low drain voltages. At these voltages, the dependence is almost parabolic, which results in a non-exponential charging behavior for the LCD pixel capacitor. An ideal device is generally linear in the behavior of the drain voltage versus the source voltage at low drain voltages. Non-ideal behavior leads to a drop in contact voltage V _c . This voltage drop is undesirable. However, the effect this drop in contact voltage has on the drain current reduction in the FET is less obvious. The contact voltage drop at higher drain currents is generally greater than V _c . This reduces the actual gate and drain voltages applied to the internal device structure, and thus the drain current, compared to what would otherwise be achievable.

To minimize the source-gate capacitance C _SG , it is generally desirable to reduce the overlap between the source and gate electrodes accordingly. However, this reduction leads to an increase in the contact voltage drop V _c .

It is accordingly an object of the invention to provide FETs with amorphous silicon to create a critical balance between minimal parasitic capacitance and control of contact voltage drop exhibit.

FET structures are also intended to be created by the invention in liquid crystal display devices, in particular in gray scale devices.

Furthermore, the parasitic source-gate capacitance is intended by the invention can be reduced in a thin film FET device.

In addition, the contact voltage drops are intended by the invention can be reduced in thin film FET devices.

After all, it should be understood without any limitation is a better performance by the invention of FETs with amorphous silicon by doping the amorphous ones Silicon layer in connection with the control of the  Overlap dimensions for the source and gate electrodes be achieved.

In a preferred embodiment of the invention, a thin film FET with amorphous silicon has an insulating substrate, a gate electrode arranged on this substrate, an insulating layer arranged over the gate electrode and an amorphous silicon layer arranged over the insulating layer and having a thickness t . The FET also has a drain electrode disposed on the amorphous silicon layer so that it partially overlaps the gate electrode. In addition, a source electrode is arranged on the amorphous silicon layer so that it defines a channel region of length L in the amorphous silicon layer and that the source and gate electrodes overlap by a distance d . In the present invention, the overlap distance is approximately given by d _cc = c µ _e / (2 L α ) , where c is the gate capacity per unit area, µ _{e is} the effective electron mobility in the amorphous silicon and α is the ratio between the current density J in the direction from the gate electrode to the source electrode in the area of their overlap and the gate voltage is also in the n-th power, in which case n is 2 (see FIG. equation 16 below and the equation 11 foregoing discussion). The invention particularly seeks to control α . In the above formula, c is the dielectric constant associated with the insulating layer divided by the thickness h of the insulating layer. In this way, the overlap d and α are mutually related. In fact, they are critically interrelated, since overlap distances much larger than those given above produce a channel current in saturation that is independent of contact overlap, so that the output current begins to decrease rapidly.

Embodiments of the invention are described below Described in more detail with reference to the drawings. It shows

Fig. 1 is a diagram illustrating the use of FETs in matrix-addressed liquid crystal displays,

Fig. 2 is a diagram illustrating (shown in phantom), the presence of parasitic capacitances in an FET device, used in particular in a in a liquid crystal display,

Fig. 3 is a cross-sectional side view of a typical thin film FET illustrates the physical structure and the dimensions,

Fig. 4 to test a cross-sectional side view of a replacement device that is used here experimentally to certain parameters relationships

Fig. 5 is a cross-sectional side view of an enlarged portion of Fig. 3 for better illustrating the vertical current density J,

Fig. 6 is a graph of the drain current d to the source or drain overlap distance,

Fig. 7 is a graph of the calculated and the measured drain current versus drain voltage at a gate voltage of 8 volts,

Fig. 8 is a graph of the measured current density over the voltage and temperature for the circuit shown in Fig. 4 structure,

Fig. 9 is a diagram of the contact current density over the contact voltage drop for a plurality of thicknesses of silicon at a temperature of 20 ° C,

Fig. 10 is a graph of the calculated lateral current I and the vertical current density J for various overlapping routes,

Fig. 11 is a diagram in Fig. 10, except that the drain voltage is 2 volts similar here instead of 10 volts,

Fig. 12 is a graph of the calculated drain current (solid lines) over the source contact path overlap for different channel lengths L, wherein the dashed curves show a quadratic approximation of the contact-limited current for small overlap,

Fig. 13 is a graph of the calculated drain current versus source overlap for the same conditions as in Fig. 12, except a silicon thickness of 0.2 microns instead of a thickness of 0.3 microns as shown in Fig. 12,

FIG. 14 shows a diagram of calculated (drawn with a solid line) and measured characteristic curves of the drain current versus the drain voltage at a gate voltage of 8 volts, and

Fig. 15 is a graph of the calculated drain current as a function of the silicon thickness.

The amorphous silicon thin film field effect transistors according to the invention are particularly useful in liquid crystal display devices. In particular, the devices according to the invention show reduced capacitive effects and reduced contact voltage drop effects, which is advantageous in these devices. A circuit diagram of a conventional matrix addressed liquid crystal display is shown in FIG. 1. FETs 50 are connected to (usually transparent) pixel electrodes 40 . Each FET 50 is connected to one of a plurality of gate lines 42 . Likewise, the drain electrode of each FET 50 is connected to a data line 41 . Accordingly, the source electrode of each FET is typically connected to the pixel electrode. The conventional arrangement is to arrange the pixel elements in the form of a rectangular grid, part of which is shown in FIG. 1. Accordingly, Fig. 1 shows a context in which the device according to the invention can be used.

As stated above, there is still a problem of parasitic capacitance in FET devices. In particular, the problems addressed in the present use are directed to the parasitic capacitance that exists between the source and gate electrodes in an amorphous thin film silicon FET. An electrical circuit diagram, which illustrates the presence of these parasitic capacitances (shown in broken lines), is shown in FIG. 2. The parasitic capacitances C _GS and C _SD are present in the circuit in addition to the effective capacitance C _LC , which is present as a result of placing liquid crystal material between electrically conductive electrodes.

Amorphous silicon FET devices for use in liquid crystal displays are known. However, the present invention relates to FET structures that have certain critical dimensional criteria and to control the doping in the amorphous silicon. The relevant physical dimensions are illustrated in Figure 3, which shows a cross-sectional view of a conventional thin film FET. An electrically conductive gate electrode 22 is typically applied to an insulating substrate 20 , which is made of glass, for example. A layer 24 of insulating material, for example silicon nitride, is then applied over the gate electrode and part of the underlying substrate 20 and serves as the gate insulating material. A layer 26 of amorphous silicon is then applied over the insulating layer 24 . The hydrogenated silicon and silicon nitride films are made by conventional plasma enhanced chemical vapor deposition (PECVD) at plasma frequencies from approximately 50 kHz to 13 MHz. For example, silane (SiH₄) diluted with 90% argon can be used for silicon deposits and a mixture of silane and ammonia and argon can be used to deposit a silicon nitride layer. Helium, neon or no thinner can also be used. To produce the N⁺-doped layer 28 , silane doped with about 1% phosphine (PH₃) and further diluted with argon can be used. The thicknesses of the N⁺ silicon, the intrinsic silicon and the nitride are typically 50 nanometers, 200 nanometers and 150 nanometers, respectively. The conductivity of the N⁺ layer can be up to 10 ^-2 Siemens per centimeter at 20 ° C and an activation energy of 0.21 electron volts (eV). The contact metal for the drain electrode 30 and the source electrode 35 can comprise vacuum-deposited molybdenum. The N⁺ layer is removed from the channel area by drum plasma etching in an atmosphere of carbon tetrafluoride, CF₄, combined with 8% oxygen. However, it should be noted that the present invention is not limited to these particular processes, compositions, methods or areas.

However, a better understanding of the invention requires consideration of particular dimensional aspects shown in FIG. 3. In particular, the distance between the source electrode 35 and the drain electrode 30 is such that a channel region is created which has a length L. This is an important dimension in the practice of the invention. In addition, it can be seen that the source electrode 35 and the gate electrode 22 overlap by a distance d as shown. It can also be seen that the amorphous silicon layer 26 has a thickness t . This thickness is directly related to the parameter α , which is described below (see Equation 16). Another dimension is the thickness h of the insulating layer 24 . In the sense that the layer 24 has dielectric material which is arranged between the source and the gate electrode, it has a certain capacitance c per unit area, where c = ε _s / h , where ε is the dielectric constant that of the layer 24 is assigned. In fact, the present application teaches that for proper operation these dimensions are critically related, cf. Equation 15 below. In the present invention, c is about 4 x 10 ^-8 farads / cm².

As indicated above, one of the significant parameters in the geometric configuration of the invention is the overlap distance d between the source and gate electrodes. This overlap has a certain effect on the drain current. This fact is indicated in Fig. 6. The lower curve in FIG. 6 is the measured drain current at V _G = 8 volts and V _D = 10 volts as a function of the source overlap distance d for an FET with a gate electrode width W of 100 μm and a channel length L of 7 μm. The drain electrode 30 has a larger overlap that is larger than 2 μm. Also shown in Fig. 6 is the drain current with the reverse drive voltage so that the side of the device with the small overlap becomes the drain electrode. Since the channel field breakdown occurs near the drain electrode in saturation, the overlap near the drain electrode can actually be negative before the drain current is reduced. The points inserted in Fig. 6 show experimental data obtained for source overlap and the x represent data obtained for drain overlap. The data in FIG. 6 was obtained using a device similar to that shown in FIG. 3.

Figure 7 shows the characteristics of drain current versus drain voltage for multiple devices. The curves shown in solid lines in FIG. 7 apply to the model calculations described below. The circles represent experimental data measurements. The non-ideal behavior at low drain voltages, which is almost parabolic, leads to a non-exponential charging behavior for the LCD pixel capacitor C _LC . For matrix-addressed displays with gray scale, the voltage on the pixel capacitor must be set within a few tenths of a volt from an applied total voltage of (typically) 5 volts. Because of the non-ideal drain characteristic, the charging time to a value within the required 5% or less of the applied voltage can be greater than the permitted dwell time of approximately 10 ^-5 seconds in typical displays. Failure to fully set can be compensated by a voltage offset, but changes in the contact voltage drop behavior on the display are still a problem. It is therefore desirable to understand and minimize this contact voltage drop behavior. Both the reduction in the ON current with decreasing overlap and this drop in contact voltage are clearly mutually related phenomena. The voltage drop across the source contact reduces both the effective internal gate-source voltage and the internal drain-source voltage.

In an attempt to understand and minimize this voltage drop behavior, the current-voltage characteristics of the metallic N⁺ contact, the N⁺ / intrinsic silicon structure and the influence of the silicon layer thickness as well as the doping on the voltage drop and the ON currents were examined been. The structure used for this study is shown in FIG. 4. In this experimental configuration, molybdenum contacts on opposite sides of a 500 nanometer thick layer of almost intrinsic silicon (i-Si) were used. The intrinsic silicon also included a 50 nanometer thick layer of N⁺-doped silicon on each side in contact with the molybdenum electrode. The contact structure can be modeled as a nin structure. The current through this structure can be limited by the contact resistance at the molybdenum / N⁺ interface or by a space charge-limited current flow through the intrinsic layer. The conductivity of the N⁺ layer, which is 7 × 10 ^-3 Siemens / cm, is too high to form a limitation.

The current-voltage characteristics of the Mo / N⁺ / Mo structures are almost linear and can be represented well by the following relationship: J _C = bV , where b = 1.9 × 10⁶ A / V-cm² exp (-0.33 eV / kT) . Here T is the temperature and k is the Boltzmann constant. This characteristic cannot be explained by the N⁺ material, which has a 100 times higher conductivity, namely 7 × 10 ^-3 Siemens / cm, and a lower activation energy of 0.21 electron volts. This is therefore an inevitable limitation of the Mo / N⁺ contact. Mo / N⁺ / Mo structures that are produced by using different application conditions for the N⁺ layer have somewhat different properties. These different manufacturing conditions include high frequency power or argon dilution.

Fig. 8 shows the measured current-voltage characteristic curves at several temperatures. These data have been corrected for the voltage drop at the Mo / N⁺ interface. The points shown are experimental data and the solid lines are an adaptation to this data. Only one polarity is shown in Figure 8, but the curves for the case of opposite polarity are symmetrical. The behavior up to about 3 volts can be understood as a current flow limited by space charge in the intrinsic layer. Model and experimental data on the space charge-limited current flow in amorphous silicon (a-Si) structures have already been explained in the prior art, cf. W. Den Boer, J. Phys. Paris, Vol. 42, C4, page 451 (1981) and KD Mackenzie, PG Le Comber and WE Spear, Phil. Mag., Vol. B46, pp. 377-389 (1982). At very low voltages, the current is ohmic, and the size and the temperature dependence correspond to the volume conductivity of the intrinsic layer with σ ₀ = 308 Siemens / cm and an activation energy of 0.58 electron volts. This shows that the intrinsic layer does not become impoverished in small fields. This coincides with the capture density of 5 × 10¹⁶ # / cm³ / eV, which is determined from the size of the space charge-limited current at higher applied voltages. This capture density implies a screen length of 115 nm or less than 25% of the film thickness. At higher voltages, the dependence in V becomes quadratic, which is characteristic of space charge-limited current flow with a simple constant trapping density at even higher powers of V at higher voltages, because the quasi-Fermi level reaches the area of non-uniform trapping density. The capture density can be determined from the space charge limited currents. For the data of Fig. 8, it is 5 x 10¹⁶ # / cm³ / eV near the equilibrium fermin level. Fitting this data into a polynomial gives the following equation:

J _sc = a ₁ (T) V / t + a ₂ (T) V ² / t ³ + a ₄ (T) V ⁴ / t ⁷ (1)

where the coefficients a _i all have the form a _i = a _{i 0} exp (- E _{i 0} / kT) , with experimental prefactors a _{i 0} of 308, 7.7 × 10 ^{-7 and 3.4 × 10, respectively -3 and activation energies E _{i 0} of 0.58, 0.54 and 0.4 electron volts, respectively. The values of a ₁, a ₂ and a ₄ have as units volts, cm and A / cm² for V, t and J _sc , respectively. Above, T is the temperature, measured in degrees Kelvin, and k is the Boltzmann constant. The form of equation 1 corresponds to the scaling law for the space charge limited current J / t = V / t 2, so that it can be applied to other thicknesses t of intrinsic silicon, provided the same material properties. Fig. 9 shows the current density-voltage characteristics of Mo / N⁺ / i-Si contacts, which have been determined from separately measured characteristics of Mo / N⁺ and N⁺ / i-Si structures. The Mo / N⁺ curves are determined from J _c = bV as above and are only due to the voltage drops at the Mo / N⁺ interface (ie at zero thickness of intrinsic silicon). Using the usual gradual channel approximation for the FET characteristic and the approximation that the channel conductance is proportional to the local field, the effect of the contact voltage drop on the FET properties can be modeled in the model. When the FET is in saturation, the channel current is given by: I _D = 0.5 (W / L) c µ _e (V _G - V _T - V _sc ² (2) where V _{sc is} the voltage drop between the channel at the Edge of the source contact and the metal of the source contact and V _{T is} the threshold voltage. In the materials used in the invention, the electron mobility µ _{e is} typically between 0.5 and 0.8 cm² / volt. In saturation the contact voltage drop is only important at the contact with the lowest voltage (source), because of the very strong electric fields near the drain electrode The contact voltage drop V _sc at the source contact is determined by: I _D = J _c (V _sc ) Wd _c (3) where d _c an effective contact overlap distance and J _c, the current density at the edge of the contact is, which is the channel on the next. d _c = d applies to very small contact overlapping routes. For larger contact overlapping the current distribution must be calculated under the contact, and an effective d _c must a can be determined from the contact current distribution. d _c is generally not constant for a given FET structure, but depends on the gate and drain bias. However, it is roughly constant and is a useful quantity because it allows physical insight. Three methods for determining d _c and the dependence of the drain current on the actual overlap d are considered. First, the distance scale of the current drop under the contact can be estimated from the following equation: d _c -1 = 2 (1 / J) (∂ J / ∂ x) = (1 / J) (∂ J ∂ V) (∂ V / ∂ x) (4) where x is the distance along the channel and under the contact and all sizes are evaluated on the edge of the contact that is closest to the channel, cf. Figure 5. V is the voltage along the channel both under the contact and in the FET channel. J is the current density at the contact. The equation is an approximation that assumes that the thickness of the silicon is thin compared to the lateral dimension. The factor 2 defines d _c such that the total contact current is approximately d _c J ₀, where J ₀ is the current density at the edge of the contact. When the FET is in saturation, the channel current results from equation 2 and the current at the edge of the source contact is given by the following equation: I _D = W (∂ V / ∂ x) c µ _e (V _G - V _T - V _sc ) (5) For all simulations the following applies: c = 3.8 × 10-8 farads / cm², µ _e = 0.26 cm² / V and V _T = 2 V. If these two identical currents are equated, the result is the derivative of V and therefore the estimate for the maximum effective contact distance, namely: d _cc = (L / (V _G - V _T - V _sc )) ( V _sc / n) (6) where n is the power law slope of the contact current density at V = V _sc , cf. in this regard Fig. 9. The second term is of the order of magnitude and for typical values of the other parameters d _{cc is} approximately 2 µm. This estimate is a reasonable match with Fig. 6 when the maximum drain current is reached with an overlap distance of approximately 1 µm. Therefore, contact overlap distances of more than 1 to 2 µm have little effect on the contact voltage drop or the drain current. The conclusion is confirmed by the more accurate replication in the model given below. A more precise method is to calculate the current distribution under the contact for a finite contact overlap. The channel current I _D is given by the following standard equations: for V _G - V _T < V _D for V _G - V _T < V _D When approximating that the silicon film is thin compared to the lateral dimensions, the following equation applies: where J is taken from Fig. 9. The lateral current I (x) flowing in the channel under the contact is related to the voltage V (x) under the contact: where G (V) = µ _e cV . This form for the layer conductance G of the FET channel is an approximation, which is satisfactory in strong accumulation, but does not need to be sufficient near the threshold value. It is the form of the conductance that leads to Equation 7. These three equations can be combined into a first and second order equation pair: in which and These can be solved for V (x) , I (x) and J (x) by using a forward iteration and a second order Taylor series for V (x) . The initial limit condition V (x) = V _sc is the contact voltage drop. This is changed to achieve I (d) = 0, where d is the contact overlap distance. This approximation assumes that the contact current stops abruptly at the edge of the gate boundary. This approximation takes place in the same sense as the separation of the vertical current J and the lateral current I (cf. FIG. 5) and is valid if the silicon thickness is small compared to the contact overlap. Fig. 10, the contact current density J 3.8 shows (dashed curves) and the lateral current I (solid curves) for the contact tracks overlapping 0.5, 1, 2, 8 and 20 microns. The vertical scale applies only to the lateral current I. The standard for the current density J is any unit. The silicon thickness is 300 nanometers and the temperature is 20 ° C. In the invention, the amorphous silicon layer is preferably less than 300 nm thick, and more preferably about 150 nm thick. Other parameters are given in Fig. 10. The drain current without any drop in contact voltage is 2.5 µA. For an overlap of less than 1 µm, the contact current density is almost independent of x , but increases as d decreases. This fact is the basis of a useful approximation, which is explained below. It should be noted that the drain current is almost independent of the overlap if the overlap distances are greater than 1 µm. This is despite the fact that as the contact overlap increases there is considerable current flow under the contact at long distances from the source edge. The reason for this is the high degree of non-linearity in the contact current. Figure 11 shows a similar calculation for a reduced drain voltage of 2 volts. Although the device is not in saturation, the basic shape of the curves is similar. Fig. 12 shows the channel current I _D through the contact overlap d for the same conditions as in Fig. 10. Fig. 13 shows similar calculations for 0.2 micron silicon thickness and contains the data from Fig. 6. The channel length for the devices of FIG. 6 is 7 µm. There is a reasonable match considering how difficult it is to visually estimate such small overlaps. The model does not predict a drain current for d <0, but fringe fields allow some current flow even with negative overlaps. The simple one-dimensional model cannot take these effects into account. However, the model pretty much predicts the characteristic overlap distance of 1 µm, which has been determined experimentally. Figures 12 and 13 show that contact voltage drop is a very significant problem in shorter channel FETs. For L = 0.5 µm, the ON current is 15% of the maximum possible value without contact voltage drop with a silicon thickness of 0.3 µm. The exact reduction in the ON current depends on the silicon thickness and the silicon quality (trap density), but the effect of the contact voltage drop is always stronger with shorter channel lengths. As mentioned above with reference to Figures 10 and 11, the magnitude of the drain current for contact overlaps greater than 1 µm does not mean that there is insignificant contact current flow over distances greater than 1 µm for larger contact overlaps. This paradoxical result is based on the strong dependence of the contact current on the voltage. On the basis of the observation that the contact current density between x = 0 and x = d is almost uniform with a small overlap, a closed form expression for the channel current with a small overlap can be obtained. In this approximation, J = J (V (0)) and I _D = J (V (0) Wd) . These two equations and equation 2 are solved for V (0) = V _SC and I _D for certain approximations of J. If J = α V n , with n = 2 or 4, then it holds where: V (0) = (((1-4 µ ( V _T - V _G )) ½ - 1) / 2 µ n = 4 (12) or V (0) = V _G - V _T ) / (µ + 1) n = 2 (13) and µ² = (Ld α ) / (c µ _e ) (14) In equation 14, α from Fig. 9 can be estimated as a function of the contact current density. The dashed curves in Fig. 12 are this approximation with n = 2 and α = 0.2 A / cm² / Volt². This approximation is good enough to be useful. It fails with a small overlap because J is better represented by n = 3 in this area. This approximation can be used to estimate the slope of I _D overlap d . Using this slope from equations 11 and 3 with n = 2, a critical contact overlap d _cc = I _{C 0} / (∂ I _D / δ d) is determined, where I _{D 0 is} the drain current for a zero contact voltage drop. An important conclusion is the fact that d _cc is related to the FET geometry by the following approximation: For overlap distances that are much larger than d _cc , the saturation channel current becomes independent of the contact overlap. This approximation shows the significant dependencies of the minimum contact overlap distance on the device and material parameters. If this formula is used, it should be checked whether the work area remains in the area where J can be approximated as a quadratic function. Although the above explanation shows a method for experimentally determining α , it can also be shown that α is related to the thickness and trapping density of the undoped or lightly doped silicon layer, as follows: where N _{e is} the replacement density of conduction band additives and N _{t is} the density of band gap middle states. ε is the relative dielectric constant, which is approximately 12.8 for silicon. ε ₀ is the dielectric constant of free space. The difference E _c - E _fn is the distance of the quasi-Fermi levels from the conduction band edge. A good approximation is E _fn = E _f , where E _{f is} the Fermi level. As indicated above, µ _{e is} the electron mobility in amorphous silicon. For amorphous silicon, and most semiconductors N _e is about 10²¹ # / cm³. For good amorphous silicon, N _{t is} typically between about 10¹⁵ and 10¹⁷ # / cm³ / electron volt. It can generally be seen that α is a material-dependent property. α is between about 0.1 and 1 A / cm² / Volt² for undoped amorphous silicon and is much larger for weakly doped amorphous silicon. α can also be increased by reducing the density of bandgap center states N. In the invention, the doping increases the value of α by a factor of about 50, so that α is between about 5 and 50 A / cm² / Volt². The particular invention described here relates to weakly doping the silicon layer with an n-type dopant, such as P or Sb. This is achieved by mixing gases containing n-dopant, such as PH₃, with the SiH₄ used, to deposit the amorphous silicon or by ion implantation of the n-type dopant atoms into the silicon. In the latter case, masking is used to restrict the dopants to the contact areas and thereby eliminate the somewhat adverse effects of the dopants on the channel region of the FET. The doping of the amorphous silicon leads to a considerable increase in α (cf. equation 16) and therefore drastically reduces the critical contact overlap distance d _cc (cf. equation 15). This allows a significant reduction in the contact overlap distance d and thereby a reduction in the source-gate capacitance. For example, phosphorus doping is used to achieve a conductivity of about 2 × 10-5 Siemens / cm in the amorphous silicon at room temperature. Note, however, that α is inversely proportional to N _t , so better amorphous silicon material with a lower density of band gap states has a smaller α and therefore a smaller d _cc . It should also be noted that when the material is doped with phosphorus or other N-type dopant, the difference E _c - E _{f is} reduced. For a 0.1 electron volt change in E _c - E _f a rises at room temperature on the 47fache. The solid curves in Figures 7 and 14 are simulations of drain current versus drain voltage using the exact model (Equation 10). Substantially equivalent results are obtained by calculating the drain current overlap using the exact model at a given bias (e.g., see FIG. 12) and using this current to select an effective overlap d _c , which is adapted to the approximate model (equations 3 and 7). In Fig. 7, note the significant effect of the intrinsic silicon layer thickness on the maximum ON current and also the contact voltage drop behavior at low drain voltages. The theoretical device with an intrinsic silicon thickness of zero has only the voltage drop due to the Mo / N⁺ interface. The ideal contact curve does not include a voltage drop across the contacts. FIGS. 7 and 14 also show some experimental data for FETs with different intrinsic silicon thickness and different dopings. L = 7 µm and W = 200 µm apply to all devices. Curves (a) and (d) apply to 300 nm thick intrinsic silicon, (b) to 200 nm thick intrinsic silicon and (c) to 200 nm thick, weakly doped with phosphorus with a conductivity at room temperature of 2 × 10-5 Siemens / cm. The contact overlap for these devices is between 1 and 1.5 µm, except for curve (d) where it is 5 µm. Curve (d) is the same device structure as curve (a), except that the contact overlap is 5 µm. Note the small increase in the ON current for the increase in contact overlap by this factor 5. The device with a weakly N-doped active silicon layer, curve (c), behaves like a device through the Mo / N⁺ contact and is not limited by conduction limited conduction. This can be explained with the theory of space charge limited currents due to a change in the ratio of free to trapped electrons, since in the V ² area the space charge limited current should be proportional to exp [- (E _C - E _f ) / kT ] (cf. Equation 16). The substantial increase in current and the reduction in contact voltage drop behavior at low drain voltages confirms the expected reduction in α when the silicon layer is weakly n-doped. Of course, the weak doping of the channel tends to increase the OFF currents. Because of the small amount of dopant introduced in the above experiment, however, OFF currents at V _G = -5 volts of less than 10-10 amps have been achieved. The theory and data in Figure 7 show that there is a significant loss in device performance with intrinsic silicon layers thicker than 300 nanometers. Figure 15 summarizes this conclusion. It shows exact model calculations based on equation 10 and the contact voltage drop data of the drain current shown in FIG. 9 at V _G = 8 V and V _D = 10 V over the silicon thickness for two source-gate overlaps. Note the rather small effect of 1 µm versus 5 µm overlap. The drain current decreases rapidly below 1 µm. These results depend on the quality (bandgap center capture density) and the Fermi level of the silicon layer in the channel. Reducing the bandgap center capture density reduces the contact voltage drop. Changes in the Fermi level of the intrinsic silicon layer have an even greater impact. The critical thickness for the deterioration of the performance of the device thus depends on various treatment processes. The answer to the question of whether weak N-type doping is useful depends critically on the OFF current requirements for the particular use. In sum, it can be seen that there is a critical relationship between the channel length L , the source-gate overlap d , the silicon thickness t and α . In particular, it can be seen that the efforts to reduce the source-gate overlap to reduce the parasitic capacitance C _SG are critically limited by the fact that this procedure causes a voltage drop on the contacts. According to the invention, however, a maximum silicon thickness and minimum overlap distances are provided in the geometry of the device together with an α- Si doping to control a in order to reduce this problem to an acceptable value. It should also be noted that reducing the silicon thickness to a small value can reduce the contact voltage drop. However, this has undesirable effects on device processing and threshold voltage control. Therefore, the largest possible silicon thickness is usually desirable.}

Claims (7)

1. Thin film field effect transistor with amorphous silicon, in particular for use in liquid crystal display devices, characterized by :
an insulating substrate ( 20 );
a gate electrode ( 22 ) disposed on the insulating substrate ( 20 );
an insulating layer ( 24 ) disposed over the gate electrode ( 22 );
an amorphous silicon layer ( 26 ) disposed over the insulating layer ( 24 ) and having a thickness t ;
a drain electrode ( 30 ) disposed on the amorphous silicon layer ( 26 ) so that it is partially superimposed on the gate electrode ( 22 );
a source electrode ( 35 ) disposed on the amorphous silicon layer ( 26 ) so as to define a channel region of length L in the amorphous silicon layer, the channel region in the amorphous silicon layer being between the source electrode ( 35 ) and the drain electrode ( 30 ) extends and the source electrode is superimposed on the gate electrode by a distance d ;
where the distance d is approximately given by c µ _e / (2 L α ), where c is the gate capacity per unit area, µ _{e is} the effective electron mobility in the amorphous silicon layer ( 26 ) and α is between about 5 amperes / cm² / volt² and 50 Ampere / cm² / volt². 2. Transistor according to claim 1, characterized in that the thickness t is less than about 300 nm. 3. Transistor according to claim 1, characterized in that the thickness t is approximately 150 nm. 4. Transistor according to one of claims 1 to 3, characterized in that µ _{e is} between about 0.5 cm² / volt and 0.8 cm² / volt. 5. Transistor according to one of claims 1 to 4, characterized in that c is about 4 × 10 ^-8 farads / cm². 6. Transistor according to one of claims 1 to 5, characterized in that the overlap distance d is less than about 1 micron. 7. Transistor according to one of claims 1 to 6, characterized in that the amorphous silicon layer is phosphorus-doped in order to achieve a conductivity of about 2 × 10 ^-5 Siemens / cm at room temperature.