DE3633227A1 - Arrangement for conversion of a virtual address into a physical address for a working memory organised in pages in a data processing system - Google Patents

Abstract

An arrangement for conversion of virtual addresses into physical addresses in a data processing system, using an address translation memory. The address translation memory contains a segment table address register, a register for the virtual addresses, a working memory subdivision register, which subdivides the working memory into a user part and a system part, a comparator which is assigned to the working memory subdivision register, a working memory address register, and control logic. An ATM memory, which is connected indirectly via a comparator unit to the control logic, is provided. A circuit arrangement consisting of an associative memory (ASS) with an associated control unit (ASS-ST), with a multiplexer (MUX) connected in series, is inserted between the segment table address register (STAR) and the ATM memory (ATM-MEM). The multiplexer (MUX) has two signal inputs, one signal output and one signal input. A signal (VADR SYP), which indicates whether a given address is a system address or a user address, can be fed to the control input of the comparator (K) which is assigned to the register for the virtual addresses (VADR). <IMAGE>

Description

The present invention relates to an arrangement for converting virtual addresses into physical ones Addresses in a data processing system using a Address translation memory, the address translation Store a segment table address register Register for the virtual addresses, a memory Subdivision register, which is the memory divided into a user and a system part, a comparator assigned to this, a working memory Contains address registers and control logic and an address translation (ATM) memory is provided is, which is indirectly via a comparator unit with the Control logic is connected.

Known assemblies of the aforementioned type use an address translation memory (ATM Address Translation Memory) or a plurality of such memory next to one another in teilassoziativem operation, see FIG. 1 and FIG. 2.

A problem with this circuit is that the ATM's have very broad words. Because this store usually have to be very fast, you can in the Practice do not have a large capacity.

The present invention has for its object to provide an arrangement for converting virtual addresses into physical addresses in a data processing system, the performance of which is increased compared to known arrangements of this type and / or in which the effort in address translation memories ATM compared to known ones Orders is reduced.

The object underlying the invention is achieved by an arrangement of the type mentioned and according solved the preamble of the claim, thereby is characterized in that between the segment table Address register and the ATM memory circuitry - consisting of an associative memory with associated control with a downstream multiplexer - inserted, which multiplexer has two signal inputs, a signal output and a control input having, the control input from the comparator assigned to the register for the virtual addresses is a signal can be supplied that is a statement about whether an address considered is a system address or a user address, where in the case where the address under consideration is a System address is the second signal input of the multiplexer, on which there is a predetermined signal whose signal output is switched through that Signal output of the multiplexer divided into two parts is, namely in a first part with a first Group of bit lines and in a second part with a second group of bit lines, the first Part of the data input of the ATM memory and a first Comparator within the comparator unit and the second part together with part of an output of the Register for the virtual address of the address input of the ATM memory is supplied, and that at one as new recognized entry in the segment table address register the memory area associated with the associative coding in the ATM memory by the control logic as undefined is marked.  

In the following, the invention is illustrated by several figures explained in detail.

Fig. 1 shows a logical ATM structure with an ATM memory according to a known arrangement.

Fig. 2 shows a logical ATM-structure with two associative memories ATM according to another prior art arrangement.

Fig. 3 shows an arrangement according to the invention for an associative memory application for compressing the ATM memory width.

Fig. 4 is a block structure according to the invention shows the ATM.

Fig. 5 shows an overall view of the invention according to the proposed ATM fabric.

Fig. 6 shows a table for different ATM memory devices.

In order to clearly assign an ATM entry to a virtual address space, the STB (segment table basis) was previously included in the entry. This should now be replaced according to the invention in the prior art. An associative memory is now addressed with the STB . A much shorter "code" is obtained from this, which is now to be used in the ATM word instead of STB , see FIG. 3.

The ATM can be implemented deeper. A normal increase in the ATM depth, however, results in a value that is approx. . ., 64, 128, 256,. . . is no longer an improvement because the deletion effort reduces or even exceeds the additional performance gain. Increasing the ATM depth is profitable if it is divided into ATM blocks and an ATM block is assigned to a virtual address space, that is to say an associative memory cell, see FIG. 4.

These measures are independent of one another. You can applied together or selectively. The associative memory is essential for both, and for reduction the STB entry (this can even be omitted entirely, if the number of ATM blocks is the same as the number of associative memory cells is made) or stochastically about the use of the ATM blocks to distribute more evenly (but there are also direct ones here Addressing methods, i.e. without associative memory, possible).

The associative memory is not time critical if the do not constantly change virtual address spaces. As a "code" can e.g. B. the associative memory internal physical Address of the associative memory cells used if it exists.

If you change to a new virtual address space, the associated STB value is not yet contained in the associative memory. According to a selection mechanism, an associative memory cell is to be selected and described with the current STB value. For selection, an LRU mechanism can be used that can manage more than two associative memory cells (LRU = L east R ecently U sed). For this purpose, the cells of the associated ATM block must be set to "invalid".

The used in the figures and their description Reference symbols have the following meanings:

ATM A ddress T ranslation M emory CPU C entral P rocessing U hit STAR S egment t abellen- A Dress R egister, "anchor" for the tables of the virtual address translation STB S egment t ables b asis address VADR V irtuelles Ad ress r egister SXH S egmentinde x, "H igh" part SXL S egmentinde x, "L ow" portion PX page index (P age Inde x) LOC-side local address part FRAME physical page start address K K omparator LRU L east R ecently U sed, the least recently used CX C ODE Inde x CXH C ODE Inde x, "H igh" part CXL C x ODE Inde, "L ow" part valid flag for valid / invalid entry SYP Sy stem P ARTION

As already explained, FIG. 1 shows a logical ATM structure with an ATM memory according to a known arrangement. A virtual address enters a register VADR from a CPU . An ATM memory is addressed with SXL / PX .

If ATM SXH = SXH , ATM STB = STB and the conditions for the required storage ring protection and storage key protection are not violated, a "hit" is reported and ATM FRAME concatenated with LOC forms the physical address. Otherwise there is a "miss" (valid entry, but no hit) or an interruption (hit, but conditions violated; status change necessary; error message).

As already explained, FIG. 2 shows a logical ATM structure with two partially associative ATM memories according to a further known arrangement. This ATM structure is constructed analogously to FIG. 1, but with the difference that two ATM memories are addressed here, the access results of which are associatively subjected to a "hit" comparison. In normal use, only one ATM memory can have a "hit". Accordingly, an output multiplexer must be controlled so that "FRAME" is passed on correctly to form the physical address.

A new ATM memory value is entered according to the LRU mechanism already explained.

As already explained, FIG. 3 shows an arrangement according to the invention for an associative memory application for compressing the ATM memory width. The value of STB in STAR is reduced by an associative memory to an approx. 3, 4, 5 bit wide "code". This can e.g. B. can be obtained

• - from the physical address of the associative memory
• - from a cell value of the associative memory
• - from STAR , generated by the firmware instead of STB stored in STAR , or similarly transferred.

Fig. 4, a block structure of the present invention shows, as already explained, the ATM. The ATM block address can e.g. B. are formed from the least significant bits of STB or supplied from an associative memory. The source of this information is not essential for the inventive idea. Rather, it is essential to the invention that the ATM memory is divided into blocks. This increases the effectiveness and efficiency of the ATM unit.

Fig., As already explained, shows 5, an overall diagram of the ATM according to the invention proposed structure. In this structure, the ATM address consists of two parts, namely

• - the local block address, which in turn consists of SXL and PX (both of VADR)
• - the block address , which here consists of CXH .

In addition to the "FRAME" part and the operating part, the ATM cells also contain ATM - SXH and ATM - CXH . Each time the ATM memory is accessed, it must be verified by comparing ATM - SXH the current virtual address in VADR and accordingly by comparing ATM - CXH with CXH whether the ATM value is related to the virtual address in VADR .

The associative memory is accessed with STB . Each cell contains CXH and CXL (which can also be derived from the physical associative memory address ) as well as an LRU value and a valid image.

Finally, as already explained, FIG. 6 shows a table for various ATM memory arrangements, as are to be carried out according to the invention.

Claims (2)

1. Arrangement for converting virtual addresses into physical addresses in a data processing system by means of an address translation memory, the address translation memory

• a segment table address register,
• - a register for the virtual addresses,
• a working memory subdivision register which divides the working memory into a user and a system part,
• a comparator assigned to this,
• - a memory address register and
• - a control logic

contains, and wherein an ATM memory is provided, which is indirectly connected to the control logic via a comparator unit, characterized in that
that between the segment table address register (STAR) and the ATM memory (ATM - MEM) a circuit arrangement - consisting of an associative memory ( ASS) with associated control (ASS - ST) with a downstream multiplexer (MUX) - inserted, which multiplexer (MUX) has two signal inputs, a signal output and a signal input, the control input from the comparator (K) , which is assigned to the register for the virtual addresses (VADR) , a signal (VADR SYP) can be fed, which makes a statement about it whether a considered address is a system address or a user address, in the case in which the considered address is a system address, the second signal input of the multiplexer (MUX) , at which a fixedly predetermined signal is connected, is switched through to the signal output thereof,
that the signal output of the multiplexer (MUX) is divided into two parts, namely in a first part with a first group of bit lines (CXH) and in a second part with a second group of bit lines (CXL) , the first part being the data input of the ATM memory (ATM - MEM) and a first comparator (K 1 within the comparator unit (KE) and the second part (CXL) together with a part of an output of the register for the virtual address (VADR) the address input of the ATM memory ( ATM - MEM) is fed,
and that when an entry in the segment table address register (STAR) is recognized as new, the memory area associated with the associative coding in the control logic (STL) is identified as undefined.