DE3631371A1 - Three-dimensional semiconductor memory cell and method of fabricating said memory cell - Google Patents

Abstract

The first electrode 2 of a memory capacitor of a semiconductor memory cell comprises an elevation which projects above the remaining region of the semiconductor memory cell. The memory dielectric 11 and the second electrode 12 of the memory capacitor also extend additionally over at least one lateral surface of the elevation. <IMAGE>

Description

The invention relates to a semiconductor memory cell a semiconductor substrate for storing electrical La dung consisting of a selection transistor and a Storage capacitor with two electrodes and one in between local storage dielectric and a method to manufacture this memory cell.

Such semiconductor memory cells are used, for example, in dynamic memory chips (DRAMs) to store data. The selection transistor is generally connected to a bit line via a first connection (source) and to the first electrode of the storage capacitor via a second connection (drain). The so-called. Gate electrode of the selection transistor is connected to a word line and the second electrode of the storage capacitor to a supply voltage line ( V _cc ).

For the trouble-free operation of a memory chip the storage capacitors have certain minimum capacities feature. But since the storable charge is proportional to Capacitor area is, all efforts come across the integra increase degree of efficiency, to geometric limits.

The arrangement according to DE-OS 35 21 891 tries this limit to break through by taking the effective capacitor area in extends the third dimension. By etching several, hyper fine grooves in the semiconductor substrate and a subsequent Coating the groove surface with the dielectric and second electrode manages the minimum capacitor area to accommodate on a smaller capacitor footprint.  

The hyperfine grooves are then etched to a photo technology step, in which on a photoresist layer hyperfine interference fringes through a holography processes are generated. Apart from the additional necessary The holographic step is in this process, as in similar proposals, the cylindrical recesses or V-shaped trenches suggest removing the etch residue insufficiently released from the wells. Do not remove them possible residues penetrate or contaminate the storage dielectric and thereby disrupt the voltage breakdown strength of the storage capacitor.

The object of the inventions is to form a memory cell gangs mentioned with reduced space requirements of Storage capacitor to create without the susceptibility to interference speed of the semiconductor memory cell to increase.

To achieve this object, the invention provides a Semiconductor memory cell according to the preamble of the patent Proceed 1, the first electrode of the storage probe sators in the form of an increase over the remaining area of the Form semiconductor memory cell and the memory board trikum and the second electrode also via at least one Extend the side surface of the elevation.

Depending on the design of the increase, this can be done the storage capacity with unchanged capacitor bottom increase the area by a multiple without hyperfine structure would have to be generated or harmful etching residues in the Wells remained.

In an inventive manner, the increase can, for example plan directly from a plan using structure etching processes Semiconductor substrate are generated. The first electrode then consists in this case of the semiconductor substrate self.  

Particularly advantageous electrical properties result itself when the first electrode faces the semiconductor sub strat is doped.

Such a structure is achieved, for example, by the Apply an epitaxial layer of opposite lei device type on the semiconductor substrate and a subsequent Etch off all areas outside the capacitor base area except for the original semiconductor substrate.

Based on the drawing is a preferred Her in the following Positioning method for an embodiment of a half described conductor memory cell according to the invention. It shows:

Fig. 1 in broken factors and schematic representation of a section through a semiconductor substrate having fiction, modern increases in the area of Speicherkondensa,

Fig. 2 in the illustration of FIG. 1, a development of the arrangement after the manufacture of a selection transistor and

Fig. 3 in the same representation in a further development of the arrangement according to FIG. 2, a functional semiconductor memory cell after the application of the storage dielectric and the second electrode.

To produce a semiconductor memory cell with a structure according to the invention, an epitaxial layer 3 of p-conductivity type is first applied over the entire surface of an n-doped semiconductor substrate 1 , for example according to FIG. 1, and then outside the capacitor base area by known etching techniques to the substrate surface worn away. In this way, first, p-doped electrodes 2 arise in the area of the base areas of the storage capacitors. Following the etching step, an insulation layer 4 is installed between the memory cells, for example using the so-called LOCOS method.

In a subsequent manufacturing step, the selection transistor is constructed in accordance with FIG. 2. For this purpose, a polysilicon gate 5 is produced on a gate oxide 6 . Both layers are applied over the entire surface of the semiconductor arrangement according to FIG. 1 and structured according to known manufacturing steps in the desired manner. This gate fabrication is followed by an ion implantation in which the connection zones 7 and 8 (source and drain) of the selection transistor in the semiconductor substrate 1 are redoped. Since this implantation step also takes place over the entire area, p-doped zones 9 are formed at the edge of the memory cell, but are of no importance for the function of the memory cell.

Fig. 3 shows, finally, the function finished semiconductor memory cell having a metal bit line 10, a storage dielectric 11 and a second electrode 12 which in this example as well as the gate 5 of polysilicon.

Compared to a common storage capacitor, which as effective capacitor area only the capacitor base area has available, the memory generated here capacitor five times the area and therefore five times the area Capacity.

Claims (5)

1. Semiconductor memory cell on a semiconductor substrate ( 1 ) for storing electrical charges, consisting of an optional transistor and a storage capacitor with a first ( 2 ) and a second electrode ( 12 ) and an intermediate storage dielectric ( 11 ), characterized in that the first electrode ( 2 ) of the storage capacitor in the form of an elevation projects beyond the remaining area of the semiconductor memory cell and the storage dielectric ( 11 ) and the second electrode ( 12 ) also extend over at least one side surface of the elevation. 2. A semiconductor memory cell according to claim 1, characterized in that the semiconductor substrate ( 1 ) and the first electrode ( 2 ) are constructed from semiconductors of opposite conductivity types. 3. Semiconductor memory cell according to claim 1 and 2, characterized in that the increase to increase the surface area additional structure doors. 4. Semiconductor memory cell according to one of the preceding claims, characterized in that the second electrode ( 12 ) consists of a poly-silicon layer. 5. A method for producing a semiconductor memory cell according to claim 2, characterized in that an epitaxial layer ( 3 ) of the second conductivity type is applied over the entire surface of the semiconductor substrate ( 1 ) of a first conductivity type in a first manufacturing step, and this epitaxial layer ( 3 ) except for the semiconductor substrate ( 1 ) is removed again outside the capacitor base area and that in a further manufacturing step the increase with the storage dielectric ( 11 ) and the second electrode ( 12 ) is covered.