DE3629680A1 - Heterostructure field-effect transistor - Google Patents

Heterostructure field-effect transistor

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Publication number
DE3629680A1
DE3629680A1 DE19863629680 DE3629680A DE3629680A1 DE 3629680 A1 DE3629680 A1 DE 3629680A1 DE 19863629680 DE19863629680 DE 19863629680 DE 3629680 A DE3629680 A DE 3629680A DE 3629680 A1 DE3629680 A1 DE 3629680A1
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Prior art keywords
effect transistor
layer
field effect
transistor according
inp
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DE19863629680
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German (de)
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DE3629680C2 (en
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Heinrich Dr Ing Daembkes
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United Monolithic Semiconductors GmbH
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Licentia Patent Verwaltungs GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a heterostructure field-effect transistor composed of semiconductor materials having low band gap. An uppermost p-doped semiconductor layer has been grown on to improve the blocking properties of the gate electrode. The gate electrode is deposited on the p-doped semiconductor layer. Source and drain terminals make contact with an ion-implanted or ion-diffused n-type region produced after epitaxially growing the semiconductor layers.

Description

Die Erfindung betrifft einen Heterostruktur-Feldeffekt­ transistor nach dem Oberbegriff des Patentanspruchs 1.The invention relates to a heterostructure field effect Transistor according to the preamble of claim 1.

Feldeffekttransistoren gemäß der Erfindung sind für Halb­ leitermaterialien mit geringem Bandabstand geeignet, auf denen Schottky-Kontakte nur schlecht oder garnicht her­ stellbar sind. Insbesondere in der Millimeterwellentechnik, für schnelle Schalter in integrierten Schaltungen oder für optoelektronische Bauelemente sind diese Heterostruktur- Feldeffekttransistoren geeignet.Field effect transistors according to the invention are for half suitable conductor materials with a small band gap which Schottky contacts are poor or not at all are adjustable. Especially in millimeter wave technology, for fast switches in integrated circuits or for optoelectronic components are these heterostructures Suitable field effect transistors.

Bei den bisherigen Heterostruktur-Feldeffekttransistoren werden für die Halbleiterschicht 2 (Fig. 1) Halbleiterma­ terialien mit großem Bandabstand verwendet, um ein ausrei­ chendes Sperrverhalten der Steuerelektrode zu erreichen. Eine weitere Möglichkeit, die Sperreigenschaften der Steuerelektrode zu verbessern, erzielt man durch das Ein­ fügen einer Isolatorschicht zwischen Steuerelektrode und Halbleiterschicht 2. Diese Lösungen haben jedoch den Nach­ teil, daß sie zeitlich instabil und stark temperaturab­ hängig sind.In the previous heterostructure field-effect transistors, semiconductor materials with a large band gap are used for the semiconductor layer 2 ( FIG. 1) in order to achieve a sufficient blocking behavior of the control electrode. Another way of improving the barrier properties of the control electrode is achieved by inserting an insulator layer between the control electrode and the semiconductor layer 2 . However, these solutions have the after part that they are temporally unstable and strongly temperature dependent.

Der Erfindung liegt daher die Aufgabe zugrunde, einen Heterostruktur-Feldeffekttransistor aus Halbleitermate­ rialien mit geringem Bandabstand anzugeben, die eine gute Ladungsträgerbeweglichkeit aufweisen, bei dem insbesondere als Steuerelektrode ein stabiler Metall-Halbleiterkontakt verwendet wird, der ein zuverlässiges Sperrverhalten zeigt.The invention is therefore based on the object Heterostructure field effect transistor made of semiconductor mate materials with a small band gap, which is a good one Have charge carrier mobility, in particular as a control electrode, a stable metal-semiconductor contact is used, which shows a reliable locking behavior.

Diese Aufgabe wird gelöst durch die im kennzeichnenden Teil des Patentanspruchs 1 angegebenen Merkmale.This problem is solved by the in the characteristic Part of claim 1 specified features.

Vorteilhafte Ausgestaltungen und/oder Weiterbildungen sind den Unteransprüchen entnehmbar.Advantageous refinements and / or further developments are the dependent claims.

Die Erfindung hat den Vorteil, daß Heterostruktur-Feld­ effekttransistoren technologisch günstig aus Halbleiter­ materialien hergestellt werden können, auf denen sonst keine Schottky-Elektrode als Steuerkontakt verwendet wer­ den kann, da deren Sperrverhalten ungenügend ist.The invention has the advantage that the heterostructure field Effect transistors technologically favorable from semiconductors materials can be produced on which otherwise no Schottky electrode used as a control contact can, because their locking behavior is insufficient.

Die Erfindung beruht darauf, daß der Heterostruktur-Feld­ effekttransistor einen zusätzlichen p-n-Übergang besitzt, der durch unterschiedliche Leitfähigkeitstypen in den obersten zwei Halbleiterschichten 1, 2 erzeugt wird und die Sperreigenschaften der Steuerelektrode verbessert.The invention is based on the fact that the heterostructure field effect transistor has an additional pn junction, which is generated by different conductivity types in the top two semiconductor layers 1, 2 and improves the barrier properties of the control electrode.

Die Erfindung wird im folgenden anhand eines Ausführungs­ beispiels näher erläutert unter Bezugnahme auf schemati­ sche Zeichnungen.The invention is based on an embodiment exemplified with reference to schemati drawings.

Fig. 1 zeigt einen Querschnitt durch einen Heterostruk­ tur-Feldeffekttransistor zur Erläuterung der Halbleiterschichtenfolge. Fig. 1 shows a cross section through a heterostructure field effect transistor to explain the semiconductor layer sequence.

Fig. 2 zeigt den Heterostruktur-Feldeffekttransistor mit einer für selbstjustierende Verfahren geeig­ neten Steuerelektrode. Fig. 2 shows the heterostructure field effect transistor with a suitable for self-adjusting control electrode.

Gemäß Fig. 1 ist auf einem halbisolierenden Substrat 5, das z. B. aus InP besteht, eine undotierte Pufferschicht 4 aufgebracht. Die Pufferschicht bewirkt, daß Kristallde­ fekte, und Verunreinigungen im wesentlichen an der Grenz­ schicht Substrat-Pufferschicht lokalisiert sind und möglicherweise eine vorherbestimmbare mechanische Span­ nungsverteilung entsteht für die nachfolgend aufgebrachten Halbleiterschichten. Die Pufferschicht 4 ist beispielsweise als homogene InP-Schicht oder als InP/InGaAs-Übergitter ausgebildet und besitzt eine Schichtdicke von ungefähr 2 µm. Auf diese Pufferschicht 4 wird eine Heterostruktur- Schichtenfolge aufgewachsen. Die Halbleiterschicht 3 be­ steht z. B. aus einer schwach dotierten In0.53Ga0.47As- Schicht mit einer positiven oder negativen Ladungsträger­ konzentration von weniger als 1016 cm-3 und einer Schicht­ dicke von 15-3000 nm.According to Fig. 1, on a semi-insulating substrate 5, z. B. consists of InP, an undoped buffer layer 4 applied. The buffer layer causes crystal defects and impurities to be located essentially at the interface layer between the substrate and the buffer layer, and possibly a predeterminable mechanical stress distribution arises for the subsequently applied semiconductor layers. The buffer layer 4 is designed, for example, as a homogeneous InP layer or as an InP / InGaAs superlattice and has a layer thickness of approximately 2 μm. A heterostructure layer sequence is grown on this buffer layer 4 . The semiconductor layer 3 be z. B. from a weakly doped In 0.53 Ga 0.47 As layer with a positive or negative charge carrier concentration of less than 10 16 cm -3 and a layer thickness of 15-3000 nm.

Auf die Halbleiterschicht 3 ist eine Halbleiterschichten­ folge aus einer undotierten InP-Schicht 2 a mit einer Schichtdicke von ungefähr 10 nm, einer n-dotierten InP- Schicht 2 mit einer Schichtdicke von 10-50 nm und einer p-dotierten InP-Schicht 1 mit einer Schichtdicke von 10-500 nm aufgewachsen. Die Halbleiterschicht 2 besitzt eine Dotierkonzentration von 1017 - 5 · 1018 negativen Ladungs­ trägern pro cm3. Dotiermaterialien sind beispielsweise Si, S, Se oder Sn. Die Halbleiterschicht 1 ist z. B. mit Be, Mg oder Zn dotiert und hat eine positive Ladungsträgerkonzen­ tration von ungefähr 1016 - 1019 cm-3.On top of the semiconductor layer 3 is a semiconductor layer consisting of an undoped InP layer 2 a with a layer thickness of approximately 10 nm, an n-doped InP layer 2 with a layer thickness of 10-50 nm and a p-doped InP layer 1 grown to a layer thickness of 10-500 nm. The semiconductor layer 2 has a doping concentration of 10 17 - 5 · 10 18 negative charge carriers per cm 3 . Doping materials are, for example, Si, S, Se or Sn. The semiconductor layer 1 is, for. B. doped with Be, Mg or Zn and has a positive charge carrier concentration of approximately 10 16 - 10 19 cm -3 .

Die obersten zwei Halbleiterschichten 1, 2 bilden einen p-n-Übergang, der zur zusätzlichen Steuerung der Ladungs­ träger dient.The top two semiconductor layers 1, 2 form a pn junction, which serves for additional control of the charge carrier.

An der Heterogrenzfläche der Halbleiterschichten 2, 3 entsteht ein zweidimensionales Elektronengas. Dabei werden die Elektronen im wesentlichen innerhalb der Halbleiter­ schicht 3 geführt.A two-dimensional electron gas is formed on the hetero-interface of the semiconductor layers 2, 3 . The electrons are guided essentially within the semiconductor layer 3 .

Nach dem Aufwachsen der Halbleiterschichten werden durch Ionenimplantation oder Diffusion n-leitende Gebiete 9, 9 a erzeugt. Die n-leitenden Gebiete 9, 9 a verlaufen senkrecht zu den Halbleiterschichten 1 bis 3 und sind mit sperr­ freien ohmschen Kontakten verbunden. Die Kontakte bilden den Source- und Drain-Anschluß 6, 8 und bestehen z. B. aus einer Au/Ge-Legierung. Die Steuerelektrode 7, der sog. Gate-Anschluß, ist ein sperrender oder sperrfreier metalli­ scher Kontakt, der auf der p-dotierten Halbleiterschicht angebracht ist.After the growth of the semiconductor layers, n-type regions 9, 9 a are produced by ion implantation or diffusion. The n-type regions 9, 9 a run perpendicular to the semiconductor layers 1 to 3 and are connected to non-blocking ohmic contacts. The contacts form the source and drain connection 6, 8 and consist, for. B. from an Au / Ge alloy. The control electrode 7 , the so-called. Gate connection, is a blocking or non-blocking metallic contact, which is attached to the p-doped semiconductor layer.

Die Sperreigenschaften der Steuerelektrode werden durch die p-dotierte Halbleiterschicht verbessert, da die Halb­ leiterschichten 1, 2 einen p-n-Übergang bilden, an dessen Grenzfläche eine Raumladungszone oder Sperrschicht entsteht.The barrier properties of the control electrode are improved by the p-doped semiconductor layer, since the semiconductor layers 1, 2 form a pn junction, at the interface of which a space charge zone or barrier layer is formed.

Die Erfindung ist nicht auf das beschriebene Ausführungs­ beispiel beschränkt, sondern sinngemäß auf weitere anwend­ bar. Beispielsweise kann anstatt der Halbleiterschichten 2 a, 2 ein Übergitter aus InP/InGaAs oder ähnlichen Halblei­ termaterialien aufgewachsen werden.The invention is not limited to the described embodiment example, but analogously applicable to other bar. For example, instead of the semiconductor layers 2 a , 2, a superlattice made of InP / InGaAs or similar semiconductor materials can be grown.

Weiterhin ist es möglich, durch selbstjustierende Verfah­ ren den Abstand zwischen der Steuerelektrode 7 und dem Source- bzw. Drain-Anschluß 6, 8 so zu verringern, daß parasitäre Widerstände und Kapazitäten reduziert werden können. Dabei wird beispielsweise die Steuerelektrode T-förmig ausgebildet, so daß die Ränder a, b den Abstand zwischen Steuerelektrode 7′ und n-leitendem Gebiet 9 fest­ legen (Fig. 2).Furthermore, it is possible to reduce the distance between the control electrode 7 and the source or drain connection 6, 8 by self-adjusting methods so that parasitic resistances and capacitances can be reduced. For example, the control electrode is T-shaped, so that the edges a, b define the distance between the control electrode 7 ' and the n-type region 9 ( Fig. 2).

Heterostruktur-Feldeffekttransistoren gemäß der Erfindung lassen sich beispielsweise mit Hilfe der Molekularstrahl- Epitaxie und/oder der chemischen Gasphasen-Epitaxie aus metallorganischen Verbindungen herstellen.Heterostructure field effect transistors according to the invention can, for example, be Epitaxy and / or chemical vapor phase epitaxy Establish organometallic compounds.

Claims (10)

1. Feldeffekttransistor bestehend aus einem halbisolieren­ den Halbleitersubstrat auf dem eine Heterostruktur-Halb­ leiterschichtenfolge aufgewachsen ist und mindestens einer Steuerelektrode, dadurch gekennzeichnet,
  • - daß die Steuerelektrode (7) auf einer p-dotierten Halbleiterschicht aufgebracht ist, und
  • - daß Source- und Drain-Anschluß (6, 8) mit senkrecht zu den Halbleiterschichten (1, 2, 3) verlaufenden n-lei­ tenden Gebieten (9, 9 a) verbunden sind.
1. Field-effect transistor consisting of a semi-insulate the semiconductor substrate on which a heterostructure semiconductor layer sequence has been grown and at least one control electrode, characterized in that
  • - That the control electrode ( 7 ) is applied to a p-doped semiconductor layer, and
  • - That the source and drain connection ( 6, 8 ) with perpendicular to the semiconductor layers ( 1, 2, 3 ) extending n-lei tend areas ( 9, 9 a) are connected.
2. Feldeffekttransistor nach Anspruch 1, dadurch gekenn­ zeichnet, daß auf dem halbisolierenden Substrat (5) eine undotierte Pufferschicht (4) aufgebracht ist.2. Field effect transistor according to claim 1, characterized in that an undoped buffer layer ( 4 ) is applied to the semi-insulating substrate ( 5 ). 3. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß auf die Puffer­ schicht (4) eine Heterostruktur aus einer gering n- oder p-dotierten Halbleiterschicht (3), einer undotierten Halb­ leiterschicht (2 a), einer n-dotierten Halbleiterschicht (2) und einer p-dotierten Halbleiterschicht (1) epitaktisch aufgewachsen ist.3. Field effect transistor according to one of the preceding claims, characterized in that on the buffer layer ( 4 ) a heterostructure of a lightly n- or p-doped semiconductor layer ( 3 ), an undoped semiconductor layer ( 2 a) , an n-doped semiconductor layer ( 2 ) and a p-doped semiconductor layer ( 1 ) has grown epitaxially. 4. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Pufferschicht (4) als Übergitter ausgebildet ist.4. Field effect transistor according to one of the preceding claims, characterized in that the buffer layer ( 4 ) is designed as a superlattice. 5. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Halbleiter­ schichten (2 a, 2) als Übergitter ausgebildet sind.5. Field effect transistor according to one of the preceding claims, characterized in that the semiconductor layers ( 2 a , 2 ) are designed as superlattices. 6. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß das halbisolierende Subtrat (5) aus InP besteht.6. Field effect transistor according to one of the preceding claims, characterized in that the semi-insulating substrate ( 5 ) consists of InP. 7. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Heterostruktur aus einer gering n- oder p-dotierten InGaAs-Schicht (3), einer undotierten InP-Schicht (2 a), einer n-dotierten InP-Schicht (2) und einer p-dotierten InP-Schicht (1) aufgebaut ist.7. Field effect transistor according to one of the preceding claims, characterized in that the heterostructure consists of a slightly n- or p-doped InGaAs layer ( 3 ), an undoped InP layer ( 2 a) , an n-doped InP layer ( 2 ) and a p-doped InP layer ( 1 ). 8. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Pufferschicht (4) aus einer undotierten homogenen InP-Schicht besteht.8. Field effect transistor according to one of the preceding claims, characterized in that the buffer layer ( 4 ) consists of an undoped homogeneous InP layer. 9. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Puffer­ schicht (4) aus einem InP/InGaAs-Übergitter aufgebaut ist. 9. Field effect transistor according to one of the preceding claims, characterized in that the buffer layer ( 4 ) is constructed from an InP / InGaAs superlattice. 10. Feldeffekttransistor nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Halbleiter­ schichten (2 a, 2) als InP/InGaAs-Übergitter ausgebildet sind.10. Field effect transistor according to one of the preceding claims, characterized in that the semiconductor layers ( 2 a , 2 ) are designed as InP / InGaAs superlattices.
DE19863629680 1986-09-01 1986-09-01 Heterostructure field effect transistor Expired - Lifetime DE3629680C2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562551A2 (en) * 1992-03-23 1993-09-29 Sumitomo Electric Industries, Limited Heterojunction field effect transistor
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE MTT-S Int.Microw.Symp.Techn.Dig., pp 434-436, 1984 *
IEEE MTT-S Int.Microw.Symp.Techn.Dig., pp 543-546, 1985 *
IEEE Proc., Vol. 133, No. 1, Febr. 1986, pp 18-24 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562551A2 (en) * 1992-03-23 1993-09-29 Sumitomo Electric Industries, Limited Heterojunction field effect transistor
EP0562551A3 (en) * 1992-03-23 1993-12-01 Sumitomo Electric Industries Heterojunction field effect transistor
US5446296A (en) * 1992-03-23 1995-08-29 Sumitomo Electric Industries, Ltd. Semiconductor device
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same

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