DE3621469A1 - Method for localising defective gate elements in a gate matrix group - Google Patents

Abstract

A multiplicity of gate elements (gate arrays) which are arranged like a matrix are connected by means of their line outputs and by means of their column outputs to an oscillator circuit, whose first output is connected to all the column inputs and whose second output is connected to all the row inputs. In the event of defective gate elements, said elements are localised in that, during the detection of a defective gate element row, the gate element rows orthogonal thereto are selected successively via their address and via a signal data input. The gate element row located in front of and behind a defective gate element row is determined by oscillator loops. The individual gate elements consist of a plurality of gates and make it possible to change a signal flow from a line into a column and vice versa. This makes possible signal flow diversion which simplifies fault localisation and its representation in the course of a display. <IMAGE>

Description

The invention relates to a method for localization defective gate elements of a gate matrix group, whose gate elements are oriented in rows and columns and are addressable and a device for Execution of the procedure.

For gate matrix groups, also called gate arrays there is the problem of defective transistors of a gate element of such a gate array locate. This is all the more difficult, ever complicated the individual gate elements are.

To control process errors, e.g. specific Metallization of the gate array on the individual Wafer applied.

To determine the failure rate of such gate arrays e.g. several thousand due to emitter-collector short-circuits Emitter connected in parallel and then the leakage current measured. The measured leakage current is in its  Size is a measure of error checking. However, at Determination and determination of a specific leakage current as a total current value not on a single defective one Gate element can be inferred. If e.g. at 100 emitters each have a leakage current of 0.5 µA would be such an evenly distributed one Leakage current is harmless. However, if the leakage current increases on a transistor or at most on some Transistors distributed, e.g. due to a leakage current of 50 µA a chip failure.

The invention is therefore based on the object Process for locating defective gate Elements of a gate matrix group and gate array a device for performing the method create a clear statement of a defective gate element or a gate of the gate Element allowed.

The object is achieved in that with the help of a ring oscillator matrix circuit in the train the address signals the gate rows and gate columns be switched into an oscillator loop. Then, when the oscillator loop is closed and thus the Oscillator works effectively, it is guaranteed that the relevant gate element or those in series Gates of the relevant gate element are error-free. With the help of the address signals and with the help of the lines and oscillator loop formation performed in columns defective gate elements can be easily removed localize, by determining the respective Intersection of faulty columns and rows.  

Then when each gate element has a signal flow Change of direction from a row to a column and Conversely allowed, each gate line and each Gate column of the gate elements addressed simultaneously. In addition, the relevant row and column will be in the Ring oscillator loop of the ring oscillator matrix circuit looped in, with data signals in the defective gate Row or gate column can be entered. To this Way you get the advantage that a Ring oscillator loop at least one gate line partially as well as a gate column at least partially has, the two parts of the gate line and Gate column each make a serial contribution for that Form oscillator loop.

In an advantageous manner, the Oscillator loops line by line and simultaneously or subsequently formed column by column corresponding addressing signals. If you find one faulty gate row or column becomes the Addressing the relevant gate line or gate Column together with the associated data feed maintain. In addition, the gate columns or gate lines from one line or Column direction addressed and subsequently from the opposite gate row or gate Column direction the gate columns or gate rows addressed and fed with data. It follows from this the advantage that while maintaining addressing and Data feed e.g. a defective gate line Oscillator loop from the intact part of the gate Line and the subsequent part of those gate Column is formed on the defective gate element  next comes. This first test or inspection process takes place in the line direction, seen from a first Direction. Below is the opposite Direction tested, and in such a way that now the individual columns are addressed in succession and be fed with data. The last gate column in front of the broken gate element forms with their first Part of a vertical oscillator loop part while due to the line addressing maintained broken gate line the remaining part of the concerned gate line the serial connector for forms the oscillator loop. You get one redirected oscillator loop.

This test process is in a display device represented in a matrix, so it is easy to see at which point the defective gate element located.

The task is also carried out by a device for Implementation of the procedure solved. This device contains a ring oscillator circuit, which with all row data inputs and column Data inputs of the gate elements is connected. The Oscillator circuit is on the input side to the individual Row and column outputs connected. Through the Ring oscillator circuit form the gate lines and Gate columns individually or collectively Oscillator loop.

For measuring the circuit speed of Semiconductor circuits are e.g. Ring oscillators used. From the determined number of flawless  working oscillators, which have more than 1000 cells could have the expected yield of an integrated circuit to be measured will. However, such a circuit Speed determination procedure not for Localization of defective gate elements of a gate Arrays.

The invention is advantageous with With the help of the ring oscillator circuit a ring oscillator Matrix formed, which the individual ring oscillators the ring oscillator circuit in the manner mentioned connects the gate elements. With the help of Addressing signals, it is possible that each row and each Column swings individually. With a data flow redirection enabling or permitting gate elements in such a way that the rows are addressed first, that the columns are then addressed, that defective rows of gates from one direction with data be fed that in addition by appropriate Addressing the data flow in the relevant gate Columns will be redirected until you get into the column before defective gate element arrives. Following it the gate columns from the opposite direction sequentially addressed and supplied with data for as long as until the column is reached that comes from the opposite direction to the defective gate element comes closest. This way you get one simple error encirclement. Can also be done with help this procedure, determine whether three NAND Gates formed gate elements the input gate or one of the two deflection gates is defective or not.  

The interruption of the oscillator loop and thus the Switching off the relevant oscillator are on reliable display feature for a defective gate element. Emitter-collector shorts and Determine metallization short circuits in the same way. The ring oscillator frequencies allow back calculations on the transistor capacities in the unloaded state and the wiring capacities in the loaded state.

Further advantages can be found in the subclaims.

The invention is described below with reference to an exemplary embodiment shown in FIGS. 1 to 3. Show it

Fig. 1 shows a schematic view of a gang elements matrix with an oscillator circuit,

Fig. 2 is a gate element and

Fig. 3 shows a schematic representation of the error encirclement of a defective gate element.

According to Fig. 1 comprises a gate-matrix circuit 4 rows R 1, R 2, R 3 and R 4 as well as four columns S 1, S 2, S 3 and S 4 on. The individual gate elements are 1, 2, 3, 4; 5, 6, 7, 8; 9, 10, 11, 12 and 13, 14, 15, 16 . All gate elements 1 to 16 are of identical design. Row control lines of the rows R 1 to R 4 are denoted by St _{R 1} , St _{R 2} , St _{R 3} and St _{R 4} . Column control lines are designated St _{S 1} , St _{S 2,} St _{S 3} and St _{S 4} . These control lines St _{R 1} to St _{R 4} and St _{S 1} to St _{S 4} are also referred to as address lines. The individual output lines of the rows R 1 to R 4 of the gate elements 1 to 16 open into a ring oscillator circuit 17 . The same applies to the output lines of columns S 1 to S 4 . The ring oscillator circuit 17 contains a distributor circuit 18 which is controlled by a control stage 19 .

Output stages of the ring oscillator circuit are designated 20 and 21. These output stages invert the incoming signals. The output stage 20 is connected to all the inputs of the rows R 1 to R 4 , while the output stage 21 is connected to all the column inputs of the columns S 1 to S 4 . The distribution circuit 18 can be used to redirect the row outputs R 1 to R 4 to the column inputs. The same applies to the column output lines.

Referring to FIG. 2, a gate element 1 consists of three NAND gates 22, 23 and 24. The first NAND gate 22 is connected on the input side to the column S 1 and to the row R 1 . On the output side, this NAND gate 22 is connected to a first input of each of the second and third NAND gates 23 and 24 . The second input of the second NAND gate 23 is connected to the address control line St _{R 1} , while the second input of the third NAND gate 24 is connected to the address line St _{S 1} . For example, if the column input S 1 receives "1" potential while the row input R 1 has "0" potential, the "1" potential is transferred to the first two inputs of the second and third NAND gates 23 and 24 . If the row or column address line St _{R 1} or St _{S 1 has} "1" potential, the "1" signal of column S 1 is transmitted either to the row output or to the column output. If both address lines St _R1 and St _{S1 have} response potential "1", then the "1" potential is distributed over the row and column output.

Referring to FIG. 3, the gate element is of the series R 2 and column 2 S defective. The addressing of the R 2 row shows an interruption of the oscillator circuit due to the interrupted oscillator loop. When addressing column S 1 , the data flow from row R 2 is diverted into column S 1 , so that this loop contributes to the oscillation of the oscillator circuit. Subsequently, with the addressing of the row R 2 maintained, column addressing is carried out from the right by applying the potential “1” starting with the column S 4 . For columns 4 and 3 , two oscillator loops are obtained, namely the pure column loop S 3 and a composite oscillator loop made up of a section of column S 3 and a remainder of the row R 2 . With a corresponding matrix-like display of this oscillator loop formation, the error is easily encircled.

If the gate 22 in a gate element is defective, the row and column oscillators do not oscillate (in the example R 2 and S 2 ). If the gate 23 or 24 is defective, the series oscillator does not oscillate; however, all column oscillators. The defective gate element must now be found with the help of the redirection of the signal path.

Assuming that the second gate 23 of the gate element of FIG. 3 is defective, this can be determined simply by moving the test method from column S 3 to column S 2, the column oscillator loop is closed while the deflection of the Data flow from the column S 2 in the row R 2 does not come about.

If there are several defective gate elements, this is done accordingly method.

Claims (9)

1. A method for localizing defective gate elements of a semiconductor gate matrix group, the gate elements of which are oriented and addressable in rows and columns, characterized in that the gate rows and gate columns are used with the aid of a ring oscillator matrix circuit in the course of the address signals are switched in an oscillator loop. 2. The method of claim 1, wherein each gate element a signal flow direction change from a gate Allowed row in a gate column and vice versa, characterized in that each Gate row and each gate column of each Gate elements is addressable at the same time, and that the relevant gate row and gate column into the ring oscillator loop of the ring oscillator Matrix circuit is looped in such that after applying a row or column signal Oscillator loop from the gate line into the gate Column or vice versa.   3. The method according to claim 2, characterized in that initially the oscillator loops line by line and simultaneously or subsequently column by appropriate Addressing are formed, and that at Finding a faulty gate line or Gate column the addressing of the concerned Gate row or column along with the associated data feed is held and additionally the gate columns or gate rows addressed from one row or column direction and subsequently from the opposite line or column direction the gate columns or gate Rows are addressed and fed with data. 4. The method according to claim 3, characterized in that the additional gate column or gate row Addressing from one direction or another successively. 5. The method according to any one of the preceding claims, characterized in that the Data for the gate rows and gate columns each entered via a common data line will. 6. Device for performing the method according to Claim 1, with rows and columns in matrix form arranged addressable gate elements, characterized in that all Row data inputs and column data inputs of the Gate elements with a ring oscillator circuit  are connected on the input side to the individual Row and column outputs of the gate elements are connected, and that through the Ring oscillator circuit the gate rows and gate Split an oscillator loop individually or together form. 7. The device according to claim 6, characterized in that the Row data inputs and column data inputs of the Gate elements via a common connection the ring oscillator circuit are connected. 8. The device according to claim 6 or 7, characterized in that the Ring oscillator circuit optionally by means of a external or internal multiplexing Distribution circuit on the data line inputs or Switchable data column inputs of the gate elements is. 9. Gate matrix circuit for performing the Method according to claim 1 or 2, characterized in that each Gate element consists of three NAND gates, from which the one a row data input and column Has data input and on the output side with one Input of the second and third NAND gates connected is, the second of which is via the second input with the row address connector and the third over the other second input with the column Address port is connected.