DE3613593A1 - FIXED BODY IMAGE SENSOR - Google Patents

Description

PATENT LAWYERS dr.-ino. praw * vuesthofp

WUESTHOFF - ν. PECHMANN - BEHRENS -COLl Z ^{rR PI: IL} · ^{? RE0A} ™ "™ °"

DIPL.-LftG.GcxHARD PULSE (l9f2-I «7l)

EUROPEAN PATENTATTORNEYS _,., ""

D1FL.-CHEM. DR. E. BARBER OF FECHMANN

3613 5 93 ^DR - ^{ING DIETER} « ^{hear $}

DIPL.-ING. DIPL.-WIRTSCH.-ING. XUFERT GOETZ DIPL.-PHYS- DR. AXEL VON HELLFELD

OLYMPUS OPTICAL COMPANY LIMITED _{D. 800Q MUNICH 90}

LA-60 3 50 SCHWEIGERSTRASSE 2

phone: (089) 66 zo $ 1 telegram! protectpatent Telex: 524070 fax: (089) 663936 (in)

Solid-state image sensor

The invention relates to a solid-state image sensor with a number of picture elements, each of which has at least one lateral have static induction transistor in which a source-drain current is parallel to the main surface of a semiconductor substrate flows.

A solid-state image sensor with lateral static induction transistors (which are abbreviated to LSIT in the following) is in U.S. Patent Application No. 715,641 filed on Mar 25, 1985. With this solid-state image sensor a number of LSITs are arranged in a matrix and these are successively selected using a drain / gate selection process, a source / gate selection process and a source / drain selection process. Among these three selection procedures the source / gate selection process was found to be very favorable if the areas of the picture elements are designed as small as possible should be.

Fig. 1 shows such a solid-state image sensor. The sensor has LSIT 1-11, 1-12, ... 1-mn, which are arranged in a matrix Form picture elements and are selected one after the other by means of a source / gate selection method. An output signal of a selected picture element is read out by means of a circuit with a common source. The gate connections of the LSIT are arranged in individual lines in the X direction and attached to the

- / 13 -

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Row lines 2-1, 2-2, ... 2-m each connected. The source connections of the LSIT arranged in the Y direction are arranged in individual columns and are each connected to column lines 3-1, 3-2, ... 3-n. The column lines 3-1, 3-2, ... 3-n are connected on one side to the video line 6 via column selection transistors 4-1, 4-2, ... 4-n and on the other side via Anti-selection transistors 5-1, 5-2, ... 5-n connected to the ground potential. The video line 6 is connected to the video voltage supply V _nn by means of a load resistor 8. All of the drains of the LSIT 1-11 to 1-mn are connected in common to the video line 6 so that the video bias voltage ν is applied to the drain electrodes of the LSIT 1-11 to 1-mn. The row lines 2-1, 2-2, ... 2-m are applied to the output terminals of a vertical scanning circuit 9 which generates _{signals S G1} # $ _Γ · »... Φ _β. The gate terminals of the column selection transistors 4-1, 4-2, ... 4-n and the anti-selection transistors 5-1, 5-2, ... 5-n are connected to the outputs of the horizontal scanning circuit 10 , which generates signals <Eg., ^ co '* * · ^ s directly or via an inverter.

The operation of the solid-state image sensor shown in FIG. 2 will now be explained with reference to the waveforms shown in FIGS. 2A to 2F. As shown in Figs. 2A to 2C, each of the signals 3 » _G1 » * g2 '**' ^eus applied to the row lines becomes a readout gate voltage V with a small amplitude and a reset voltage V with an amplitude equal to is greater than the voltage V, formed. During a line scanning period t "the signal assumes the lower voltage value V and during a blanking period t_ the signal assumes the higher voltage V. As shown in FIGS. 2D to 2F, the horizontal scanning signals ^ä _s i »i _s2 / ... which are applied to the gate terminals of the column selection transistors 4-1, 4-2, ..., a lower level at which the column selection transistors 4-1, 4-2, ... block and the anti-selection

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transistors 5-1, 5-2, ... conduct, as well as a higher level at which the column selection transistors 4-1, 4-2, ... conduct, however, the anti-selection transistors 5-1, 5-2, ... block.

If the signal 3> _G1 »which is applied to the first row line 2-1 assumes the read-out level V, _G , the LSIT 1-11, 1-12, ... 1-ln connected to the row line 2-1 become selected. When the column select transistors 4-1, 4-2, ... 4-n in succession by means of the provided from the horizontal scanning circuit 10 signals <B _S1 * S2 '*** ®Sn ^durcn 9 ^»escnaltet so be on the video line 6 successively read out from the LSIT 1-11, 1-12, ... 1-ln video signals. These LSIT are reset at the same time when the fltq. assumes the higher value V--.

Increases then the signal δ__ the lower level V__, so associated with the second row line 2-2 lsit 1-21, 1-22, ... 2n-l are selected and successively by means of the horizontal scanning signals _gl ä »* c2 ''''^ s read out. Then all LSIT 1-21, 1-22, ... l-2n are reset simultaneously when the signal * _G2 assumes the higher level ^Tr _R. In the manner described above, the LSIT are read out one by one to derive a video signal for one image field.

In the particulate image sensor described above, a constant reverse voltage V is always applied to the semiconductor substrate in which the LSIT are integrally formed, and a video bias voltage V is applied to the LSIT of the selected line which are not read out. The substrate / drain-source arrangement therefore forms a PIN diode to which the voltage ^V _R ^{+ V} _{DD is} applied. This results in the serious problem that when reading out an LSIT belonging to the line, in addition to the video signals read out from the affected LSIT, currents which flow through the PIN diodes formed by the remaining LSIT in the same row are simultaneously on the video line 6 can be read out. the

Currents flowing through the PIN diodes represent a noise signal for the video signal, which is why the signal-to-noise ratio on the video line is significantly degraded. It should be noted that the diode current is proportional to the number of LSIT arranged in the row increases. In addition, the column lines 3-1, 3-2, ... 3-n take a potential difference of the size V__ in the time between the selection period and the non-selection period, so that the charge and discharge time constants of the individual lines become large and the response speed of the solid-state image sensor deteriorates.

Since a dark current is superimposed on the video signal in the solid-state image sensor described above, the signal / Noise ratio of the video signal further reduced. In order to exclude the influence of the dark current it is necessary to have a to provide external signal processing circuitry for subtracting the dark current from the read video signal. There but the dark current varies from picture element to picture element and is also different from substrate to substrate, the Signal processing circuitry complicated and expensive.

The invention is based on the object of providing a solid-state image sensor which has a high packing density for the LSIT and from which a video signal can be read out, which at high response speed a good signal / Has noise ratio.

The solution to this problem according to the invention is characterized in its refinements in the claims.

The solid-state image sensor according to the invention thus has the following components:

a semiconductor substrate having a main surface;

a number of lateral static induction transistors forming picture elements and in matrix form in said one Semiconductor substrate are arranged, each of the lateral static induction transistors source and drain regions has, which are formed in said main surface of the substrate in such a way that a source-drain current is parallel to the main surface of the substrate flows, and

- A scanning device for the successive selection of said lateral static induction transistors by means of a Source / gate selection method and for reading out a video signal from a lateral static induction transistor by means of a source follower circuit.

In a preferred embodiment of the solid-state image sensor according to the invention the gate terminals of LSITs arranged in a row are connected to a row line, which in turn connected to a vertical scanning circuit, the drains of all LSITs are common to a video bias source and the source terminals of the LSIT arranged in a column are selective via individual column selection transistors connectable to a load resistor, the column selection transistors by a horizontal scanning circuit operate.

In another preferred exemplary embodiment of a solid-state image sensor according to the invention, there is also at least one LSIT shielded from light provided to generate a dark current and a differential output signal between a Video signal and the dark current is generated in that every time an LSIT is read out in the matrix as well the LSIT shielded from light is read out.

Exemplary embodiments of the invention are explained in more detail below with reference to the drawing. It shows:

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Fig. 1 is a circuit diagram of the solid-state image sensor described above;

Figs. 2A to 2F are pulse shapes for explaining the operation of the solid-state image sensor shown in Fig. 1;

3 is a circuit diagram of a solid-state image sensor according to the invention;

Figs. 4A to 4F are pulse shapes for explaining the operation of the solid-state image sensor shown in Fig. 3;

Fig. 5 is a circuit diagram of a further embodiment
a solid-state image sensor according to the invention;

Figs. 6A to 6H are pulse shapes for explaining the operation of the solid-state image sensor shown in Fig. 5;

Fig. 7 is a circuit diagram of a further embodiment
a solid-state image sensor according to the invention;

Fig. 8 is a circuit diagram of another embodiment

a solid-state image sensor according to the invention; and

9A to 9F are pulse shapes for explaining the operation of the solid-state image sensor shown in FIG.

Fig. 3 shows the circuit diagram of a solid-state image sensor
a number of LSIT 11-11, 11-12, ... 11-mn, which are arranged in a matrix in a semiconductor substrate. Each of the LSIT forms a picture element and has source and drain regions
which are formed in a main surface of the substrate in such a way that a source-drain current flows parallel to the main surface of the semiconductor substrate. With such a lateral
static induction transistor are the drain connections of all LSIT 11-11, 11-12, ... 11-mn together to a video preload

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voltage source with the voltage V__ (> 0) connected. The gate connections of the LSIT arranged in the individual rows are connected to row lines 12-1, 12-2, ... 12-m. The source connections of the LSIT arranged in the individual columns are connected to column lines 13-1, 13-2, ... 13-n. The column lines 13-1, 13-2, ... 13-n are connected to a video line 16 via column selection transistors 14-1, 14-2, ... 14-n and to a line 17 via so-called anti-selection transistors 15 -1, 15-2, ... 15-n connected. The line 17 is connected to the ground potential via a voltage source V (> 0). The video line 16 is connected to the ground potential via a load resistor 18 and a connection point between the video line and the load resistor is connected to the output connection 19, from which the video signal is derived. The row lines 12-1, 12-2, ... 12-n are connected to a vertical scanning circuit 20 to receive signals ÄL ·., <5 _G2 f ... 5-. The gate terminals of the column selection transistors 14-1, 14-2, ... 14-n are directly connected to the outputs of a horizontal scanning circuit 21 to transmit signals _S i ä »®οο '* * * * s ^{to em} P ^ ^an 9 ^en »while the gate connections of the anti-selection transistors 15-1, 15-2, ... 15-n are connected to the outputs of the horizontal scanning circuit 21 via inverters in order to generate inverses of the signals a _e1 , Φ _ο ~ , ... S _e too

si ο ζ fan

receive. As stated at the outset, the LSIT are formed integrally in the semiconductor substrate, to which a negative voltage V _gUB KO) is applied.

4A to 4F show signal pulse shapes for explaining the operation of the solid-state image sensor according to FIG. 3. Signals ffi_ ,,

$ _G2 / ... are applied to the row lines 12-1 or 12-2 ... and take the gate voltage V with a small amplitude during a row scanning period t "and a voltage ν_ _β

π (BR

with a larger amplitude during a blanking period t_ on. Applied to the gate terminals of the column selection transistors 14-1, 14-2, ... 14-n applied signals _sl * f ^φ '2' *** ^ha ^ ^{en a} low level, which the column selection transistors 14 * -1,

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14-2, ... 14-n blocks while the anti-selection transistors 15-1, 15-2, ... 15-n conduct, and a high level which turns on the column selection transistors while the anti-selection transistors lock. It should be noted that the signals shown in FIGS. 4A to 4F are used when the voltage V applied to line 17 is zero, ie line 17 is connected to ground potential. If V> 0, the reset voltage V of the signals $ ",, ^s q2 '" * * * G must be changed ^{in a} positive direction.

_{If the signal fl & G1} supplied by the vertical scanning circuit 20 is increased to the read-out level V, the LSIT 11-11, 11-12, ... 11-ln connected to the first row line 12-1 are selected. If the column selection transistors 14-1, 14-2, ... 14-n in succession by means of the signals <B _S1 '* _S 2' * ·· <E_ turned on, the signals being provided from the horizontal scanning circuit 21, so these LSIT are read out one after the other and video signals are derived via the video line 16 at the output connection 19. The LSIT 11-11, 11-12, ... 11-ln are then reset at the same time when the signal <δ-, _{Ί assumes} the reset _{voltage V_ o} . Then the signature

Cj X (DK

nal d> _G2 the read-out _{voltage V G} an and the LSIT 11-21, 11-22, ... ll-2n, which belong to the second line 12-2, are selected and successively according to the signals δ., Sg ₂ * · ·· Φ_ read out. Then all these LSIT 11-21, 11-22, ... ll-2n are reset at the same time. The same operation is carried out to read out all of the LSIT one by one and to obtain a video signal for an entire frame at the output terminal 19.

In order to keep the source connections of unselected LSIT at a stable potential in this exemplary embodiment, the anti-selection transistors 15-1, 15-2, ... 15-n are provided. In a modified embodiment, however, the anti-selection transistors are dispensable. In such a case, too, it is possible to place photo-charge carriers in the gate areas of the

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Save LSIT. In addition, the read-out voltage V of the gate signal can be identical to the voltage that occurs during a photo charge carrier storage period is applied.

Since the LSIT which form the picture elements are selected according to the invention by means of a source / gate selection method it is no longer necessary to provide an isolation area between the picture elements. Accordingly, can the dimensions of the picture elements can be reduced considerably and a large number of picture elements with a very high Integrate density. Furthermore, since the influence of stray drain capacitances can be reduced and the capacitance of the column lines can also be decreased, it is possible to perform high-speed readout. There, moreover the video signal is read out by means of a source follower circuit, it is possible to record a video signal with a large signal / To get noise ratio. Furthermore, the potential fluctuations of the column lines between the selection period and decrease the non-selection period, which is why reading can be carried out at a very high speed.

Fig. 5 shows the circuit diagram of a further embodiment of a solid-state image sensor according to the invention. With this one Embodiment are those components which correspond to those of the embodiment according to FIG. 3, with the same Provided with reference numerals. In this regard, reference may be made to the description above.

In this embodiment, a so-called "blind" picture element 22 is provided in the semiconductor substrate and a light shielding element Layer, such as an aluminum layer, is disposed over the dummy picture element. The dummy picture element 22 i ^ st formed by an LSIT, its drain connected to the video bias source V_ is connected and whose source terminal is connected to a line 23, which on one side

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with the dark current readout line 26 via a selection transistor 24 and on the other side with a line 17 via an anti-selection transistor 25 is connected. The dark current readout line 26 is also by means of a load resistor 27 connected to the earth potential. The load resistor 27 has the same resistance value as the load resistor 18, which is with the video line 16 is connected. A gate connection of the dummy LSIT 22 is by means of a line 28 with an additional Output of the vertical scanning circuit 20 connected. The vertical scanning circuit 20 generates a logical sum signal δ- ^

of the signals Φ _β . , ä> _G2 »· · · ^a » which are applied to row lines 12-1, 12-2, ... and 12-m, respectively.

The gate connections of the selection transistors 24 and the anti-selection transistors 25 are applied to an additional output of the horizontal scanning circuit 21 directly or via an inverter. The horizontal scanning circuit 21 generates a logical sum signal <S _S _ of the signals Sgi »®s2 '*** ^ S' which are applied to the gate connections of the column selection transistors 14-1, 14-2, ... or 14- n can be created. A connection point of the video line 16 and the load resistor 18 and a connection point of the dark current readout line 26 and the load resistor 27 are applied to the positive and negative inputs of the differential amplifier 29, respectively, so that a difference between the video signal read from the selected LSIT is and a dark current read out from the dummy LSIT 22 appears at the output.

The pulse shapes shown in FIGS. 6A to 6H explain the operation of the solid-state image sensor shown in FIG. the Signals ä> ",, δ ~~, $" · ,, which are shown in FIGS. 6A to 6C

CaI Ca i UJ

correspond to the signals shown in Figs. 4A to 4C and the signals $ _s -. / ^ c? ' ^{δ ς3 'we} ^ ^{n cne} i are shown in FIGS · 6D to 6F, correspond to those shown in Figs. 4D to 4F. _{The signal a> r} _ shown in Fig. 6G is the logical sum of the signals Φ - ,,, <ß ~.>, ... δ_ and is connected to the gate terminal of the

CaI Ca ^ Kr ^

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Blind LSIT 22 applied via line 28. _{The signal <δ_ Λ} shown in Fig. 6H is the logical sum of the signals Φ_ _Ί ,

4 _e ,,, ... 4 _e , which are sent to the individual column selection transistor

ren 14-1, 14-2, ... or 14-n can be created. If the signal a> _ _{n assumes} the high level, the selection transistor 24 becomes conductive, while the anti-selection transistor 25 blocks.

If the signal flL, .. is changed to the read value V, the LSIT 11-11, 11-12, ... 11-ln connected to the first row line 12-1 are selected. At the same time, the blind LSIT 22 is activated _{by means of the signal Φ βΟ.} When the horizontal scanning circuit 21 generates the signals a _g ., * Co '*** ^ s one after the other, the column selection transistors 14-1, 14-2, ... 14-n are switched on one after the other and the LSIT 11-11, 11-12, ... 11-ln are read out one after the other. Each time one of the LSIT 11-11, 11-12, ... 11-ln is read, the blind LSIT 22 is read out _{repeatedly using the Φ ο _ signal.} In this way

Ov /

video signals read out from the LSIT 11-11, 11-12, ... 11-ln are derived one after the other on the video line 16 and input to a non-inverting input of the differential amplifier 29. At the same time, the dark current is discharged on line 26 and input to the inverting input of differential amplifier 29. Accordingly, a video signal appears at the output, from which the dark current has been subtracted. After reading out the first line, the LSIT 11-11, 11-12, ... 11-ln and the dummy LSIT 22 are reset at the same time by means of the reset voltage _{V_ ö.} Then the LSIT 11-21, 11-22,.. Output terminal 19 appears with the influence of the dark current removed. In the manner described above, all LSIT 11-11, 11-12, ... 11-mn are read out one after the other and the video signal of one image field appears at the output terminal 19, the influences of the dark current being removed from the video signal.

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In this embodiment, a single dummy picture element shielded from light is formed in the semiconductor material, in which the picture elements are also integrally formed. Since the differential amplifier 29 is also integral on the same Is formed semiconductor die, it is not necessary to use an external signal processing circuit to remove the to provide for influences caused by the dark current.

7 shows a further exemplary embodiment of a solid-state image sensor according to the invention. In this embodiment, a column is provided with dummy picture elements which are covered by a light-shielding layer 32. The dummy picture element row has dummy LSIT 31-1, 31-2, ... 31-m, the drain connections of which are commonly connected to the video voltage source V_. The gate terminals of the dummy lsit 12-m connected to the individual row lines 12-1, 12-2, ..., so that the signals * _G1 "* g2 '*** ^ ^ Gm ^{nutrition ten} · ^D ^ ^e source terminals of the dummy LSIT are jointly connected on one side to the line 23, which is connected to the line 26 via the selection transistor 24, and on the other side via the anti-selection transistor 25 to the line 17. Im Otherwise, the structure of the solid-state image sensor shown in FIG. 7 corresponds to the exemplary embodiment according to FIG. 5.

If the signal a> _G1 assumes the read-out level V, the LSIT 11-11, 11-12, ... 11-ln and the dummy LSIT 31-1, which belongs to the first row line 12-1, are selected and the selected LSIT are read out one after the other by means of the signals Sg-i » ^s s2 '... ffi _c . At the same time, the blind LSIT 31-1 is synchronized with the readout by means of the logical sum signal " _Q

the LSIT 11-11, 11-12, 11-ln read out repeatedly. on

in this way the dark current is subtracted from the output signal read out from the LSIT 11-11, 11-12, ... 11-ln and a video signal freed from the dark current appears at the output terminal 19 of the differential amplifier 29. After completion of the When the first line is read out, the LSIT 11-11, 11-12, 11-ln

60 35Π

and the blind LSIT 31-1 reset at the same time. In the manner described above, the lines are read out one after the other, in order to obtain the video signal of an entire image field, the dark current being subtracted from the video signal read out.

In this embodiment, a plurality of dummy picture elements are provided for each line and are synchronized with the Reading of the associated LSIT. read out of the individual row lines. Accordingly, the carrier storage period the charge carrier storage period for the dummy picture elements are made the same for each picture element, which is why the influence of the dark current can be removed very precisely from the video signal, so that a very high signal-to-noise ratio results.

In the embodiment shown in Fig. 7, the row of dummy picture elements is on the right-hand side of the picture element matrix arranged. However, it is also possible to accommodate this row at a different position on the semiconductor substrate.

8 shows the circuit diagram of a further exemplary embodiment of a solid-state image sensor according to the invention. With this one In the exemplary embodiment, no dummy picture element is provided for the dark current correction and the dark current is provided for one picture element is obtained by reading out that picture element which, with respect to the picture element concerned, in the same column is arranged one row before.

The lsit 41-11, 41-12, ... 41-mn constituting the picture elements are arranged in a matrix, and the drain terminals of the lsit are commonly connected to a video bias voltage V_ _D (> 0). The gate connections of the LSIT arranged in the individual rows are connected to the individual row lines 42-1, 42-2, ..., 42-m. The source connectors. of the LSIT arranged in the individual columns are alternately connected to the column lines 43-1, 44-1; 43-2, 44-2; ... 43-n, 44-n ver

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bound. The column lines 43-1, 44-1; ... 43-n are on one side with a first video line 47 via column selection transistors 45-1, 45-2, ... or 45-n and on the other hand via anti-selection transistors 46-1, 46-2, ... 46-n connected to a line 48. The line 48 is still connected to the voltage source V (> 0) connected. The column lines 44-1, 44-2, ... 44-n are on one side with a second video line 51 via column selection transistors 49-1, 49-2, ... or 49-n and on the other side via anti-selection transistors 50-1, 50-2, ... or 50-n connected to one line.

The first and second video lines 47 and 51 are connected to ground potential by means of load resistors 52 and 53, respectively. the two resistors having the same resistance value. The connection points between the video lines 47, 51 and the load resistors 52, 53 are connected to the positive and negative inputs of a differential amplifier 54. An output signal of the differential amplifier 54 is forwarded to an output terminal 58 via an absolute circuit 55. The row lines 42-1, 42-2, ... 42-m are connected to outputs of a vertical scanning circuit 56 in order to receive signals <B ",, fl>" o, ... äL, to receive. The gate connections of the (ii Cn: t »m

Column select transistors 45-1, 49-1; 45-2, 49-2; ... 45-n, 49-n are connected in common to outputs of a horizontal scanning circuit 57 in order to receive signals 3> _s -, * _s2 »··· and δ_, respectively. The gate terminals of anti-selection transistors 46-1, 50-1; 46-2, 50-2; ... 46-n, 50-n are connected to outputs of a horizontal scanning circuit 57 through inverters so that they receive inverted signals.

9A to 9F show pulse shapes for explaining the operation of the solid-state image sensor shown in FIG. Referring to Figures 9A through 9C, the signals & _c -ir ^ q? ' ** '* Gm Honoring successive sampling periods t "two lines the readout

voltage V__. During two consecutive blanking

6 0 3Γ50

Periods t they take on the value of the reset voltage ν _.

The signals δ _ο1 , (6 _CO , ... fc _o “ , which in FIGS. 9D to 9F geoi ο ζ on

correspond to those of the previously described embodiments.

If the signals $ _G1 and <5 _G2 simultaneously assume the value of the read-out voltage V during a period T, the LSIT 41-11, 41-12, ... 41-ln and 41-21, 41-22, .. . 41-2n selected. If the column selection transistors 45-1, 49-1; 45-2, 49-2; ... 45-n, 49-n are switched through one after the other by means of the signals Φ., & ~ Ο ' ... a> _, which are provided by the horizontal scanning circuit 57, so successively on the first video line 47 are video signals which are read out from the LSIT 41-21, 41-22, ... 41-2n, which belong to the second row line 42-2, and at the same time video signals, which are from the LSIT 41-11, belonging to the first row line 42-1, are read out. 41-12, ... 41-ln, derived one after the other on the second video line 51 in synchronism with the video signals read out from the LSIT 41-21, 41-22, ... 41-2n. It should be emphasized that the LSIT 41-11, '41 -12, ... 41-ln belonging to the first line 42-1 are just by means of the reset voltage V, "

of the signal <ß _{G1 are} reset. The video signals read out from these LSIT 41-11, 41-12, ... 41-ln are therefore equivalent to dark currents. If the difference between the video signals on the first and second video lines 47 and 51 is accordingly formed by means of the differential amplifier 54, a video signal is obtained which is freed from the influences of the dark current.

Then the LSIT belonging to the first and second lines 42-1 and 42-2 are reset at the same time when the signals S ^ ₁ and Φ ^ _ assume the reset voltage V synchronously with one another. Then the signals ffi and _{00 take on} the value of the read-out ^{voltage V during the next line scanning period T 1} and the LSIT 41-21, 41-22, ... 41-2n and 41-31, 41-32,. .. 41-3n, which are connected to the second and third row lines 42-2 '

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or 42-3 are connected, are selected and read out one after the other. Then, video signals read out from the LSIT 41-31, 41-32, ... 41-3n are sequentially derived on the first video line 47, and at the same time video signals read out from the LSIT 41-21, 41-22, ... 41-2n are read out Signals derived one after the other on the second video line 41. A video signal freed from the dark current is obtained at the output terminal 58 by means of a differential amplifier 54 and the absolute circuit 55. Then, the LSITs 41-21, 41-22, ... 41-2n and 41-31, 41-32, ... 41-3n connected to the second and third row lines 42-2 and 42-3, respectively reset once. In this way the lsit are successively read out to the video signal to obtain an entire scanning field, said lsit lying in previously angeord- ¹ Neten lines are read in order to win a dark current which is subtracted from the video signal by means of DifferenzverstHrkers 54th

In this embodiment, since the dummy picture element for generating the dark current is not required, the structure becomes particularly easy. Furthermore, since the dark current is obtained from a picture element which is adjacent to that picture element from which the video signal is currently being read, it is possible to precisely correct the influence of the lightning current, so that a video signal with a very good signal-to-noise ratio results.

In the embodiments shown in FIGS. 5, 7 and 8, the influence of the dark current can be completely eliminated and the video signal has a very high signal / noise ratio. The video signal is therefore exactly proportional to the amount of incident light, even if the intensity of the incident light is very weak. In addition, since no external signal processing circuit is required, the solid-state image sensor is simple in structure and inexpensive to manufacture. In addition, the fluctuation of the signal /

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The noise ratio for individual semiconductor wafers can be reduced and the positive yield in the manufacture of the Solid-state image sensors are being improved.

The exemplary embodiments of the invention described above permit the following modifications, for example: The picture elements can also be formed by static induction transistors of the so-called vertical type, instead of the lateral static ones Induction transistors. Also, the conductivity type of the static induction transistor is not limited to the n-channel type, but can also provide a p-channel. In the latter embodiment, the dark current is used for correction of the video signal read out from a picture element is obtained from that picture element which is in the same column in the previous line. According to the invention, the dark current can also be obtained from a picture element, that is in the same row but in the previous column.

Claims (1)

PATENT LAWYERS r> »- ino. pr «, n <: vuesthofp WUESTHOFF-v. PECHMANN-BEHRENS-GOETZ '«> · ^» EUROPEAN PATENT ATTORNEYS- ^DI ' ^l " ^NG · °" ^HA "''"" DIFl ₁ -CHEM. DK. E. VKEIHER * VON PICHUANN 3 G 135 93 »».-INC. DIETER BEH XE NS DIPL.-ING. D1PL.-TIRTSCH.-ING. KUFERT GOET Drri.-PHYS. DK. AXEL VON HELLFELD OLYMPUS OPTICAL COMPANY LIMITED _O ^ _{QQ monks 9q} LA-60 350 SCHWEIGERSTRASSE 2 phone: (089) ££ 2051 telegram! fkotectpatent TELEX: 124070 fax: (o8>) 66) 9 3 <(«") Claims 1. solid-state image sensor, marked by - A semiconductor substrate with a main surface; - a number of lateral static induction transistors (11-11, ..., 11-mn) forming picture elements and in matrix form are arranged in the semiconductor substrate, with each lateral static induction transistor source and drain regions which are arranged in said main area of the substrate in such a way that the source-drain current flows parallel to the main surface of the substrate; and - A scanning circuit (20, 21) to successively scan the lateral static induction transistors by means of a source / gate selection process and to select a video signal from a selected lateral static induction transistor read out by means of a source follower circuit. Solid-state image sensor according to claim 1, characterized, that the following are provided as scanning devices: - A horizontal scanning circuit (21), at the outputs of which horizontal scanning signals appear; - A vertical scanning circuit (20), at the outputs of which ver vertical scanning signals appear; - A video bias _{voltage source (V_ D} ) to which the drain connections of all lateral static induction transistors are connected in common; - A multiplicity of column lines (13-1 ... 13-n), to each of which the source connections of the lateral static induction transistors (11-11 ... 11-mn) are connected, which are arranged in the relevant column; - a plurality of column select switches (14-1 ... 14-n), each connected to respective column lines and having control terminals which are connected to the outputs of the horizontal scanning circuit (21); - A video line (16) to which the column selection switches are connected; - A load resistor (18) which is connected between the video line (16) and the ground potential; - a plurality of row lines (12-1 ... 12-m), each connected to associated outputs of the vertical scanning circuit (20) and to associated gate connections of the lateral static induction transistors, which are shown in the individual lines are arranged; and - A video output connection, which is connected to the junction between the video line (16) and the load resistor (18) connected. 3. Solid-state image sensor according to claim 2, characterized in that the column selection switch (14-1 ... 14-n) consists of column selection transistors are formed whose source-drain current paths in series with the assigned column lines (13-1 ... 13-n) and whose gate connections are connected to the associated outputs of the horizontal scanning circuit (21). 4. Solid-state image sensor according to claim 3, characterized in that the column lines continue to have associated anti-selection transistors (15-1 ... 15-n) connected to a line - 3 - 60 3bn which is connected to a constant potential, and that the gate connections of the anti-selection transistors are assigned via Inverters are connected to said associated outputs of the horizontal scanning circuit (21). 5. Solid-state image sensor according to claim 4, characterized in that that the constant potential corresponds to the earth potential. 6. Solid-state image sensor according to one of the preceding claims, characterized, that the semiconductor substrate is applied to a voltage source with constant bias, the polarity of which is opposite to that of the video bias source (V_ _D ). 7. Solid-state image sensor according to one of the preceding claims, characterized, that the lateral static induction transistors are of the n-channel type. 8. solid-state image sensor,
marked by - a semiconductor substrate; - a number of static induction transistors (11-11 ... 11-lmn), which form picture elements and in the form of a matrix in the semiconductor substrate are arranged; - A scanning device (20, 21) for successively selecting the static induction transistors by means of a source / gate selection method and for reading out a video signal from selected static induction transistors by means of a Source follower circuit; - 4 - 60 350 - A device (22) for generating a dark current which corresponds to a video signal which is read out from a picture element is on which no light falls; and - Means (29) for subtracting the dark current from the Video signal to obtain a corrected video signal. 9. Solid-state image sensor according to claim 8, characterized in that the device for generating a dark current is a dummy image element (22) which is formed integrally in the semiconductor substrate. 10. Solid-state image sensor according to claim 9, characterized in that the dummy picture element (22) is a dummy static induction transistor and a light shielding layer (30) formed over the blind static induction transistor is, and that the dummy static induction transistor is read out repeatedly every time the picture elements can be read out. 11. Solid-state image sensor according to claim 10, characterized in that the static induction transistors which form the picture elements (11-11 ... 11-mn) and the blind static induction transistor (22) are each formed from lateral static induction transistors. 12. Solid-state image sensor according to claim 11, characterized in that the scanning device comprises: - A horizontal scanning circuit (21) having outputs at which horizontal scanning signals appear; - A vertical scanning circuit (20) having outputs at which vertical scanning signals appear; - 5 - 60 350 a video bias source (V _DD ) to which the drains of all lateral static induction transistors are commonly connected; a plurality of column lines (13-1 ... 13-n), to each of which the source connections of those lateral static Induction transistors (11-11 ... 11-mn) are connected, which are arranged in the relevant column; a plurality of column selection switches (14-1 ... 14-n), each connected to associated column lines and have control terminals connected to the outputs of the horizontal scanning circuit (21); a video line (16) to which the column selection switches are commonly connected; a load resistor (18) connected between the video line (16) and the ground potential; a plurality of row lines (12-1 ... 12-m) connected to associated outputs of the vertical scanning circuit (20) as well are connected to the gate terminals of lateral static induction transistors, which are in the associated Rows are arranged; and a video output connection that connects to the junction between the video line (16) and the load resistor (18) connected, where a gate terminal of the blind static induction transistor (22) of the dark current generating device with a additional output of the vertical scanning circuit (20) is connected to a logical sum signal of the vertical scanning signals to generate a drain of the dummy static induction transistor (22) with said video bias source (V__) is connected, a source terminal of the blind static induction transistor (22) with a Dark current output line (26) is connected via a selection transistor (24), the gate terminal of which is connected to an additional Output of the horizontal scanning circuit (21) is connected to a logical sum signal with respect to the horizontal To generate scanning signals, the said dark current - 6 - 60 350 Output line (26) is connected to ground potential via a load resistor (27) which has the same resistance value as the load resistor (18), which is connected to the video line (16), and wherein the subtracting device (29) has a differential amplifier, whose first input to the video line and whose second input to the Dark current line (26) is connected. 13. Solid-state image sensor according to claim 12, characterized in that that the column lines (13-1 ... 13-n) continue to have one line via associated anti-selection transistors (15-1 ... 15-n) are connected, which is connected to a constant potential that the gate terminals of the anti-selection transistors are connected to said associated outputs of the horizontal scanning circuit (21) via individual inverters, and that the source of the dummy static induction transistor (22) is connected to said line via an anti-selection transistor (25) is connected, the gate terminal of which is connected to the additional output of the horizontal scanning circuit (21) connected via an inverter. 14. Solid-state image sensor according to claim 8, characterized in that that the device for generating a dark current has a plurality of dummy picture elements (31-1 ... 31-m), which in a column are arranged, and a light-shielding layer over the dummy picture elements, wherein a dummy picture element, which belongs to a line is read out repeatedly when the picture elements belonging to the line concerned are successively read out can be read out. 15. Solid-state image sensor according to claim 14, characterized in that that each of said dummy picture elements is formed from a dummy static induction transistor. - 7 - 60 350 16. Solid-state image sensor according to claim 15, characterized in that that the static induction transistors forming the picture elements and the blind static induction transistor from the lateral Type are. 17. Solid-state image sensor according to claim 16, characterized in that that the scanning devices have the following: - A horizontal scanning circuit (21) having outputs for generating horizontal scanning signals; - A vertical scanning circuit (20) having outputs for generating vertical scanning signals; - a video bias source (V - .. J, to which the drains of all lateral static induction transistors (11-11 ... 11-mn) are connected together; - A multiplicity of column lines (13-1 ... 13-n), on each of which the source connections of the lateral static induction transistors are connected, which are arranged in the relevant column; - A multiplicity of column selection switches (14-1 ... 14-n), each connected to assigned column lines and whose control connections are connected to the outputs of the horizontal scanning circuit (21); - A video line (16) to which the column selection switches are connected in common; - A load resistor (18) which is connected between the video line (16) and the ground potential; - A multiplicity of row lines (12-1 ... 12-m), each connected to associated outputs of the vertical scanning circuit (20) and to gate connections of lateral static induction transistors are connected, which in the assigned Rows are arranged; and - A video output connection, which is connected to a connection point between the video line (16) and the load resistor (18) connected, the gate terminals being the blind - 8 - 60 350 lateral static induction transistors (31-1 ... 31-m) are connected to associated row lines, the drain connections of the blind lateral static induction transistors are connected together to the video bias _{source (V DD} ), the source connections of the blind lateral static Induction transistors are connected to a dark current output line (26) via a selection transistor (24), the gate terminal of which is connected to an additional output of the horizontal scanning circuit (21) in order to generate a logical sum signal of the horizontal scanning signals, said dark current output line (26) is connected to the ground potential via an additional load resistor (27) which has the same resistance value as the load resistor (18) connected to the video line (16), and the subtracting device has a differential amplifier (29) whose first input is connected to the video line (16) and its second input with the Dark current line (26) is connected. 18. Solid-state image sensor according to claim 17, characterized in that that the column lines continue to be connected to a line via associated anti-selection transistors (15-1 ... 15-n) are connected to a constant potential that the gate terminals of the anti-selection transistors are associated with Outputs of the horizontal scanning circuit (21) are connected via individual inverters, and that the source connections of the blind lateral static induction transistors (31-1 ... 31-m) to said line via an anti-selection transistor (25) are connected, the gate terminal of which is connected to the aforementioned additional output of the horizontal scanning circuit (21) is connected via an inverter. 19. Solid-state image sensor according to claim 8, characterized that the devices for generating a dark current one - 9 - 60 Have circuit for selecting and reading out a static induction transistor, which is close to the static to be read out Induction transistor is arranged and which is read out immediately in front of this static induction transistor. 20. Solid-state image sensor according to claim 19, characterized in that the static induction transistor from which the dark current is to be read, belongs to the same column as the static induction transistor to be read, but one Row is arranged in front of this static induction transistor. 21. Solid-state image sensor according to claim 20, characterized in that the scanning device has the following: - A horizontal scanning circuit (57) having outputs for generating horizontal scanning signals; - a vertical scanning circuit (56) having outputs for generating vertical scanning signals; - A video bias source (V ") to which the drain connections of all static induction transistors are common are connected; - A multiplicity of row lines (42-1 ... 42-m) to which the gate connections of the row in question are arranged static induction transistors are connected; - a plurality of first column lines (43-1 ... 43-n), as well as a plurality of second column lines (44-1 ... 44-n), to which the source connections of the static induction transistors arranged in the relevant column are alternately connected; - First and second video lines (47, _Λ 51), which can be connected to the first and second column lines via first and second column selection switches (45-1 ...; or 49-1 ...); and - 10 - 60 350 - First and second load resistors (52, 53) which are connected between the earth potential and the first and second video lines, respectively the first and second column selection switches belonging to the assigned columns in succession are operated by means of the horizontal scanning signals, and wherein the subtracting device is a differential amplifier (54), the first and second inputs of which are connected to the first and second video lines, respectively. 22. Solid-state image sensor according to claim 21, characterized in that the subtracting device (54) further comprises a circuit (55), which is connected to the output of the differential amplifier (54), to an absolute value of the output signal of the differential amplifier. 23. Solid-state image sensor according to claim 22, characterized in that the static induction transistors by lateral static induction transistors are formed. 24. Solid-state image sensor according to claim 21, characterized in that each of the generated by the vertical scanning circuit (56) vertical scanning signals has a readout voltage level which lasts at least approximately as long as two successive ones Line scan periods, as well as a reset voltage level that is between the readout voltage levels of two consecutive line scan periods. 25. Solid-state image sensor according to claim 21, characterized in that that the first and second column selection switches (45-1 ...; 49-1 ...) are formed by column selection transistors, wherein the source-drain current paths of the first and second column - 11 - 60 350 Selection transistors of the individual columns with first and second column lines (43-1 ...; 44-1 ...) are connected, the belong to the relevant columns, and that the gate terminals of the first and second column selection transistors, which are to belong to the relevant columns, are connected together to assigned outputs of the horizontal scanning circuit (57), 26. Solid-state image sensor according to claim 25, characterized in that that the first and second column lines (43-1 ...; 44-1 ...) continue to have associated first and second anti-selection transistors (46-1 ...; 50-1 ...) are connected to a line, which in turn is connected to a constant potential and that the gates of the first and second anti-selection transistors connected via individual inverters to assigned outputs of the horizontal scanning circuit (57) 27. Solid-state image sensor according to claim 26, characterized in that that the earth potential is provided as a constant potential 28. Solid-state image sensor according to claim 8, characterized in that that the semiconductor substrate is connected to a constant bias voltage source, the polarity of which is opposite to that of the video voltage source (V _DD ).