DE3581556D1 - Steuerungsgeraet in einem digitalen computer. - Google Patents

Steuerungsgeraet in einem digitalen computer.

Info

Publication number
DE3581556D1
DE3581556D1 DE8585105042T DE3581556T DE3581556D1 DE 3581556 D1 DE3581556 D1 DE 3581556D1 DE 8585105042 T DE8585105042 T DE 8585105042T DE 3581556 T DE3581556 T DE 3581556T DE 3581556 D1 DE3581556 D1 DE 3581556D1
Authority
DE
Germany
Prior art keywords
control unit
digital computer
digital
computer
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585105042T
Other languages
English (en)
Inventor
Gregory C Edgington
Daniel M Mccarthy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of DE3581556D1 publication Critical patent/DE3581556D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE8585105042T 1984-04-27 1985-04-25 Steuerungsgeraet in einem digitalen computer. Expired - Fee Related DE3581556D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US60475884A 1984-04-27 1984-04-27

Publications (1)

Publication Number Publication Date
DE3581556D1 true DE3581556D1 (de) 1991-03-07

Family

ID=24420912

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585105042T Expired - Fee Related DE3581556D1 (de) 1984-04-27 1985-04-25 Steuerungsgeraet in einem digitalen computer.

Country Status (5)

Country Link
EP (1) EP0159712B1 (de)
AU (1) AU572647B2 (de)
CA (1) CA1243411A (de)
DE (1) DE3581556D1 (de)
FI (1) FI86484C (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
JP2680899B2 (ja) * 1989-08-28 1997-11-19 日本電気株式会社 情報処理装置及びその制御方法
EP0475209A3 (en) * 1990-09-14 1993-09-29 Siemens Aktiengesellschaft Arrangement for the determination of instructions modified by the cpu of a processor
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
US5684977A (en) * 1995-03-31 1997-11-04 Sun Microsystems, Inc. Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
US5655100A (en) * 1995-03-31 1997-08-05 Sun Microsystems, Inc. Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
US5826073A (en) * 1995-10-06 1998-10-20 Advanced Micro Devices, Inc. Self-modifying code handling system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156906A (en) * 1977-11-22 1979-05-29 Honeywell Information Systems Inc. Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands
FR2420168B1 (fr) * 1978-03-16 1986-09-26 Ibm Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4521851A (en) * 1982-10-13 1985-06-04 Honeywell Information Systems Inc. Central processor

Also Published As

Publication number Publication date
FI851638L (fi) 1985-10-28
EP0159712B1 (de) 1991-01-30
AU572647B2 (en) 1988-05-12
AU4173385A (en) 1985-10-31
FI86484B (fi) 1992-05-15
FI851638A0 (fi) 1985-04-25
EP0159712A3 (en) 1987-08-05
CA1243411A (en) 1988-10-18
EP0159712A2 (de) 1985-10-30
FI86484C (fi) 1992-08-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL HN INFORMATION SYSTEMS INC., BILLERICA, MASS.

8339 Ceased/non-payment of the annual fee