DE3540753A1 - Store for data processing systems - Google Patents

Abstract

To increase the speed of data processing systems, use is made of a store which, once it has intermediately stored an entire matrix line from the approximately square storage matrix in a register provided especially for this purpose on a memory chip, can output the bits, assigned to the same memory chip, of the commands of successive program steps quickly from this register while bypassing the storage matrix and independently of other accesses. The use of a plurality of such registers makes this design suitable also for the parallel operation of a plurality of processors on the same store both for fast data exchange with the processor and for early reloading to ensure a continuous data stream.

Description

Description :

Program memory for data processing system The invention relates to a fast program memory for data processing systems, especially for von-Neumann calculator.

Such a memory holds on the one hand with the commands to be executed the program for one or more processors, but also data for these. In doing so, commands are constantly read out from this memory that reflect the change any data, including from this memory, cause. In general commands in memory are executed one after the other, only sometimes this sequence is disturbed by program branches, for example.

In previous computers, every command or at most very small groups of commands an access to the memory for fetching the respective one Command carried out, at most commands already used are carried out in a quick Intermediate storage for renewed access stored or the storage in individual groups entangled, with access then generally to different groups and therefore takes place quasi-parallel and therefore faster.

A memory used for this purpose generally consists of a number of memory chips, which often correspond to the memory word length of the computer, optionally corresponds to a part or a multiple thereof. Any memory chip now contains one or more memory matrices. An access is made by the desired Row of memory is selected and then all bits in that row are brought via the column lines to the column decoder, from which this then selects one. This happens simultaneously for each bit of the memory word. All remaining column bits are discarded. If necessary, with some storage types a different column address can be specified while retaining the cell address, However, this is transferred separately to the memory (page mode) or it is fixed Starting points assumed (nibble mode), this process also blocks the whole Storage matrix. There are only so-called for special applications such as graphics systems Multiport DRAM '*, which has such a column regardless of the column address of output a few fixed starting points from what via a separate shift register it comes very close to the invention, but fast program branches are impossible because there the program flow is continued at any point. Also is an attempt at direct parallel processing on the chip for special video applications made (SLAM from Stanford University).

The disadvantage of this is that the memory is unnecessary when the commands are fetched is loaded and is therefore only available to a limited extent for access to data. Furthermore, the performance of the possibly very fast processors limited by delays in fetching commands, especially when these only perform internal, non-memory processing.

The invention is based on the task of fetching the commands as possible to make it independent of the memory.

This object is achieved according to the invention in that a memory chip assigned bits of the commands of successive program steps after one-time Intermediate storage of an entire matrix line from the approximately square memory matrix in a specially provided register on the same memory chip bypassing the memory matrix and separately from other accesses from it Register can be read out.

In order to have several processors working on such a memory let you quickly exchange processor data such as processor register contents with the memory or the data flow if the column register is exhausted by reloading early to ensure, according to a further embodiment of the invention, several matrix cell registers provided on the same chip.

The advantages that can be achieved with the invention are, in particular, that by largely eliminating intensive memory accesses only for fetching the program commands the program execution becomes independent of the memory speed and simultaneously Memory is often available for other tasks such as data changes stands.

An embodiment of the invention is described below: A slow dynamic memory with 64KBit capacity and approx. 150 is given ns access time. This is made up of a 256 by 256 bit matrix. In the Addressing is now first selected one of the 256 lines.

The memory cells now transfer their charges to the column lines at the same time, where these are converted to valid logical signal levels by the line amplifier and the information for the purpose of renewal - because of the destructive reading up to At the end of the access, they are kept in a register and then stored back again to become. One of these lines is now selected and output.

At this point the invention is now applied: Instead of like a little bit discard all other bits, these are stored in a further static register cached.

This register can now be connected to its own column decoder be. The processor now requests the next command from the following address on, the meanwhile saved in a counter and z. B. to an increased column address is applied to the column decoder assigned to this register and the associated data is output to an additional output. So he has to Processor does not wait 150 ns, but only about 40 ns and the memory will be at linear program sequence in the best case only loaded with every 256 access.

If the counter has counted to the end, a new matrix line must be requested will. For further acceleration, this can of course also be done beforehand in one other additional register. In the case of a program branch the new address is simply placed in the memory and, as above, one more whole matrix cell loaded.

Instead of the version with a counter, it is of course also used a shift register conceivable.

This memory can be used to accelerate the process of branching Of course, also with an attic for the first commands after one Branch to be linked. This type of memory is particularly good for processors be suitable with a reduced instruction set (RISC concept).

Claims (3)

Claims: 1. Memory for a data processing system, characterized in that the bits of the commands assigned to a memory chip successive program steps after one-time intermediate storage of a entire matrix row from the approximately square memory matrix in one for it specially provided register on the same memory chip quickly bypassing the memory matrix and read out from this register separately from other accesses can be. 2. Memory as above, characterized in that by providing multiple matrix line registers multiple processors can be operated at the same time or overlapping reloading is enabled. 3. Memory as above, characterized in that by providing further matrix line registers also successive data information quickly can be exchanged with the processor.