DE3511920A1 - ELECTRONIC GUIDE - Google Patents

Description

I I 920 DIPL.-ING. DIPL .- 'TIRTSCH.-ING. RUPERT COETZ TRW Inc. SCHWEIGERSTRASSE 2

IA-59 198 phone: (089) 6620 51

TELEGRAM: PROTECT PATENT

TELEX: 524070

TELEFAX: VIA (089) 2 7I 60 63 (ill) Electronic advisor

The invention relates to a data processing system which can be used as a so-called "expert system". Expert systems are known in the art of "artificial intelligence" and are also referred to as "electronic advice".

The books "Principles of Artificial Intelligence", by N. J. Nilsson, Tioga Publishing Company, Palo Alto, 1980; "Logic for Problem Solving", by R. Kowalski, North Holland, New York, 1979; "Introduction to Mathematical Logic", by E. Mendelson, Van Nostrand, New York, 1963.

A variety of approaches exist in the prior art for generating systems of inference based on certain rules and regulations are based. In general, however, these rule systems depend undesirably on the given languages or operating systems which require very specific computing systems.

Since existing systems of the type mentioned above that are based on certain rules use an embedded language, which If rules are observed and interpreted, the known systems do not always have a syntax that is comprehensive enough to allow so-called To be able to express expert rules easily. Also enough

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the quality of these systems in terms of the explanation of the drawn Conclusions are not drawn. Also, some rule-based systems do not obey traditional regulations mathematical logic, although this has already been successful for the development of what is known as artificial intelligence has been used.

Although intensive efforts have been made, there remains a need for a system in which for every given programming language the structure is separated from the expression and which is independent of the particular characteristics of a given operating system. Many rule-based systems are dependent on the LISP source codcs limited. These systems are generally unsuitable for complex applications such as the VAX / VMS system of DIGITAL EQUIPMENT CORPORATION.

The program languages FORTRAN and PASCAL are suitable for most systems. PASCAL has two main advantages over this FORTRAN regarding systems based on rules of execution, although FORTRAN can also serve these ticks. First PASCAL enables recursive procedure calls, i.e. a clear one and short procedural execution scheme for complex searches required in deductive testing techniques. Second, PASCAL promotes the dynamic runtime allocation of Link lists, a storage operation with which data field structures cannot compete in terms of simplicity, their Sizes must be determined statically in the translation time.

If an embedded language is implemented for a rules-based system, i.e. for the rule language that the recognizes the deductive verification procedures to be used, PASCAL is more suitable than FORTRAN. Recursion and linked lists are basically two programming tools, as described in the

Compiler (compilation) and interpretation techniques can be used and their availability in the program language is a major consideration in language selection.

If e.g. PASCAL is used as the implementation language and a VMS (virtual storage technology) chosen as the host for a rules-based system, it still remains the requirement, the quasi-forme: He procedural documentation of the to translate so-called expert rules into the embedded language of the skittles, which is made by the rules-based system be recognized. There is a need to develop processes to specify formal expressions based on rules and regulations regarding the instruction-dependency of the Steps taken by the expert system in procedurally solving the problem. The definitions of expressions which are used by the expert system when expressing its rules must be supported directly by the formal syntax will.

In order to be understandable, a system must establish and maintain documentation of the expert's analytical strategies (the so-called expert rules). The documentation of the expert rules is initially controlled by means of a Consultation technology developed with experts. Perceptual techniques are made explicit in procedural terms during these exercises Documented form.

The expert documentation should expressly contain certain judgments. For example, an expert can use the terms "deep", Use "middle", "high", "outside" and "unusable". parameter are usefully quantified heuristically, since the expert language is not very much in most applications is precise. The semantics of a syntax with formal rules receives and receives this heuristic information as far as possible also the judgment of the expert as he falls, e.g. "the tolerance X is not small ...".

In view of this prior art, it can be seen that there is a need for an improved expert system and related There are procedures which are independent of special processing computers and languages and which can be freely applied with different software and hardware systems.

The inventive solution to this problem is in the claims marked.

The invention thus consists in a data processing system and a method for operating such, with universal Files are implemented as so-called flat files and with conclusions based on the in the Data stored in flat files are taken by machine. The data in the flat files represent the expert knowledge and are separate from the inference device.

The flat files are multi-dimensional allocation tables which represent a certain knowledge that is required when solving a problem is used or at a paradigm. A conclusion is made when there is observed information with the flat files is processed. In the simplest case, the flat file structure is a conventional two-dimensional table of results (Conclusions) as a function of observable properties (conditions, causes). Any of these assignments is treated as a rule (regulation) and the rules codify the mapping knowledge regarding the data, with which the conclusions are carried out to address the issues Solve a problem.

The automatic inference takes place through a backward or forward chaining by means of one based on the rules Deduction. The system works with a computation which eventually makes a determination on the basis of an arbitrary one Initial state (a set of previously verified primitive statements) confirmed by applying the generation rules (P rules).

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According to one embodiment, a backward chaining is carried out to confirm a target determination in such a way that that interim determinations are derived through the applied rules up to each new interim determination by the initial state is confirmed. In this way, the determination of the target is ensured by combining individual test steps backwards until only those are known Steps remain that are known to be correct.

In the invention, the explanatory system is that for each of the steps performed in the test, a simple one Report is formed. The report corresponds to an expert's rationale for reaching the conclusion of a Test. The explanatory device therefore only tracks down the individual steps of the inference engine and reports she. The report consists of a text-oriented display, which is written at the point in time when the rule sentence is being developed. For each statement contained in a rule (regulation) there is an affirmative sentence in English and a the opposite, negative sentence also set up in English. The explanation procedure receives the index a statement, the mnemonic identifier of which appears in the printout of a rule that is used in a certain test step is used. The determination index is used to determine the affirmative or non-affirmative rate for the Recover display, depending on whether the mnemonic short form for the statement usually confirms or negates it has been.

In summary, it can be stated that with the invention an expert system, so an electronic adviser, with a Knowledge base containing data, information, expert knowledge and logical means of justification, is created which does not depend on a particular processing computer or a particular programming language. So it will be a wearable one

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Expert system provided which works with any general purpose computer is usable and which can be implemented as special computer hardware. The hardware device enables faster runtimes compared to common multi-purpose computers, uses less power and takes up less space.

The invention is explained in more detail below with reference to the drawing. Show it:

1 shows a block diagram of an expert system according to the invention;

Figure 2 is a block diagram of a flat file in accordance with the invention;

Fig. 3 is an abbreviated data record representation of a Flat file;

Fig. 4 is a block diagram of an inference device according to the invention for forward concatenation; and

Figure 5 is a block diagram of an inference device according to the invention for backward concatenation.

Fig. 1 shows a block diagram of the device according to the invention. The knowledge base memory 10 stores N-dimensional ones Data fields, which are called flat files. The memory 10 is typically a RAM (random access memory) with addressable memory cells, each address memory cell stores a flat file in the form of logical values "1" and "0". Entries into memory 10 consist of determinations (= Statements). A distinction must be made between different types of findings. The relationships between the findings are called rules (regulations). Each rule has a combination of a presupposed finding and an inferred one Finding on. For example, a Boolean combination of one or more presupposes

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Findings another Boolean combination of one or several follow-up findings are defined. Presupposed (or also to be designated as preceding) determinations, which are the result of an observation, for example by humans, are referred to as "primitive" (statements). For the purpose of illustration, presupposed statements should be on the left side of a printout, which is separated by the symbol ": =", while the subsequent statements should be on the right side of this symbol. The terms "left" and "right" have no other meaning than that only the requirements and the consequences (consequences) are separated from each other. The requirements only appear on the left side of the rule symbol (: =) and the consequences, which can also be designated as goals, appear exclusively on the right-hand side of the rule symbol (: =). One Consequences that appear on the right-hand side for one rule can occur on the left-hand side for another rule. In general, therefore, a sequence is only an intermediate result due to a "primitive" statement and one Target.

A flat file has one or more rules that are divided by common types of properties (i.e., common types of Findings), but different property values (i.e. the findings can have different logical values "1" or "0"). Because the sequences from one flat file serve as prerequisites in another flat file can, the flat files are indirectly linked by the fact that follow-up statements from different files can appear either to the right or to the left of the rule symbol (: =). The information in the flat files is thus connected to one another via follow-up determinations, but no pointer is provided which connects one flat file with another Linked flat file.

The rules stored in the memory 10 are by means of a Address or name identifies which rule ID (Rule identifier) is called. Each rule has a field to identify the type of rule, whether inclusive or exclusive, and one or more fields identifying each of the rule's determinations along with the relationship between the presupposed and the following statement.

Inclusive rules require backward chaining, but exclusive rules have both forward and forward chaining backward chaining is possible. An example of a rule can be expressed as follows:

P ₁ & P ₂ : = P ₃ .

In this rule, P. & P ~ are the requirements and P-. is the consequence. The rule states that a logical AND of the determinations P ₁ and P ₂ implies the determination P _3.

In addition to the rules, the memory 10 also stores a determination table. The determination board is an arrangement of all the determinations within the knowledge base and is in three sections divided up. The first section is a primitive memory which has address memory cells which are defined by the Names of the primitive statements or identifications (ID) are addressed. All sorts of primitive statements of the system are stored in primitive memory. Each memory cell has a field to assign the rule ID for each rule save, within which the primitive statement appears together with a field for an explanatory text, which is used whenever the statement is confirmed.

The determination table also has a sequence memory (for the conclusions) addressed by the names or identifications of the consequential statements. All possible consequential findings from the knowledge base are made

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stored in the episode memory. Each address memory cell for each sequence determination has a field for the rule identifier (Rule ID) for each rule in which the subsequent statement appears. The episode memory also has a field for explanatory texts, which is always used when the sequence is confirmed.

The determination board also has a target memory ciui, which is addressable by the names or identifications of target statements. All possible target statements the knowledge base appear in the target memory. Each memory cell for a destination determination has a field for storing the Rule identification for each rule within which the target occurs. There is also a field for an explanatory text which is used whenever the destination is confirmed.

In FIG. 1, the inference device 11 is an apparatus which collects the information from the knowledge base memory 10 used to determine whether certain goals are given for a given set of selected input primitive determinations (i.e. Input observations) is true. The initial primitive statements are checked by either forward or backward chaining to determine whether they conform to the rules of the rule board suffice. The inference engine examines the primitive statements and rules to determine whether the goals is complied with. The sequence followed by the inference device 11, by which the individual determinations as are correctly determined is recorded in the explanatory memory 13. The memory 13 is then queried in order to to reach each statement one after the other and, together with the explanatory text from the statement table, which of these A so-called "expert text" is generated, which explains one after the other how the individual goals have been confirmed as correct.

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In Fig. 1, the interface 12 is used to enter requests. If the user interface 12 is an application program, so this is resident in the host computer 14. The host computer 14 typically includes hardware 16 and 16 an operating system 15. The interface 12 typically has a so-called "terminal" (keyboard) or another Input / output device which can be used with the host computer 14. The user interface 12 is used to enter primitive determinations, with which inference engine operates to determine whether the objectives are met by the rules of the expert system will.

FIG. 2 shows a multidimensional assignment table which represents a knowledge structure of a problem-solving method or a paradigm. Such multi-dimensional assignment tables are called "flat files ^11. The flat file offers a clear, two-dimensional table representation of results (consequences, conclusions), depending on observable properties (prerequisites, initial findings). Each assignment of this type forms a rule (regulation) and each rule contains the linkage knowledge in the form of data, on the basis of which inferences are made in order to solve a particular problem.

Fig. 2 shows an example of the rule P ₁ VP ₂ VP ₃ : = P ₄ & P ₅ . This rule states that a logical OR of P., P ₃ and (-PJ implies a logical AND of P. and P _1. The prerequisite here is P-VP _? V (-P_), while the sequence P ₄ & P is ₅ .

The basic idea of the paradigm is to use observations to reduce the number of possible outcomes by only those candidate results are retained, their properties associated with those observed to match. From the original set of eligible outcomes (also called "candidates"), which one

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typically contains all possible outcomes will only selected those whose properties correspond to the present set of observations. This way becomes a new set of candidates derived from a previous set of candidates by means of new observations.

The representation by means of fold files solves two construction problems. First of all, the flat files allow one of specific Program language-independent representation of the rule base, which is used in order to use the paradigm (the problem-solving technique) solve the problem of interest. This independence from a particular language enables Postponement of the point in time at which the computer hardware and language are selected until the implementation phase. Frequently a LISP variant is used for the implementation. The use of flat files enables the Use of different software and hardware, e.g. ROSIE with INTERSLIP / 20 and PASCAL with DEC VAX3,0.

The second design problem solved by the flat files concerns the need for a data abstraction technique when displaying the rule base for the applications of the expert system. The table display of the rule base using the Flat file allows for a clear and easy understanding of the rules. Wrong approaches and inadequacies in the rule base are easily detectable once the specifics of the problem to be solved are clearly understood.

Given a flat file with rules linking observable properties to results, the main problem is when implementing in the correct selection of the correct data structure implementation technique. It is desirable to choose data structures that are relatively well suited for different languages, for example ROSIE or PASCAL.

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When using ROSIE, those in the flat file are codified Assignments are represented by assertions of the type "x is a property of the object y". When using PASCAL, the flat file is only sparsely occupied, since only a relatively small number of all possible assignments are selected. Since it would be a waste of storage capacity, see a flat file with a two-dimensional boolean Data arrangement (most values would have the value "false"), the flat file is instead filled with a pair of mapping list data fields implemented, the first listing all properties of each result (result), while the second lists all results with all properties. In both cases, the flat file is sufficiently abstract and language-independent with regard to the rule base in such a way that the advantages of each language, especially with regard to the data structure, can be used. Moreover, it is easy to ensure that the two implementations are semantic are equivalent.

The design of a standard paradigm for flat files must operate without reference to any particular language or language Enable hardware. The flat file representation is particularly useful in combination with standard paradigms.

Derivation through regular backward chaining:

The Artificial Intelligence Paradigm which is responsible for the parameter selection problem can be referred to as a regular, backward-chaining, deductive inference system will. In such a system, an invoice is a "confirmation of a destination based on the determination" Initial state "(a set of previously verified primitive statements) by applying so-called "production rules", which are called "P-rules". P-rules are so-called "If-then-relations", which regularities in one reflect certain problem areas.

Syntactic structure of the production rules:

In a backward chaining derivation system, there is a production rule by an "if-then" sign, ": =", with the left and right sides (requirement or consequence usually called) Boolean combinations of simple statements form. The simple statements are also called "atoms" in technical terminology. In the following, the "letter" every simple statement (atom) denotes. The requirement of a production rule can be any conjunction (Boolean product) of letters and the sequence can be any OR combination (Boolean "see sum") of Be letters.

The symbols for the conjunction are the AND sign and the inverted wedge, while the symbols for the OR combination (Disjunction) the vertical line and the wedge are. The symbol for the negation is the hyphen. Atoms (simple statements) are identified by mnemonic identifiers with alphanumeric characters together with underscores represented, whereby the first digit of the mnemonic representation is always alphabetical.

Confirmations through backward chaining:

Upon confirmation of a goal, the rules are applied to derive intermediate goals until each new intermediate goal is passed the initial state is confirmed (truth assignment). In this way, target establishment is secured by its confirmation via a backward chaining of test steps is won until there are only steps left whose truth is known. For example, the sentence:

1. A: = B • -
• E. G 2. -C & -D E. • ZS 3. B & F &

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4. TO: = F

5. Tl & -H: = F

6. T2 & -J: = F

of production rules (1-6) are used to confirm target "G" by applying rules 3, 1, 4 and 2, where the letters "A", "TO", "-C" and "D" represent an initial state beeing confirmed.

The representation of the P-rules in the flat file:

The P-rules (production rules) require the explicit representation of negations of atoms (simple statements) using the rule structure. Fig. 2 shows a representation of P-rules in the flat file · For each production rule of the P-rule form a flat file according to FIG. 2 is provided. This provides a method to create a flat file for draft any given production rule in P-rule form. For a PASCAL implementation of the inference system a more space-saving data structure results (corresponding to the flat file representation according to FIG. 2) from the fact that the columns of each flat file of the type shown in Figure 2 are either empty or select exactly the same rows. So if η atoms are provided, the complexity of the

Implementation of a P-rule with 4n elements in the associated Flat file reduced to 4n elements in the PASCAL data structure, which are used to represent the P rule will. FIG. 3 shows the reduction in memory space for P-rules for the flat file shown in FIG. 2 using by PASCAL.

System syntax:

A rule consists of a Boolean product of letters as well as a sequence which consists of a single letter

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stands. The system allows for a Boolean sum of letters as a result of a rule.

The system does not allow claims of simple statements which are composed of relationship predicates followed by designations (for example "Father (Mary, John) "," Cousin (Mary, x) "). Furthermore, the reverse derivation system enables not the expression of non-atomic determinations in the form of quantifying sentences for which individual variables are linked to the occurrence of set symbols, for example "each" and "some" (e.g. "(some x) Cousin (Mary, x) "which means that Mary has at least one cousin).

The production rules of the system have no relationship predicates, Designations or sizes. Instead, the atoms (simple statements) are simple sentences with none developed syntactic structure. This distinction with regard to the syntactic structure enables the transition to the mathematics of the used derivation logic. The system does not allow "first order predicate calculi" which inferences allow with quantifications and reference determinations, but the system enables so-called "sentence calculi", which contain conclusions only with simple statements, which do not have a syntactic structure above the level of Boolean operators.

Logical validity and provability within the system:

A Boolean combination of simple sentences is conventional referred to as "logically valid" if, and only if, through every assignment of truth values of the atomic Components is confirmed, i.e. the so-called truth table shows the value "true" for each associated column in the corresponding column atomic row. The logical validity is one

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semantic property, as it has to do with the value of the sentence and the assignment of truth values to its components Has.

Conventionally, on the other hand, within a given system of deductive logic, a proposition is then, and only then, called "Verifiable" means when a sequence of sentences ending with the sentence in question is made through the application of confirmation rules can be generated. This kind of checking of sentences by means of other sentences is in most formal representations of course implemented using deductive logic.

Reliability and completeness of the deduction system:

The two terms "logical validity" and "verifiability" are traditionally used to define two important properties of a formal system of deductive logic. First a system is called "logically reliable" if only logically valid sentences are confirmed in it can. A system is then called "semantically complete" if every logically valid sentence is confirmed in it can be.

The system is logically reliable, but semantically not complete. This incompleteness follows from the fact that the only derivation rule used in the backward reconstruction is a "modus ponens" is (if "A: = B" and "A" are confirmed, then "B" can be deduced), which is particularly reliable. Around To semantically complete the system, various other reliable inference rules are added, in particular the "indirect affirmation" (can be concluded with both "B" and "-B" assuming "A", then can also be based on "-A" can be deduced) as well as the so-called "Condition Confirmation" (if "B" are concluded under the assumption "A" then "A: = B" can be concluded). The main one

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The goal in implementing a reverse drainage system is but not achieving "semantic completeness" at the expense of other important properties, such as the Obtaining confirmations in the form that an expert would give.

Logical programs can achieve semantic completeness, however, the level of justification is greatly reduced. Reproduce the confirmations thus obtained only sequential chains that are expressed in a very restricted syntax.

The envisaged paradigm with backward chaining allows for a natural explanation of the individual conclusions. The explanations are obtained as simple reports of each step taken in the review will. By its nature, the report represents an "expert" opinion on how to base the conclusion would. The possibility of giving explanations is thus provided by means of a simple addition to the inference device (tracing and reports).

The explanatory device converts the steps used when confirming the last individual result into a Text ad. The text used in the display is determined by the designer when developing the rule set.

For every atom contained in a rule of a rule set (simple statement) the designer supplies a confirming one Sentence in English and a contrary sentence, also in English. The explanation procedure needs only to be executed if the index of an atom appears, whose mnemonic identifier is for a particular one Test step occurs in the expression of the rule used. The index of the atom can be used to determine the affirmative or to recover the negative sentence for the advertisement,

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depending on whether the mnemonic code for the atom has generally been confirmed or negated. This simple approach To provide the user with explanations of the results of the system is by the nature of inference using backward chaining enables.

The explanations displayed have a form such that the text for a particular letter (atom) is based on a given Height appears while the text below appears at a different height for each of the letters required for confirmation will. The first line of text provides general information about the results of the last run carried out. from Objectives that reflect results that are dependent on individual parameters are embedded more deeply in the explanations, in accordance with The way an expert would analyze the problem too.

A compiler for higher rules of the system:

Representing the production rules in the form of P-rules PASCAL data records are in a file in the system's file directory. The P-rules file is replaced by a Generates compiler which develops one or more P-rules from a higher-level rule which is stored in an ASCII file (American Standard Code for Information Interchange) are included.

The higher rules, called Η-rules, expand the content of the P-rules, but are at the same time based on them by means of more familiar ones Laws of propositional logic traceable. The relationships between P-rules and Η-rules described below enable a reduction in the risk of errors when entering rules, since this allows the number of rules per rule set to be reduced is. For example, a rule set generates 77 P-rules in PASCAL from 43 H-rules.

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Η-rules expand the content of P-rules:

Η-rules enable the specification of equivalent statements (so-called "then and only then" or "exactly then" statements) as well as canonical implications ("if, then" conditions). Of the User can express two separate P-rules of the form "A =: B" and "B =: A" with a single Η-rule of the form "A == B". A Η-rule can also be a Boolean sum of products (OR link of AND links) of letters (atoms or their negations) as a prerequisite ("if" on the left Page) instead of a single Boolean product, as indicated by the syntax of the P-rule. This allows a further narrowing of the rule set as the user can express two rules of the form "A&B: = C" and "D&E: = C" with a single rule of the form "A & BvD & E: = C". X similar the sequence (the "then" on the right) of an H-rule can be the Boole's product of sums instead of a single one Boolean sum. This enables the reduction of two such expressions, for example "A: = (BvC) & (DvE)".

The compiler evaluates some properties of the sentence logic:

The system's H-rule compiler (translator) enables a more precise form of user-definable rules and also eliminates meaningless and redundant P-rules. Nondescript P-rules are those that are true in every case, i.e. those with contradicting prerequisites (e.g .: "A&A: = B") as well as those with trivial or necessarily true consequences (e.g. "A: = Bv-B"). Such P-rules are made by the P-rule set generated by the compiler is eliminated and a corresponding message is issued.

The elimination of redundant P-rules is achieved through optimization of the file of the originally generated P-rules.

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The basic idea is that if the sequence of a given P-rule can be derived from an initial state, the precondition of which is present in the rest of the P-rules, then this rule can be eliminated, since it does not add any information of its own to the P-rule. The formal justification of this optimization lies in the so-called "deduction theorem ¹¹ of sentence logic, according to which if B can be confirmed on the basis of assumption A, then" A: = B "can also be confirmed.

Another logical feature of the system that can be exploited comes from its foundation on sentence logic. There Decision-making procedures for the logical consistency of rule sets are provided in sentence form (but not for rule sentences in complete first-order predicate form), the rule compiler checks a given set of rules for its logical consistency.

This check is an advantage of the backward chaining of the system, which becomes more important the larger the selected rule set becomes. Evidence of logical inconsistencies through
human inspection becomes increasingly difficult as the complexity of the cone theorem increases. In the case of a very large set of rules, however, consistency in particular should be guaranteed.

The compiler described is desirable for the reasons noted, but the present invention is applicable to any flat file regardless of how the P-rules are generated
are.

Generalization of the conclusion initialization of the
Systems:

The system of flat file and inference device can be implemented by means of a PAiU'Al.-St .indard-Unterstionye. Implemented in this way, the system is very diverse
Operating systems can be used.

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Though a rule compiler only boolean structures ("if-then", "and", "or", "no") as admissible rules, there are also advantages when a compiler uses syntactic Recognizes structures below the level of simple sentences, including relational and functional expressions with free variables (the formal counterparts of pronouns).

Entering a FORTRAN name list is a good example for a standard data representation. In a name list there is an identifier for each list component with the assigned values. In the simplest case, this identifier turns every name list into a binary relation (a set of ordered pairs of values). For example, the list of names can:

idl 123 id 2 456 id3 789

can be decomposed into a set of tuples satisfying a binary relation, such as "value of (X, Y)", "lower bound (X, Y) "or" Coefficient (X, Y) ", depending on the application. Higher-order relationships can also be obtained from FORTRAN name lists. An advanced inference facility uses FORTRAN name lists and corresponding representations of relations which are easy to recognize by the user in the sense that no special interfaces for each application for these data representations must be developed.

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The system uses data representations (i.e. tuples) which the Structure according to those used in database administrations. That is, database systems and on Systems based on predicate logic rules are based on the same thing Understanding of a relationship.

The development of relational expressions within the Inference facility is expanded to provide transparent access to FORTRAN name lists and relational lists for the user To give databases like INGRES. This extension eliminates the need to develop special interfaces for certain Problems.

System performance data:

The inference facility's performance results in part from the reduction in the required expiration time, in which confirmations for targets are obtained by backward chaining. The traditional method of finding a rule base uses an nth order linear scan for the next η rules to confirm a given sub-goal. These Calculation is eliminated by the fact that the rule compiler for each letter (a simple sentence or its negation) a rule list is calculated, which is used in the search for evidence which identifies the letter in question (Atom) as a result. This list of rules is injected and in the name of the atom or its identification Saved atom blackboard. This atomic table reduces a component of the evidence structure from the order (n) to the Order (1).

Another factor that determines the performance is the time in which SETATOMS are executed to produce an output state description against which the inference engine will perform its backward concatenation search for confirmation terminated by goal setting. The runtime parameters of the

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Systems and also the atomic panel arrangement allow a reduction the processing effort. The observed delays due to the transit times are so on the order (2M), the time limit for the confirmation search algorithm itself, where M is the number of simple (atomic) Is sentences that are usually used as a rule-base.

Predicate logic:

The extended, partially implemented in the software of the system Rule language has atoms that act as relationships between individual constants (names, numbers) and individual variables (Pronouns) and functions of details are expressed which serve as valid arguments. These extensions lift See rule language from a simple Boolean level Sentence logic to the level of a first-order predicate logic. Rules expressed in the unexpanded syntax are as Rules defined in sentence form, while rules expressed in extended syntax as first-order rules in predicate form are defined.

The inference facility provides inferences whose correctness is guaranteed by the predicate logic form of the rules becomes, but not by the sentence form of the rules used in the inference device via which the Inference by means of rules in sentence form procedures used In addition, the rule of standardization (finding suitable substitutes for free variables) is implemented, to handle predicate logic inference rules, e.g .:

Formal expression German

OFF: forbidden (x) Everything is forbidden.

CLOSE: forbidden (min (INTl)) The minimum INTl is

forbidden.

A disadvantage of predicate logic is that the consistency of a rule set cannot be effectively checked, since the consistency of formula sets in a logic of the first order represents an unsolvable problem (a problem,
for which no algorithm exists that gives a final answer with a finite number of steps).

Nevertheless, there is a significant practical advantage of the extended Language means that complex logical relationships and conditions can be precisely expressed. The introduction of Atoms (simple statements), which are put together as relations and functions, enable a shortening of the scope the rule-sentences. Instead of unlimited lists of rules:

: Parameter forbidden: = Bad parameter
: Parameter2forbidden: = Bad parameter2

In English:

: ParmlOutOfBounds: = BadParml
: Parm2OutOfBounds: = BadParm2

which are expressed without relational expressions and free variables can use the only rule instead:

: Parm (x) & Gr (VaKx), upper limit (x))
: = bad value (x)

be used.

The rule is to be interpreted in such a way that "everything a
Parameter is and a value greater than the determined upper
Limit has a false value (bad value) is ". Or less
cryptic, "any parameter value that is greater than its
upper limit value, is incorrect ¹¹ .

Rule syntax:

The system language of rules is based on a formal language of symbolic logic. The syntactic definition of this language can be represented by a discussion of the lexical (word) structure and then the grammatical (phraseological) Structure of printouts that are recognized by the rule compiler.

The lexical structure of the expressions:

The types of symbols used in the formation of assertions, rules and other expressions understood by the syntax of the system are the following:

(1) predicate constant.

(2) Individual constants.

(3) Individual variable.

(4) Function symbols.

(5) Marking symbols (punctuation).

(6) Logical constants.

These types of symbols are discussed in detail below. (1) Predicate constant:

Predicate constants are means of identification which are used to establish finite, m-place relationships between individual objects to express. Predicate constant identifiers are available as sequences of alphabetic and numeric characters using Underscores combined (underscores: "_"), with the condition that the chains are each marked with a Start "large" alphabetic characters. Accordingly, for example, Greater Than, Lesser Than, Equal To, Predicate Constant, while the following chains are not (for the reasons given below):

greater than - no capital letter at the beginning 2nd_Spark_Plus - no capital letter at the beginning Performance_l / 2 - illegal character "/"

(2) Individual constant:

The class of individual constants includes sequences which both conform to the rules for predicate constants as well as with sequences which reflect actual (fixed point) numbers. Individual constants can be used as names interpreted by unique individuals (objects, numbers, etc.) will. Therefore, the following sequence is a proper individual constant:

Battery ignition System_2000 3706 -123.4546,

while the following sequences are not for the reasons given:

battery - no capital letter at the beginning 2-te_Besetzung - no capital letter at the beginning -.123e4546 - no fixed point representation

(3) Individual variable:

Individual variables are a sequence of the same character sets formed like the predicate constants and the alphanumeric individual constants, but with the difference that they begin with a lowercase letter. Individual variables are as formal counterparts to the pronouns in the ordinary To interpret English (German) because they name individual individuals only within a context. To note is that typical variable chosen from the end of the alphabet

but the description is much broader. Accordingly the following sequences are proper individual variables:

χ y xl

y234 object_l plus_2

while the following are not, for the reasons given:

xl - no initial lowercase letter

2nd_object - no initial lowercase letter

x.l - illegal character "."

(4) Function symbols:

Function symbols are formed in the same way as the individual variables and differ in grammatical terms the context. Function symbols can be finite, m-digit Functions are interpreted which single out a unique individual from a sequence of individuals. Function symbols usually do not start with letters from the end of the alphabet, but such functional symbols are not wrong. That is why the sequence is

sort xml bin-width

a proper function symbol, while the following sequences are not for the reasons given:

SQUARE - no lowercase letter at the beginning.

2s_complement - no initial lowercase letter. int # min - illegal character "#".

(5) Marking symbols:

The marking symbols are used to arrange the expressions so that they can be recognized by the syntax. The marking symbols are the round brackets "(" and ")", and the square brackets "£" and "3". Expression arrangements such as functions or predicate-argument lists or Boolean combinations of sentences that begin with "(" must end with ")", while those that begin with "£"_; must end with "2".

(6) Logical constant:

The logical constants are the Boolean ¹ sentence operators, which are symbolized as follows:

SYMBOL OPERATOR LINK & conjunction (and) V Disjunction (or) - negation (no) : = condition (if then) == equivalence (then and only then)

The syntactic structure of the system expressions:

The syntax differentiates between different types of syntactic structures. These are:

(1) Individual expressions.

(2) Atomic formulas.

(3) Correctly formed formulas.

(4) P-rules.

(5) H-rules.

(1) Individual expressions:

Individual expressions are classes of expressions that can serve as arguments for functions or predicates. they are defined recursively as follows:

(a) Each individual constant is an individual expression.

(b) Each individual variable is an individual expression.

(c) If f is an n-digit function symbol and Tl, ..., Tn are individual expressions (terms), then f (Tl, ..., Tn) and f [Tl, ..., Tn] are also individual Terms (expression = term).

(d) Only expressions that comply with provisions (a), (b) or

(c) are individual terms.

(2) Atomic formulas:

Atomic formulas represent the lowest level of a complete one Phraseology within the syntax. Atomic formulas are recursively defined as follows:

If P is an m-place predicate constant and Tl, ..., Tm are individual terms, then P (Tl, ..., Tm) and PCTl, ..., Tm] are atomic formulas. Nothing else is one atomic formula.

(3) Well-formed formulas:

The highest level of phrase structure recognized by the system is the class of "well-formed formulas". The Elements

of this class are arbitrary Boolean combinations of atomic Formulas. The class is defined recursively as follows:

(a) Every atomic formula is a well-formed formula.

(b) If P and Q are well-formed formulas, then they are also -P (P&Q), (PVG), (P: = Q) and (P == Q).

(c) Only expressions which are divided by a finite number of Applications of rules (a) and (b) formed are well-formed formulas.

Furthermore, a class of well-formed formulas is distinguished, which literals are mentioned:

(d) If A is an atomic formula, then both A and -A are literals.

(4) P-rules:

P-rules are the simplest rules recognized by the system. P-rules are defined recursively as follows:

(a) Every single literal or every finite combination of literals is a LITPROD.

(b) Every single literal or every finite disjunction (or combination) of literals is a LITSUM.

(c) If P is a LITPROD and S is a LITSUM, then (P: = S) is a P-rule.

(d) Only expressions which are formed according to rules (a), (b) and (c) are P-rules.

Note that individual literals, for example "-forbidden (Int (x))" can be viewed both as a Boolean suite or as a Boolean product of literals, according to the laws "S == (SVS)" and "S = = (S&S) ⁿ . There is a one-to-one relationship between P-rules and the data structure generated by the rule compiler.

(5) H-rules:

Η-rules are the most general kind of rules established by the Syntax to be interpreted. Η-rules are defined recursively as follows:

(a) Every single LITPROD or every finite disc function of LITPRODs is a PRODSUM.

(b) Every single LITSUM or every finite combination of LITSUMs is a SUMPROD.

(c) If P is a PRODSUM and S is a SUMPROD, then are

(P: = S) and (P == S) H-rules.

(d) Only expressions formed according to rules (a), (b) and (c) are H-rules.

There is a one-many relationship between the H-rules and the P-rules, which preserve the data structure generated by the rule compiler. The reason is that H-rules are abbreviations of conjunctions of P-rules and are therefore equivalent to sets of P-rules due to the following reduction scheme :

Η-rule Equivalent P-rule set

((P&Q) V (R&S)): = T ((P&Q): = T, (R&S): = T) P: = ((QVR) & (SVT)) (P: = (QVR), P: = (SVT)) P == Q (P: = Q, Q: = P)

Formation of an H-rule set:

The rule sets are created as ASCII text files in the host computer. There are four sections in a rule set, which expressions indicate and serve to represent the expert knowledge:

(1) The NAME section.

(2) The PRADICATES section.

(3) The FUNCTIONS section.

(4) The RULE section.

An example of such a section is given below of an H-rule set for an application example presented and commented on.

(1) The NAME section:

To the non-numeric individual used in an application To number constants, the user arranges them in the initial section of the application H-rule as follows:

- NAME -

Prang
Prange2
Prange3

In the further course of the formation of the H-rule set, these specified names are used to provide arguments for the relevant To form predicates and functions.

(2) The PREDICT sections:

Following the NAME section, the user explains the predicate constants, which are used in the rule expression of expert knowledge can be used as follows:

- PREDICATES -

reasonable (x)
χ is acceptable.

prohibited (x)

χ is forbidden.

Minimum (x, y)

χ is the minimum of y.

Maximum (x, y)

y is the maximum of y.

DeltaThresh (x, y)

y is the limit for acceptable changes in x.

It should be noted that for each in the predicate section introduced Predicate constant a blind argument list (dummy argument list) given is. The blind arguments list is used two purposes. First, the length of the list is taken as the degree ("arity") of the relationship so that, e.g., "forbidden" a monadic (unary) relationship is first degree, while "minimum", "maximum" and "DeltaThresh" binary relationships second Second, the blind argument list is used to mark the relative positions in the following line of text, where the test for each substituted individual term

During the explanation in the backward confirmations is arranged.

(1) FUNCTIONAL section:

After the user has specified the PREDICATES to be used in the rule set introduced, the FUNCTIONAL sections are formed as follows:

- FUNCTIONS -

CONNECT square root (x) ufool square root of x.

min (x) PROJECT Min (x, y)
Minimum of x.

max (x) PROJECT Max (x, y)
Maximum of x.

It should be noted that in the representation of the functional symbols Ie not only is given an argument list which serves the same two purposes as the argument list in presentation of the predicate constants, but also that an attribute is specified which describes the evaluation process in more detail .

Functions that are provided with a CONNECTION attribute, are evaluated during the runtime of the confirmation by calling a PASCAL function that is assigned by the present Chain is mentioned as an argument for the CONNECTION attribute, in the present case e.g. the function called "ufool". The present

Low terminology arises from the concept of the "procedural Connection "for the verification of (sub) goals within the rules-based technology of the system.

USER FUNCTION module (input / output)

*
•

function ufool (x: real): real; beginning

ufool: = sqrt (x); end.

Functions declared with the PROJECT attribute are evaluated in such a way that that a term of a tuple appears in the table attribute In the example given above with regard to the declaration for "min" the relationship table for a previously agreed predicate constant, "min", is checked during confirmation and the function evaluates the appropriate projection of each corresponding tuple. For example, if "min (Prange1)" is used during the Confirmation evaluates as a substitution for "min (x)", then becomes the second element of the fourth tuple from the following Diagram 1 determined as the result.

Diagram 1

Rangel, 123.456
Range2, 234.567
Range3, 345,678

Range9, 456.789

The function "min (Range3)" is made up by PROJECTION 345,678 the tuple range3,345,673- evaluated in the relationship table for "Min".

(4) The RULE section:

The last section of an application rule set is the one in which the user applies the rules of the technical knowledge in the form of agreements that have been made in the previous three sections. For example:

- RULES -

: Range (Range9).
! Range (Range8).

! Range (range).
! Range (Range2).

! Range (x) & Gr diff (max χ, min χ, deltathresh (x): = normal (x).

This rule section leads to a rule which the idea that "every reach whose maximum differs from its minimum by differs more than a known limit value, is acceptable ".

Forward chaining - Fig. 4:

An expert system for forward chaining is shown in FIG. The system has a given stack memory 25 which contains the values entered via the interface 12 of FIG Receives primitive statements. The given stack memory 25 is typically a hardware stack which is a subset of all primitive statements stored in the knowledge

Base memory 10 occur. This subset of primitive statements in memory 25 represents the data of certain observations which are checked against the knowledge base should. A sorter 26 causes each primitive determination (one at a time) stored in memory 25 in its address register 27 according to the LIFO principle (LIFO principle: Last Inn-First Out = cascading). That Address register 27 addresses the primitive memory 28, which forms part of the knowledge base memory 10 of FIG. The primitive memory 28 stores a rule ID (a Address) for each rule in which the primitive determinations of register 27 occur. In the table 28, each rule ID stored in the rule ID register 28. The sorter 26 causes that each rule ID in register 29 (one at a time) addresses rule memory 30. Register 29 typically has a number of fields, one for each rule ID. Controlled by CIDS signals from the sorter 26, the rule ID in register 29 is shifted piece by piece to the output field memory cell 37, which is the rule memory 30 addressed.

The rule memory 30 is part of the knowledge base memory 10 of FIG. 1. The access to that in the rule memory 30 The field corresponding to the addressed rule takes place by means of the CCR signal, which is entered in the output sequence register 31 will. The sequence register 31 is connected to one input of the AND gate 32. The other input of AND gate 32 is connected to the result register 33. The sorter 26 sets the result register 33 for the initial state of the gates 32 all in the "1" state. The output signal of the AND gate 32 is then entered in the result register 33 by means of the CRR signal set. The sorter 26 then causes the next rule to be accessed from the rule ID register 29 in the rule memory 30 and the associated sequence field is stored in sequence register 31. The content of the sequence register 31 is then

via an AND link with the content of the result register 33 linked, whereupon the result is again stored in the result register 33.

This process of accessing rules in memory 30 is continued until all with the first primitive determination related rules are recorded in register 27. The sorter 26 uses the tester 36 to determine whether the register 29 is empty.

The tester 36 detects an empty state of the register 37. The tester 36 then delivers an empty signal to the sorter 26, which in turn emits the CGS signal, which causes the next primitive determination from the stack memory 25 is entered into register 27 to the primitive memory

28 to be addressed. The process is carried out with regard to the rule ID of the Primitive memory 28 repeats which is in the rule ID register

29 is stored. To the rules regarding the second primitive statement is again accessed piece by piece and the sequences are specified in sequence register 31. Every episode In register 31, an AND link is used to link the previous results in results register 33.

This process of accessing rule sequences corresponding to each primitive statement is continued until all primitive statements and all rules are recorded and the associated consequences via AND operations are connected. If the tester 34 indicates that there are no more primitive determinations present and shows the Tester 36 indicates that there are no more rules, sorter 26 causes decoder 35 to read the contents of the result register 35 checks. If the decoder 35 finds only "O" values in the register 33, it is indicated that the given primitive determination does not conform to the rules of the expert system. More information is required before confirming a result can be.

59 198

The decoder has one and only one value "1" in the result register 33 and emits a corresponding signal via the line 65, then the expert system has a confirmation of the entered primitive statements.

If the decoder 35 has more than a single "1" in the result register 33 after, it indicates (via line 66) that more than one unique confirmation for the given set of Primitive statements exist and that therefore not a single, unambiguous evidence has been determined.

In operation of the arrangement shown in FIG. 4, each rule identifier used in addressing the rule memory 30 becomes stored in the declaration stack 38. The stack memory 38 accordingly supplies the track of the sequence in which the result has been achieved. Is on the explanation stack 38 and the associated rule text of the rule memory 30 is accessed, there is an explanation for the result. The sorter 26 accesses the rule identifications one after the other of the declaration stack 38 by generating the CES signal which is the rule identifiers writes in each case in the lowest memory cell 92 of the explanation stack memory 3 8. Each rule identification in the register 92 addresses the rule memory 30. The addressed memory cell in memory 30 causes the text field section to output device 89 is read out. The output device 89 is typically a screen or a Printer.

Backward chaining:

An expert system for backward chaining is shown in FIG. A target stack 50 is part of the knowledge base 10 of Figure 1. The target stack 50 stores all of the system's targets. As previously defined, the goals are individual follow-up findings. The target stack 50 is

for example a random access memory (RAM) which operates in "LIFO" (batch memory mode). The bottom Register of this stack memory is the register 78. The contents of the memory 50 are under the control of the stack signal Sorter 79 CGOS are sequentially downstored in ordered order whenever a new destination is processed got to.

The sorter 29 is of a conventional type, such as a programmed processor or a hard-wired, programmable one Logic circuit. The sorter 29 generates the control signals, which in FIG. 5 all begin with the letter "C". The timing and function of these control signals will be described below.

In Figure 5, the output stack 72 stores a subset of primitive determinations which, compared to the goals in the target stack memory 50, correspond to those in the rule memory 74 stored P-rules are to be checked. The output stack 72 is typically random access memory (RAM) operating in the aforementioned "LIFO" mode is working. It represents the current status description.

The destination address memory 51 is part of the rule address memory 91, which in turn is part of the knowledge base memory 10 of the Fig. 1 is. The rule address memory 91 can also be used as an "atom table" because it is addressed by atoms. Each memory cell in memory 68 has one or more text fields which are accessed when a text is completed to allow a linguistic explanation of the sequence, with which the test was carried out.

The memory 51 is constructed to recognize any rule in which a specific goal (goal determination) as a result is recognized appears. The memory 51 is created by means of the rule compiler

- Ai - 59 198

or another suitable facility. The destination address store 51 is a random access memory (RAM) which is determined by the contents of the lower register 78 in the Target stack memory 50 is addressed. When addressed by the contents of register 78, the output signal contains the Destination address memory 51 contains all rule identifications in which the destination in register 78 occurs as a result.

The selection gate 53 delivers when the CGOT signal is output the sorter 29 transfers the rule identifications from the addressed memory cell in the address memory 51 to the rule identification register 75. If the CGOT signal is not issued, the gates 53 select the output signal from the address memory 68. Register 75 is activated by the CRID signal of the sorter 69 clocked in order to store the parallel output signals of the selection gates 53. The register 75 is with a variety of Fields are provided, with for each rule identification that is taken from the target address memory 51 or from the sequence address memory 68 is selected, a memory cell is provided. The rule identifiers are unloaded in such a way that a shift takes place from left to right, for example by CSID signals from the sorter 69 to the rightmost one Memory cell 39.

The sequence address memory 68 is part of the knowledge base memory 10 of FIG. 1. The sequence address memory 68 supplies Addressing by an atom from the atom stack 60 the rule identifiers for each of the rules associated with the addressing atom are connected as a sequence. The content of the memory cells 39 of the respectively selected memory 61 or 68 is selected by the rule stack control 54 whenever the CRS signal of the sorter 69 is output. The rule stack control 54 is a push-pop stack memory for sequentially keying in each rule identification from the Store cell 39 of register 75 in stack memory 56. Whenever the CRS signal is asserted by sorter 69,

T920 - / frS - 59 198

the rule stack controller 54 expresses the rule identifiers in the stack 56 downwards. Whenever the CRS signal through the sorter 69 is not released, the rule identifications are removed from the stack memory 56.

The controller 54 has a node bit field 55. The node bit field 55 assumes the values "1" or "0" under the control of the CRSN signal of the sorter 69. The node bit becomes 55 stored as a "0" for all rule identifications except the first rule identifier of register 75, the Rule identifications from the address memory 51 or the address memory 68. Whenever the rule memory controller 54 Reads rule identifications into the stack memory 57, the test RS unit 66 checks whether the last memory location 39 (and thus all fields) in register 75 is empty and causes sorter 69 to stop adding rule identifications to the Enter stack memory 57. When the controller 54 removes rule identifications from the stack memory 57, the Test unit 66 the rule identification bits and the node bits in the top register 78 of the stack memory 56 to to enable control of the system by means of the values "1" or "0" of the bits in the top register 78 of the stack memory 56.

Node control of the rule stack:

For entries in the stack memory 56, the node bit for the first rule identification, which is in the stack memory is entered, set to "1" and each subsequent rule identification of register 75 has the node bit "0". Every rule identification is checked for empty spaces for withdrawals (all on "0") and with regard to the value "1" or "0" of the node bit.

- «- 59 198

To delete the rule stack, the rule identifications with node bits "0" may be deleted as long as until a rule identification with the node bit "1" is found and then all rule identifications with node bits "1" deleted until a rule identification with the node bit "0" is found. This rule identification with the Node bit "0" is not deleted but left at the top of the stack in register 78. So overall it takes place a deletion until a first "0" after a "1" is found.

If the rule identifications are removed from the stack memory 56, the controller 54 outputs the rule identifications that have been removed as an address in the rule memory 74. The rule memory 74 is part of the knowledge base memory 10 of FIG Fig. 1.

The rule memory 74 is under the control of the rule stack controller 54 is addressed by the contents of the top register 78 in the stack 57. The rule identification of the Register 78 addresses the memory 74 and causes all atoms preceding the addressed memory cell (simple Findings) of the rule memory 74 are read into the register 76. They are parallel in register 76 under Control by the CATR signal of the sorter 79 read in. Each atom in register 76 is locked in a different field under control of the CATR signal. The ones in the register Atoms preceding the locked rule are under control of the atom stack controller 58 from register 76 from the left shifted to the right (under control of the CSAT signal from sorter 69) and down in atomic stack 60 read in. The atom stack memory controller 58 is used to store the atoms from the register 76 in the stack memory 60 or to remove atoms from the stack memory 60 under the control of the CAS signals of the sorter 69. If the CAS

Si

Signal given, the controller pushes 58 atoms into the stack 60, while in the absence of a signal, the atoms are removed from the stack memory 60.

The atom stack controller 58 has a node control field 59 which is activated under the control of the CASN signal of the sorter 59. If atoms other than the first atom of the Register 76 are read from the same into the atomic stack memory 60, the node controller 59 causes a Logical "0" is loaded into the associated node field 61. The first atom of register 76 for a particular set of cones is set to the value "1" to identify the node point. The check atom stacker 70 checks that the registers 76 and 79 are full or empty so that the sorter 69 can issue the CASN signal.

Control of the atom stack nodes:

For inputs, the node bit for the first atom of a rule is set to the value "1" and the node bit for each subsequent atom Atom of the rule is set to the value "0".

When an atom is asserted, it is removed from the atom stack 79 removed and entered into the explanation register 77 and then pushed into the explanation stack memory 80. If an atom is confirmed with a node bit "1", the rule stack memory 56 is deleted and the following atom is deleted Stack 66 is also considered confirmed. If the next atom also has the node bit "1", then due to the fact that the next atom is also considered checked, the rule stack is cleared again, and so on until that is in the register 79 top atom has a node bit "0" or the atom stack is empty.

If the CAS signal is not emitted and atoms are removed from the When the stack memory 60 is removed, the node control 59 together with the test atom stack unit 70 has the status "0" or "1" of the node bit in the top memory location of the register 79 of the stack memory 60 after. That way, the operation of the system shown in FIG. 5 is adapted to the value of the bits which are accessed in the atomic stack memory 60.

The atom stack memory controller 58 gives the atom at the top of register 79 as an input to comparator 73 as well as in the sequence address memory 68. Sequence address memory 68 is typically random access memory (RAM), which forms part of the rule address memory 91. The sequence address memory 68 is represented by the atoms in the register 79 of the atom stack memory 60 is addressed.

The comparator 73 compares the atom in the topmost memory location of the stack register 79 with the contents of the register 81, which is the lowest register in output stack 72. The output stack memory 72 acts as a shift register, the The output of the lowest stack register 81 serves as an input into the uppermost memory location of the stack memory 72. To this Manner, the contents of the stack memory 72 are circulated and each entry into the stack memory 72 can be compared with the contents of the Register 79 in the stack memory 60 are compared. The output stack 72 stores primitive atoms, which are used as starting conditions for the examination of the target (determinations) serve, are specified by the target atoms in the target stack memory 50 and the rules stored in the rule memory 74 correspond. The output stack memory 72 is therefore also called the "primitive stack memory".

If the comparator 73 proves an identity, the sorter 69 causes the atom from the register 79 in the register 77 is locked and pushed into the stack memory 64. Of the

59 198

The contents of register 79 are under the control of the declaration stack controller 62 pressed into the stack memory 64. The controller 62 pushes the atoms into the stack memory 64, as soon as a CES signal is issued by the sorter 69 and removed Atoms from stack 64 when no CES signal is asserted. The controller 64 has a node control field 63 which, together with the tester 67, serves to determine the node bits stored in the node fields 65 of the stack memory 64 to prove and control. In addition to the first, every atom which is the last one is removed from the stack 56 Usually related, stored with a logical "0". The first atom is stored with a "1". Will the Rule taken from stack memory 56, which is represented by a sequence of atoms in stack memory 60, not confirmed, i.e. the comparator 73 has no comparison, then all atoms related to this rule will be the have previously been stacked in the declaration stack memory 64, removed from it again. That is, all atoms with a "0" before one with a "1" are removed from the stack memory 64. The "1" or "0" node state from the stack 64 atoms removed is determined by means of the test unit 67, which in turn sends corresponding signals to the Sorter 69 delivers.

The backward chaining operation of the system shown in Figure 5 continues until all of the destinations in stack memory 50 are serviced have been. The sorter 69 always emits the CGOS signal when it is determined by means of the test unit 66 that the Rule stack memory 56 in its top register 78 has a free space to put a new destination in the bottom register of the stack memory 50. The new target is then processed in the same way as the one described above first goal. If all targets from the stack memory 50 have been processed, which is verified by the test unit 52, the sorter 69 signals that the backward chaining analysis is complete.

Si

Control of the declaration stack nodes:

The node bit of the first atom, which has been confirmed for a target is set to the value "1" and then the node bit for each subsequent atom is set to the Value "0" set. If a target is not confirmed, all atoms in the stack memory 64 are deleted with a node bit "0" until the first node bit with the value "1" is detected and this is also deleted. The node bit field 65 on the stack 54 can have more than one bit. For example, the node bit values are field 61 of the stack (for each atom) also stored in the stack memory 64 in order to be able to output a text by means of the output device 91. Each node bit confirmed in this way is used to achieve a level of text explanation.

In Fig. 5, the lowest register 90 in stack memory 64 addresses sequence memory 68 and each atom in register 90 is addressed a storage location in the sequence address memory 68. One or more fields in the memory 68 store a text field, which is given to the output device 89 by means of a logic circuit. Each atom in output register 90 has the effect of that a text field is delivered to the output device 89. The atoms in stack 64 are picked up by the sorter 69 output CES signal depressed, the output of the atoms to the output device 89 typically then occurs after sorter 69 has verified that target verification is complete. The output device 89 is typically a cathode ray tube, printer, or the like. Usually the dispenser 89 is a part the user interface 12 of FIG. 1.

Operation with backward chaining:

The backward chaining operation of the system is explained using the rules in DIAGRAM 2 below, where

11 q? N

\ \ Z £ U - «- 59 198

the primitive statements according to test 1 of DIAGRAM 3 are used. In DIAGRAM 2 the three goals G-, G_ and G- are defined by the rules R ₁₃ / R ₁₄ and R ₁₅ , respectively.

In DIAGRAM 3, five different tests, Test 1, Test 2, Test 3, Test 4, and Test 5, are defined, each with different sets of primitive statements. For example, the predetermined primitive determinations of test 1 are indicated by the symbols A., A- and A ₃ . The sequence of steps for test 1 is given in DIAGRAM 4 for the first objective.

In DIAGRAM 4 (corresponding to FIG. 4) the GS column shows the content of the target stack memory 50, the RS column corresponds the content of the rule stack memory 56, the column AS corresponds to the content of the atom stack memory 60, the column ES corresponds to the inside of the explanation stack 64 and the column GIS corresponds to the contents of the output stack 72. The values "1" or "O" in brackets correspond to the respective node bit.

$ 8

59 198

DIAGRAM 2

rule

pre-condition

episode

R-,

10

4 2 13 44 ¹ 15

A ₁ & A '&

χ 4th

& A

δ A ₄ &

A _c & A, & A ^ A _c & A _£ & A-

B. B ₁ B,

B.

1 DIAGRAM 3 specification ^A 3 test 2 Aj, Aj, ^A 5 test 3 3 '4' ^A 7 test 4th ^A 5 ' ^Λ 6' test 5 A ₁ , A ₂ 3 '4' 5 test A ₁ , A ₂ , test

1,970

I3ZU, _ _Μ _ _{59 198}

DIAGRAM 4

CONDITION GS RS (knot) AS (node) ES (^ Oten) GIS (0) ^A 3 G ₃ ^A 2
0 1.1 ^G 2
^G l 0 (0) 0 (0) ' 0 (0) [ Copy] ^G 3 1.2 ^G 2 R ₁₃ (D 0 (0) 0 (0) [Copy] S. 1.3 ^G 2 0 (0) C ₁ (O) 0 (0) [Copy] ^G 3 C ₂ (I) 1.4 ^G 2 R ₇ (D C ₂ (I) 0 (0) [Copy] G _? 1.5 ^G 2 0 (0) B ₁ (O) B ₂ (I)
C ₁ (O) 0 (0) [Copy] G ₃ C ₂ (D 1.6 ^G 2 R ₁ (O) B ₁ (O) R ₃ (D B ₂ (D
C ₁ (O) C ₂ (I)

- Sri - 59

DIAGRAM 4 (continued )

SUSTANE ) GS RS (knot) AS (Node) ES (node) GIS 1.7 R ₃ (I) ^A l (Ο) ' 0 (0) [.copy] ^G 2 ^A 2
^A 3
^B l Or-IO ^B 2
^C l d)
(O) ^C 2 (1) 1.8 0.0 ^B 2 (D B ₁ (O) [copy] ^C l (O) A ₃ (O) ^C ? (D A ₂ (O) A ₁ (I) 1.9 S. R ₂ (I) ^B ? (D B ₁ (O)! Copy] ^G ? ^G l (O) A ₃ (O) ^C 2 (1) A ₂ (O) A ₁ (I)

1.10 G ₃ 0.0 A ₁ (O) B ₁ (O) [copy]

G ₂ A ₂ (O) A ₃ (O)

A ₃ (I) A ₂ (O)

B ₂ (I) A ₁ (I) C ₁ (O)
C ₂ (I)

59 198

DIAGRAM 4 (continued)

STATE GS RS (node) AS (node) ES (node) GIS

.11 S. 0.0 C ₂ (I) C ₁ (O) [Copy] 1 ^G 2 Bj (O)
A ₃ (O) Aj (O) A ₁ (O) [Copy] .12 S. R ₈ (O) C ₂ (D [Copy] [Copy] 1 ^G 2 R ₉ (D .13 S. R ₉ (D B ₁ (O) I copy] [Copy] 1 ^G 2 B ₂ (I)
C ₂ (D .14 ^G 3 R ₁ (O) B ₁ (O) t copy] [Copy] 1 ^G 2 R ₃ (D
R ₉ (D B ₂ (D
C ₂ (D .15 R ₃ (D A ₁ (O) [ Copy] [ Copy] 1 ^G 2 R ₉ (D A ₂ (O) A ₃ (I) B ₁ (O) B ₂ (I) C ₂ (I)

6t

- Sri, -

DIAGRAM 4 (continued)

STATE GS RS (node) AS (node) ES (node) GIS

.16 ^G 3 0, (0) B ₂ (I) B ₁ (O) [Copy] 1 ^G 2 C ₂ (I) A ₃ (O) A ₂ (O) A ₁ (O) [Copy] .17 S. R ₂ (D B ₂ (I) [Copy] [Copy] 1 ^G 2 C ₂ (I) .18 ^G 3 0, (0) A ₁ (O) tcopy] [Copy] 1 ^G 2 A ₂ (O) A ₃ (I) B ₂ (I) C ₂ (I)

DIAGRAM 4 (continued)

CONDITION GS RS (node) AS (node) 0, (0) 0.0 ES (knot) GIS t 1.19 Gg C ₂ (O) ^A 3 ^G 2 B ₂ (O) ^A 2 Ag (O) ^A l A ₂ (O) 0 A ₁ (O) B ₁ (O) Ag (O) A ₂ (O) A ₁ (O) C ₁ (O) B ₂ (O) Ag (O) ^A 2 (0) A ₁ (O) B ₁ (O) Ag (O) R ₁₄ (D 0.0 A ₂ (O) 0, (0) C ₂ (O) A ₁ (I) 1.20 Gg C ₃ (I) t copy] [ Copy] 1.21 Gg [ Copy] I copy]

- -56 - 59 198

In the DIAGRAM 4, in state 1.1, the target stack memory 50 with the targets G ~, G «and G is loaded. The output stack 72 is loaded with the findings Primitv-A _3, A ₃ and _A1. At this point in time, the sorter 69 has issued an enable signal which clears all other registers and stacks to the "O" state in preparation for the execution of the test. After the deletion, the test units 66 and 70 check whether the rule stack memory 56 and the atom stack memory 60 are free (all at "0"). At this point in time, the test unit 52 determines that the target G _{1 has} not been pushed through to the bottom in the register 78, so that the register 78 is recognized as "not empty". The sorter 69 detects this state and continues the delivery of the CGOS signal, which causes the target G, in the stack register 78 to be pushed through step by step. The destination G ₁ addresses the destination address memory 51. The sorter 69 emits the CGOT signal in order to select the rule identifications from the address memory cell of the destination G. in the destination address memory 51. The target address memory 51 is selected by the selector 53, but not the sequence address memory 68, because the test units 66 and 70 determine the "0" status in the rule stack memory 56 and in the atom stack memory 61.

The rule R ₁₃ ID (ID = identification) is that which was determined from the address memory 51 for the destination G ₁ . It is stored in register 75. The CRID signal locks the rule R ₁₃ ID in register 75. The sorter 69 then generates a CSID signal to shift the R ₁₃ ID into the right field memory cell 39. At this point in time, the test unit 66 determines that the field 39 is not in the "0" state, and therefore R _{13 is} entered into the rule stack memory controller 54. The rule stack 54 is controlled by the CRS signal to push R ₁₃ in the rule stack 56 into the top memory cell 78. The CRSN signal is issued so that the node bit assumes the value "1". The state of the in Fig. 5

- · & 6 - 59 198

The system shown corresponds to state 1.2 in DIAGRAM 4 at this point in time. The expression copy in the column G sharp shows indicates that the state of the output stack memory in the state includes all inputs of the previous state 1.1.

In state 1.2 of DIAGRAM 4, the test unit 66 detects the presence of the rule ID R ₁ in the rule stack memory 78 and takes the rule R 1 ^ ID from the register 78 in order to address the rule memory 74. The rule memory 74 is then accessed and all of the atoms preceding the rule R ... are loaded into the register 76 by the output of the CATR signal from the sorter 69. The CSAT signal is then emitted by the sorter 69 until all atoms, in this case C 1 and C ″, have been reloaded into the atom stack memory 60 via the storage cell 24 by the atom stack controller 58. The atom loaded first is C ", whose node bit is set to the value" 1 ". As the second and last atom, C. is pushed into the stack memory with its node bit set to the value "0". At this point in time, the test unit 70 determines that the memory cell 24 is empty and signals the sorter 69 to end the pressing of atoms into the atomic stack memory 60 via the controller 58. The state of the system shown in FIG. 5 at this point in time corresponds to state 1.3 of DIAGRAM 4.

In state 1.3, the test unit 70 verifies that the atom stack memory 60 has a non-empty uppermost register 79 and causes the atom stack controller 58 to enter the content of the register 79 into the comparator 73. If the content of the register 79 is in the comparator 73, the sorter 69 uses the test unit 71 to determine that the lowest register 81 in the stack memory 72 is in the "0" state. The sorter 69 then emits the CGIS signal, whereupon the value “0” is taken from the register 81 and pushed to the top of the stack, which represents the A ₁ -AtOm in the register 81. The comparator 73 compares the content of the register 81 with that

- 57 - 59 198

Contents of the atom stack register 79. If a comparison criterion is determined by the comparator 73, the contents of the Register 79 locked in register 77 by means of a CEXR signal and pushed into explanation stack 64. In state 1.3, however, C does not correspond to a comparison criterion with A- in register 81, so that no comparison is made. The sorter 69 in turn emits the CGIS signal, whereby A .. from the Stack is removed and pushed back to the top, with A "remaining in register 81. This process of the Comparison of each entry in the output stack 72 continues until A "and A_ again go back to the stack are pressed. The sorter 69 outputs the CGIS signal until the tester 71 again determines that in the register 81 the state "0" prevails everywhere, regardless of whether the comparator 73 finds a comparison criterion. Surrendered If there is no comparison criterion, atom C in register 79 is not removed from stack memory 60, but remains rather there.

The contents of the register 79 are also taken by the controller 58 and entered into the sequence address memory 68. Since rule stack 56 and atom stack 60 are not both empty, sorter 69 does not issue a CGOT signal and thus selects the output of the sequence address memory 68. The rule that precedes the rule addressed by C- in the sequence address memory 68 is latched in register 75. As beforehand, the contents are shifted from left to right through the memory cell 39 and into the rule stack memory 56. At the given embodiment is the accessed rule ID R_, which appears in register 78 with a node bit that is set to "1". The state of the system shown in FIG corresponds to state 1.4 of the DIAGRAM at this point in time

In state 1.4 with rule stack memory 56 that is not empty, register 77 empty, which is verified by test unit 67 and means that nothing has entered the declaration stack 64

has been given, the controller 54 combines the contents of the register 78 to address the rule memory 74. The rule ID R_ addresses the memory 74 and causes the rule that precedes this rule to be entered in the register 76 by emitting the CATR signal is locked. Thereafter, as before, the content of the register 76 is transferred to the memory cell 24 by the CSAT signal loaded to be pushed to the top of the atom stack 60 via the controller 58. The state of the in Fig. 5 The system shown corresponds to state 1.5 in DIAGRAM 4 at this point in time.

In state 1.5, that is to say after loading the atomic stack memory 60, the controller 58 is caused by the sorter 69 to feed the contents of the register 79 to the comparator 73. The comparator 73 then compares the content of the output stack memory 72 with the B ₁ content of the register 79. Since B ₁ cannot be compared with any of the contents in the output stack memory 72, no comparison signal is output to the sorter 69. Accordingly, the input of the register 79 remains connected via the controller 58 in order to address the sequence address memory 68. The sequence address memory 68 supplies the rule identifications for all rules which have B as a result in the register 75. The register 75 is then unloaded into the rule stack 56 via the memory cell 39 and the controller 54. The first rule ID loaded is R-, whose node bit is set to "1", and the second unloaded rule is R ₁ , whose node bit is set to "0". At this point in time, the state of the system shown in FIG. 5 corresponds to state 1.6 of DIAGRAM 4.

In state 1.6, the R ₁ content of the rule stack memory 78 addresses the rule memory 74 and is removed. The field preceding rule R ₁ is loaded into register 76 and unloaded via controller 58 and pushed to the top of stack 60. At this point in time, the state of the system shown in FIG. 5 corresponds to state 1.7 of DIAGRAM 4.

In state 1.7, the controller 58 feeds the value A ₁ in the register 79 to the comparator 73. The comparator 73 compares the A value of the register 79 with the contents of the output stack memory 72. The output stack memory 72 contains A., so that the comparator 73 determines the comparison criterion and transmits a corresponding signal to the signal sorter 79. On the basis of the verification of the comparison _{criterion for atom A 1} , the CEXR signal is emitted in order to lock atom A. in register 77. At the same time, the contents of the register 77 are selected by the controller 62 in order _{to push the atom A 1} into the stack memory 64. Since atom A ₁ is the first to be pushed into the stack for the target, its node bit corresponds to the value "1". If the register 77 contains a value which is determined by the test unit 67, the controller 58 connects the uppermost value in the register 79, which is the A_ atom at this point in time, since the A ₁ -AtOm is taken from the register 77. The A ₃ -AtOm is compared in the comparator 73 with the contents of the output stack memory 72. A comparison criterion is again found and the atom A_ is taken from register 79 and read into register 77. The controller 62 in turn causes the atom A_ to be pushed into the stack 64 with its node bit set to the value "0".

_{The atom A 3} occurring in the register 79 is again compared in the comparator 73 in order to find a comparison criterion with the A_ input in the stack memory 72. The A_ atom of register 79 is locked in register 77 and pushed into stack memory 64, the node bit having the value "0". The tester 67 proves that the node bit in register 77 of the A ₃ atom from register 79 has the logical value "1". The sorter 79 therefore automatically takes the next atom in the register 79, the B ₁ -AtOm, and feeds it into the register 77 and pushes it into the stack memory 64. Furthermore, the sorter 69 causes the rule stack memory to be cleared so that R ₃ (D is removed and not used while register 77 is cleared.

- frO - 59 198

by reading in all "O" values from memory cell 24 via controller 58. At this point in time, the tester 67 determines an "O" for the node bit of B ₁ in register 77, so that no further extraction of atoms from the stack memory 60 takes place without further testing. At this point in time, the state of the system shown in FIG. 5 corresponds to state 1.8 of DIAGRAM 4.

In state 1.8 the B_ atom is removed from register 79 by means of Controller 58 is entered into comparator 73 and compared with the contents of output stack memory 72. Since B “is not a primitive statement is on stack 72, addresses the B rule ID the sequence address memory 68 and causes all rules in which B_ occurs as a sequence to be entered into the register 75 will. The rule ID in register 75 is R ", which is in the rule stack 56 is pushed. At this time, the state of the system shown in Fig. 5 corresponds to the state 1.9 of DIAGRAM 4.

In state 1.9, the R ₂ rule ID addresses the rule memory 74 via the controller 54 and the atoms associated with R "are stored in the register 76, while R_ is taken from the register 78. These atoms connected with R "are pushed into the stack memory 60 and the state of the system shown in FIG. 5 corresponds to state 1.10 in DIAGRAM 4.

In state 1.10, the atoms in stack memory 60 are compared with the contents of output stack memory 72, specifically in the order in which they are pushed into the topmost position of register 79. A comparison is made sequentially for A .., A ₂ and A ₃ and each of these atoms is therefore pushed into the explanation stack 64 over the information that is already in this memory. The information already in the stack memory 64 is shown in state 1.9 and for the sake of simplicity

- 64 - 59 198

indicated in state 1.10 by the word COPY. Correspondingly, at this point in time, A _{1, A 1 and A 3 have been} removed from the atomic stack memory 60 and pushed into the explanation stack memory 64. If the A ₃ -AtOm appears in register 77, the node bit "1" is determined by the test unit 67, so that the next atom B_ appearing in register 79 is also removed from the stack memory 60 and pushed into the stack memory 64. If the atom B _{1 appears} in the register 77, it also has the node bit "1", which is detected by the unit 67, so that the next unit in the atom stack register 79 is also removed and pushed into the stack memory 64. This is the C ₁ atom. At this point in time, the state of the system shown in FIG. 5 corresponds to state 1.11 in DIAGRAM 4. It should be noted that the C ₁ , B ₃ , A, A n and A atoms are on the top layers be pressed via the information previously stored in the stack memory (which is indicated by the word COPY and is explicitly shown in state 1.9).

In state 1.11 there is C ₁ with the node bit "0" in register 77. Therefore, the sorter 69 causes the controller 58 to send the C _? -Atom from the register 79 into the comparator 73. Since no comparison criterion corresponding to C "is found in the output stack memory 72, C_ is used to address the sequence address memory 68. The rule identifiers for C _? are locked in register 75 and pushed down in rule stack memory 56. These rule identifications are R _fi and Rg. The status of the sorter at this point in time corresponds to status 1.12 in DIAGRAM 4.

In state 1.12, the Rg-Regel-ID of the register 78 addresses the rule memory 74 and causes the B ₁ and B ₂ atoms in the atomic stack memory 60 to be pushed down. This state of the system is identified in DIAGRAM 4 with 1.13.

59 198

In state 1.14, the B, -atom is addressed in the atomic stack 60 moves the sequence address memory 68 and pushes R_ and R. into the rule stack.

Then R- addresses the rule memory 74 and pushes the atoms A_, A_ and A ₁ into the atom stack memory 60.

In state 1.15 we get for each of the atoms A ₁ , A _? and A_ a comparison criterion and they are pushed into the explanation stack. Since the A, atom has a node bit "1", the B ₁ -AtOm is also printed in the stack. Since the stack memory is filled up to the node, the cone memory is deleted according to the deletion rules. Since all rules have the node bit "1" in state 1.15, all rules in the stack are deleted. The state of the system shown in FIG. 5 at this point in time corresponds to state 1.16 in DIAGRAM 4.

In state 1.16 there is _{no comparison criterion for the B 2} -AtOm in the atom stack and the R_ rule ID in the rule stack 56 is used accordingly. At this point in time, state 1.17 in DIAGRAM 4 has been reached.

In state 1.17, the R “rule ID addresses the rule memory 74 and causes the atoms according to R "according to the state 1.18 must be pushed into the atomic stack memory 60.

In state 1.18 there is _{a comparison criterion for the atoms A 1} , A 1 and A ₃ and they are removed from the atom stack and pushed into the explanation stack. Since the atom A_ has a node bit "1", the topmost B ~ value in the stack memory 60 is also taken from it and pushed into the explanation stack memory. Since B "also has the value" 1 "in the node bit, the next value C" in register 79 is also taken from the atomic stack and stored in the explanation

- # 3 - 59 198

Stack pressed. At this point in time, the state of the system shown in FIG. 5 corresponds to state 1.19 in DIAGRAM 4.

In state 1.19, the uppermost registers 78 and 79 of the rule stack memory 56 and the atom stack memory 60 are shown to be empty. Accordingly, the sorter 79 again emits the CGOS signal, as a result of which the next destination is fed into the register. At this point in time, the target G ″ addresses the target address memory 51 and the selector 53 causes the rule ID for G ″ in the register 75 to be locked. This rule ID is R ₁₄ / which is pushed onto the rule stack 56. At this point in time, the processing of the second target is continued and the state of the system shown in FIG. 5 corresponds to state 1.20 in DIAGRAM 4.

In state 1.20, the rule ID R ₁₄ addresses the rule memory 74 from the stack memory 56 and is removed from the stack memory, whereupon the atoms C_ and C »are pushed onto the stack memory. The state of the system shown in FIG. 5 now corresponds to state 1.21 in DIAGRAM 4.

The processing of the goal G ″ is continued following the state 1.21 analogously to the states 1.1 to 1.19 of the goal G ₁ (as described above). When the processing of the target G "is completed, the CGOS signal is emitted again so that the G_ target is processed in the same way as the G and G ₂ targets.

Are the register 78 in the target stack memory 50 and the top registers 78 and 79 in the rule stack memory 56 and the atomic stack memory 60 are all empty, the sorter 69 will recognize this state and test 1 of DIAGRAM 3 is complete.

- -fr4 - 59 198

Additional tests, for example tests 2-5 of DIAGRAM 3, can then be carried out, the sequence corresponding to DIAGRAM 4 corresponds to that previously described.

Once a test has been completed, the sorter 69 usually communicates with the interface 12 (FIG. 1), if necessary upon query, for the textual description of the sequence determined by the atoms in the explanation stack 64 to spend. To output the text information, the sorter 69 repeatedly outputs CES signals to stack the atoms 64 downwards, one at a time, according to the LIFO principle. Each atom appearing in the lowest register 90 is addressed the sequence address memory 78, which in turn makes a text field available to the output device 91. is the output device 91 a printer, a textual description of the way in which the result was obtained, printed out so that it can be understood by humans.

Claims (22)

-1- "1- · SCHWEIGERSTRASSE 2 LA-59 198 phone: (089) 6620 ji telegram: protectpatent Telex: 524070 fax: via (089) 271 6063 (in) patent claims: 1. data processing system,
marked by a knowledge base memory (10) for storing rules in flat files, each rule having a plurality of statements, which are linked in a manner specified in the associated flat file, a primitive memory (28) for storing one or Ί several primitive statements, a target memory (50) for storing one or more target statements and an inference device (11) for processing primitive statements and goal-statements to determine whether the goal-statements conform to the rules given by the primitive statements beeing confirmed. 2. Data processing system that uses backward chaining to check whether certain target statements meet certain rules when one or more primitive statements are present as the initial state,
marked by a rule memory (30) for storing rules in flat files, Each rule has a prerequisite and a consequence, each formed by one or more statements which are linked to one another in a manner specified in the associated flat file, «£ - 2 - 59 198 a primitive stack (28) for storing one or more primitive statements, a target stack (50) for storing one or more target statements, each target statement being a sequence of a Rule from the rule memory (30) is a rule address memory (91) with memory cells for rule addresses, wherein each memory cell is addressed by an addressing statement and wherein each rule address memory cell is rule addresses of rules which contain the addressing statement as a sequence, a rule stack memory (56) for storing rule addresses which are accessed in the rule address memory (91) is, a statement stack (60) for storing statements which represent the prerequisites in those rules which is accessed in the rule memory (30), a comparator (73), which primitive statements from the primitive stack (28) compares with statements from the statements stack memory (60) and which emits a comparison signal, as soon as a statement from the stack memory (60) matches a primitive statement according to a comparison criterion, and a sorter (69) for processing primitive and goal statements to determine whether the goal statements match the Primitive statements are confirmed according to the rules, the sorter (69) executing the following functions: Input the target statements from the target memory (50) to address the rule address memory (91), entering rule addresses from the addressed memory cell in the rule address memory (91) into the rule stack memory (56), input of rule addresses from the rule address stack (91) to the rule memory (56) entering prerequisite statements from rule memory (56) into the statement stack (60), inputting statements from the statements stack (60) into the comparator (73) for comparison with to enable the primitive statements from the primitive memory (28). - 3 - 59 198 3. Data processing system according to claim 2, characterized in that an explanation stack memory (64) is additionally provided is with explanation stack cells and with an explanation stack memory controller (62), which respond to the sorter (69), always put statements into the explanation stack (64) to press when the comparator (73) according to a comparison criterion between a statement in the primitive stack (28) and a statement in the statement stack (60) recognizes a match. 4. Data processing system according to one of claims 2 or 3, characterized in that the rule stack (56) is a push-pop rule stack with rule stack cells and a rule stack controller (54), each rule stack cell having a rule address node bit field which is used to push statements into the rule stack and extract statements from it to enable this stack. 5. Data processing system according to one of claims 2-4, characterized in that that the rule stack memory (56) is a rule stack node bit control to set the first rule address node bit to a certain state, each subsequent Rule address node bit for all rule addresses resulting from the addressing statement in the opposite state is set. 6. Data processing system according to one of claims 2-4, characterized in that that the statements stack (60) is a push-pop ("push-in-take-out") stack has which statement stack cells and <a statement stack control (58) to statements from - 4 - 59 198 the rule memory (74) into the statement stack (60) Press, as well as means to remove the statements from the statements stack (60). 7. Data processing system according to claim 6, characterized in that that the statements stack has a statements stack node bit field for each statement stack cell, the statement stack controller (58) including means to generate a statement stack node bit for the first statement of a rule to be set in a certain state value, whereupon the node bit for each subsequent one Statement is usually put in the opposite state. 8. Data processing system according to one of claims 2-7, characterized in that it is marked, that means for transferring a statement from the statement stack (60) is provided in order to address the rule address memory (91) in the absence of a comparison signal, so that statements on the rule stack memory (56) can be pressed accordingly. 9. Data processing system according to one of claims 2-8, characterized in that that a rule stack memory tester (66) is provided to check and to check rule addresses in the rule stack memory (56) determine if the rule stack (56) is empty and that a statements stack tester (70) is provided to test statements test in the assertion stack (60) to determine if the assertion stack (60) is empty wherein said rule stack tester (66) and said assertive stack tester (70) are connected to the sorter (69) to indicate to the latter that it is making a target determination select the target stack (50) if the rule stack (56) and the assertion stack (60) are both are empty. - 5 - 59 198 10. Data processing system according to one of claims 3-9, characterized, that the declaration stack (64) is a push-pop declaration stack and a declaration stack controller (62), each declaration stack memory cell having a declaration stack node bit field and the explanation stack control (62) comprises means for adding statements to the explanation stack to press and to take statements under the control of the sorter (69) from the explanatory pile. 11. Data processing system according to claim 10, characterized, that an output device (89) is provided which with the Usually address memory (91) is connected to text statements the rule address memory (91) sequentially in response to the addressing of the rule address memory (91) by in the explanation stack submit saved statements. 12. Data processing system with which it is checked by means of forward chaining whether certain target statements meet certain rules when one or more primitive statements are present as the initial state,
marked by a rule memory (30, 56) for storing rules in flat files, each rule having a prerequisite and a Has sequence, which are each formed by one or more statements that are linked to one another in a in the corresponding Flat file specified manner are linked, a primitive stack memory (28) for storing one or several primitive statements, a rule address memory (91) with rule address memory cells, where each rule address memory cell by primitive statements is addressed, which is accessed in the primitive stack memory (28), and wherein each rule address memory cell Saves rule addresses of rules which have the addressing primitive statement as a result, - 6 - 59 198 a rule address register (29) for storing rule addresses, which is accessed in the rule address memory (91), the rule address register for addressing the rule memory connected is, a sequence register (31) for storing statements which form the sequences of the rules to which the rule memory (30) is accessed a linking device (32) which sequence statements from the sequence register (31) with the contents of the result register (33) linked in order to generate a new result, which in turn is entered into the result register (33), and a decoder (35) which is connected to the result register (33) in order to detect its state and thereby determine, whether the primitive statements conform to the rules. 13. Data processing system according to claim 12, characterized in that that the logic device (32) is a logical AND gate to the contents of the sequence register (31) and the result register (33) to be linked in an AND function. 14. Data processing system according to one of claims 12 or 13, characterized , that further a declaration stack memory (38) is provided which is connected to the rule address register (29) in order to store each rule address accessed in the primitive stack memory (28). 15. Data processing system according to claim 14, characterized in that that an output device (89) is also provided, which is connected to the rule memory (30) and text explanations from the rule memory (30) one after the other in response to an addressing of the rule memory (30) by in the explanation stack (38) sends stored rule addresses. - 7 - 59 198 16. Data processing methods using rule memories for storing rules in flat files, each rule having a prerequisite and a sequence which respectively are formed by one or more statements that are given together in a given in the associated flat file Related manner, using primitive memories to store one or more primitive statements as well of target memories for storing one or more target statements, the method comprising the following steps: each of the named primitive statements is accessed one after the other, each of the stated target statements is accessed one after the other and the recorded primitive statements and target statements are processed, to determine if they conform to the rules. 17. The method according to claim 16,
characterized in that the data processing system has a rule address memory, rule address stack memory and a statement stack memory, the processing step having the following individual steps for each target statement accessed by backward chaining: Connect a target statement from the target stack to to address a rule address memory, inputting the rule addresses of the addressed memory cells iir. Rule address memory in the rule stack, connecting the rule addresses from the rule address stack, in order to address the rule memory, input of prerequisite statements from the rule memory into the statements stack, and Entering statements from the statements stack into the comparator to make a comparison with the primitive statements to perform the primitive memory. - 8 - 59 198 18. The method according to claim 17,
characterized, that the rule address stack is a rule address node bit field and that the statements stack has a statements stack node bit field having, the following steps being provided in the method: Pushing in and taking out rule addresses into and out of the rule address stack under the control of the Rule address node bit field and push in and out of statements to and from the statement stack under control of the statement stack node bit field. 19. data processing system,
marked by a knowledge base memory (10) for storing rules in flat files, each rule having a plurality of statements, which are linked to one another in a manner specified in the corresponding flat file, a primitive memory (28) for storing one or more primitive statements, and an inference device (11) for processing the primitive statements, to determine whether the primitive statements match the rules. 20. Data processing system according to claim 19, characterized in that that a target stack memory (50) is provided for storing one or more target statements, each target statement is a sequence of a rule from the rule memory and wherein the inference device (11) furthermore has one or more push / pop stack, each having a node bit field to control the depression and extraction of statements into and out of the push / pop stacks. - 9 - 59 198 21. Data processing system according to claim 20, characterized in that that the inference device (11) has a comparator (73) for comparing primitive statements with statements from one the push / pop stack has to send a comparison signal to be generated if the statements mentioned correspond to a comparison criterion. 22. Data processing system according to one of claims 20 or 21, characterized, that the inference device (11) has an explanation stack in order to store statements from the push / pop stacks in accordance with the comparison signal.