DE3462741D1 - Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase l code, and the modified biphase code - Google Patents

Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase l code, and the modified biphase code

Info

Publication number
DE3462741D1
DE3462741D1 DE8484102331T DE3462741T DE3462741D1 DE 3462741 D1 DE3462741 D1 DE 3462741D1 DE 8484102331 T DE8484102331 T DE 8484102331T DE 3462741 T DE3462741 T DE 3462741T DE 3462741 D1 DE3462741 D1 DE 3462741D1
Authority
DE
Germany
Prior art keywords
code
biphase
combination
data transmission
recovery circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484102331T
Other languages
English (en)
Inventor
Serge Surie
Francois Marcel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Alcatel Lucent SAS
Original Assignee
Alcatel CIT SA
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR8304038A external-priority patent/FR2542532B1/fr
Priority claimed from FR8319211A external-priority patent/FR2556153B2/fr
Application filed by Alcatel CIT SA, Alcatel SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of DE3462741D1 publication Critical patent/DE3462741D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
DE8484102331T 1983-03-11 1984-03-05 Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase l code, and the modified biphase code Expired DE3462741D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8304038A FR2542532B1 (fr) 1983-03-11 1983-03-11 Circuit de recuperation du rythme d'une transmission synchrone de donnees utilisant une combinaison des codes biphase l et biphase modifie
FR8319211A FR2556153B2 (fr) 1983-12-01 1983-12-01 Circuit de recuperation du rythme d'une transmission synchrone de donnees utilisant une combinaison des codes biphase l et biphase modifie

Publications (1)

Publication Number Publication Date
DE3462741D1 true DE3462741D1 (en) 1987-04-23

Family

ID=26223328

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484102331T Expired DE3462741D1 (en) 1983-03-11 1984-03-05 Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase l code, and the modified biphase code

Country Status (5)

Country Link
US (1) US4599735A (de)
EP (1) EP0121750B1 (de)
CA (1) CA1208312A (de)
DE (1) DE3462741D1 (de)
IE (1) IE55120B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2583180B1 (fr) * 1985-06-10 1987-08-07 Cit Alcatel Procede et dispositif de reduction de gigue d'un train numerique synchrone en vue de la recuperation de son rythme
US4845575A (en) * 1987-10-06 1989-07-04 Standard Microsystems Corporation Analog floppy disk data separator
EP0312671B1 (de) * 1987-10-19 1993-01-27 International Business Machines Corporation Prädiktive Taktwiedergewinnungsschaltung
US4888791A (en) * 1988-01-25 1989-12-19 Barndt Sr Robert A Clock decoder and data bit transition detector for fiber optic work station
US5287359A (en) * 1991-04-08 1994-02-15 Digital Equipment Corporation Synchronous decoder for self-clocking signals
US5535217A (en) * 1994-12-20 1996-07-09 International Business Machines Corporation Method and apparatus for probabilistic clock synchronization with interval arithmetic
EP0831478B1 (de) * 1996-09-24 2003-11-19 Hewlett-Packard Company, A Delaware Corporation Datenverarbeitungsgerät und -verfahren

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916324A (en) * 1971-07-01 1975-10-28 Sanders Associates Inc Method and apparatus for producing a baud timing signal from a modulated carrier signal
JPS5094864A (de) * 1973-12-18 1975-07-28
FR2335102A1 (fr) * 1975-10-16 1977-07-08 Cit Alcatel Dispositif de decodage d'un message en code biphase differentiel
US4232197A (en) * 1978-08-25 1980-11-04 Bell Telephone Laboratories, Incorporated Processor for a TDMA burst modem
NL7902340A (nl) * 1979-03-26 1980-09-30 Philips Nv Werkwijze voor het synchroniseren van de quadphase- ontvanger en kloksynchronisatie-inrichting voor het uitvoeren van de werkwijze.
US4320525A (en) * 1979-10-29 1982-03-16 Burroughs Corporation Self synchronizing clock derivation circuit for double frequency encoded digital data
US4301417A (en) * 1980-03-12 1981-11-17 Ncr Corporation Quadriphase differential demodulator

Also Published As

Publication number Publication date
EP0121750A1 (de) 1984-10-17
CA1208312A (fr) 1986-07-22
IE55120B1 (en) 1990-06-06
US4599735A (en) 1986-07-08
EP0121750B1 (de) 1987-03-18
IE840596L (en) 1984-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee