DE3462722D1 - Binary multiplier with sign extension for the multiplication of signed and unsigned numbers - Google Patents
Binary multiplier with sign extension for the multiplication of signed and unsigned numbersInfo
- Publication number
- DE3462722D1 DE3462722D1 DE8484400987T DE3462722T DE3462722D1 DE 3462722 D1 DE3462722 D1 DE 3462722D1 DE 8484400987 T DE8484400987 T DE 8484400987T DE 3462722 T DE3462722 T DE 3462722T DE 3462722 D1 DE3462722 D1 DE 3462722D1
- Authority
- DE
- Germany
- Prior art keywords
- signed
- multiplication
- sign extension
- binary multiplier
- unsigned numbers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8308431A FR2546318B1 (fr) | 1983-05-20 | 1983-05-20 | Multiplieur binaire avec extension de signe pour la multiplication de nombres signes ou non signes |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3462722D1 true DE3462722D1 (en) | 1987-04-23 |
Family
ID=9289061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484400987T Expired DE3462722D1 (en) | 1983-05-20 | 1984-05-15 | Binary multiplier with sign extension for the multiplication of signed and unsigned numbers |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0128072B1 (de) |
DE (1) | DE3462722D1 (de) |
FR (1) | FR2546318B1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4748582A (en) * | 1985-06-19 | 1988-05-31 | Advanced Micro Devices, Inc. | Parallel multiplier array with foreshortened sign extension |
FR2650088A1 (fr) * | 1989-07-18 | 1991-01-25 | Thomson Csf | Procede pour la generation de schemas logiques de circuits multiplieurs parametrables a decodeur de booth au moyen d'un ordinateur et circuits multiplieurs correspondants |
EP0840207A1 (de) * | 1996-10-30 | 1998-05-06 | Texas Instruments Incorporated | Ein Mikroprozessor und Verfahren zur Steuerung |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4369500A (en) * | 1980-10-20 | 1983-01-18 | Motorola Inc. | High speed NXM bit digital, repeated addition type multiplying circuit |
-
1983
- 1983-05-20 FR FR8308431A patent/FR2546318B1/fr not_active Expired
-
1984
- 1984-05-15 DE DE8484400987T patent/DE3462722D1/de not_active Expired
- 1984-05-15 EP EP84400987A patent/EP0128072B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0128072A1 (de) | 1984-12-12 |
EP0128072B1 (de) | 1987-03-18 |
FR2546318A1 (fr) | 1984-11-23 |
FR2546318B1 (fr) | 1987-12-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |