DE3431756A1 - CIRCUIT ARRANGEMENT FOR PROCESSING INQUIRED SIGNALS - Google Patents

Description

3 * 31756

ROA 80 176 Ks / Ri

U.S. Serial No. 527.795

Filed: August 30, 1983

RCA Corporation New York, N.Y., V.St.v.A.

Circuit arrangement for processing queried signals

The invention relates to an arrangement for processing so-called sample signals, which are understood here to be signals that appear in the form of discrete interrogations or "samples".

In a facility that is composed of two components When the sample signal is processed, the components should expediently be the same when they are separated Have peak amplitudes. In this case, each of the two components can use the full dynamic range of the processing device to complete. This reduces the quantization noise of each component and the Signal-to-noise ratio increased. The present invention is directed to an arrangement in which this object is achieved will.

The invention can be used with particular advantage in the processing of the chrominance signal in a color television

system, where the video signals are separated into luminance and chrominance signals. The chrominance signal can be viewed as a vector quantity, which is opposed by specifying an amount and an angle a reference angle can be described · By projection this Vector on two mutually perpendicular axes, two orthogonal components of the chrominance signal are obtained. in the Such is the chrominance channel of a color television system Component decomposition e.g. along the two to each other perpendicular (R-Y) and (B-Y) axes to obtain the components R-Y and B-Y. For signals used in the USA According to the NTSG television standard, the amount of the luminance signal is between 0 and 100 IRE units. In the Formation of the color television signal becomes the amount of the (B-Y) color component weighted with the factor 0.4-93 and the amount of the (R-Y) color component with the factor 0.877, in order to limit maximum amplitude overshoots of the signal to values within the desired ranges. So will for a saturated blue signal, the maximum amount of the (B-Y) component of 89 IRE units modified by a factor of 0.4-93, so that the maximum (B-Y) amount is approximately 4-3.9 IRE units. Similarly, will for a saturated red signal, the maximum amount of the (R-Y) vector component of 70 IRE units modified by a factor of 0.877 so that the maximum (R-Y) amount is approximately 61.4 · IRE units reduced. These signals can have either positive or negative polarity.

However, in an NTSC system, the (B-Y) and (R-Y) components can be brought back to 89 or 70 IRE units, so that the image is saturated Image components to be displayed in red and saturated blue also appear correctly. Usually this is done Recovery in the final processing stage by choosing the relative weight coefficients in a Color signal matrix circuit. The matrix circuit weights and combines the luminance signals and the

- ο- Ι components of the chrominance signal so that the control signals R, G and B for the primary colors red, green and blue are obtained in standardized relationships. These control signals R, G and B are sent to the picture tube to display the picture.

One problem is that the (B-Y) component, which has the lower magnitude (i.e., ± 4-3.9 IRE units), the strongest picture tubes - drive signal must generate (i.e.

± 89 IRE units), so that noise components or errors that introduced by such processing are more visible to a viewer than errors in the (R-Y) component. This problem becomes even greater when the (R-Y) and (B-Y) signals are processed the same or in common Circuits used because then the dynamic range of these circuits for the one with the higher amplitude occurring (R-Y) signal must be interpreted. The consequence is that the (B-Y) signal has the available dynamic range the processing circuit is not fully utilized. To reduce such problems, it would be useful to increase the amount of the (B-Y) component relative to the amount of the (R-Y) component at a relatively early stage Processing stage and not just at the end.

The above problem is particularly severe in a digital television signal processing circuit because the number of different possible values that the control signals R, G and B can have at the end the quantization resolution inherent in a digitized signal is limited. As an example, consider the case that for digitizing an analog video signal, its amplitude is between the sync pulse peak (-40 IRE units) and the maximum white level (+100 IRE units) moved, an analog / digital converter (A / D converter) with 7 bits (128 quantization levels) is used. The resulting quantization resolution is then about 140/127 = 1.10 IRE units per quantization

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leap. The (B-Y) signal that exceeds 43.9 IRE units then corresponds to about 39 quantization steps (digital steps) and the (R-Y) signal that exceeds 61.4 IRE units corresponds to about 55 digital steps. This shows that the magnitude of the (B-Y) signals is much lower than the magnitude of the (R-Y) signals.

However, the most uncomfortable problem arises because of the limited Quantization in digital signal processing and when converting the quantized signals back into analog signals. As an example, consider a digital television signal processing system in which the digital signals (R-Y) and (B-Y) are each limited to 6 bits (64 quantization levels). Since the digital signals are both must represent positive and negative signal excursions, a digital value applies to the zero value, so that 63 digital values remain for levels other than 0. In addition, since the positive and negative fractional amounts are symmetrical , only ± 31 digital values can be used for signal deflections (i.e. 62 digital values for from 0 different levels).

When the scaling (i.e. the digitization scale) for the (R-Y) signal is optimally chosen, so that the range of available digital values is fully utilized in this signal, then includes the scaled in the same way (B-Y) signal has a range of only [(43.9 IRE units) / (61.4 IRE units)] · (± 31) digital values = ± 22.16 digital values, i.e. in reality only ± 22 values are used for this signal. When the chrominance signal is brought back to the full level as an output signal, then, for example, the (B-Y) -component covers a range of ± 89 IRE units, which, however, only extends from the mean ± 22 Levels of the digital (B-Y) component is filled.

The output-side quantization resolution is thus about 4.05 IRE units per quantization jump which is pretty bad and has color outlines to be observed

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can result in the television picture. These contours give the picture an unnatural, artificial look.

If the (B-Y) component were to be amplified in such a way that it had the encompasses the entire range of ί.31 levels, then one would get a much better output-side quantization resolution of approximately 2.87 IRE units per quantization jump. However, this cannot be done simply by multiplying the (B-Y) signal by its magnitude range to increase, because by such a measure the ^ 22 levels, which until then the middle part of the £ 31 available levels, only be replaced by ^ 22 other levels, which in larger Distance distributed over the entire -31 level range lie. So you have to take more extensive measures in order to use a larger number of the available digital values for more precise information Representation of the (B-Y) -lParbart component to be able to use.

The component decomposition of the chrominance signal can also be along orthogonal coordinate axes other than along the (R-Y) and (B-Y) axes. You can have a pair of axes choose in which the resulting components differ less in terms of their maximum amplitude are as the components shown along the (R-Y) and (B-Y) axes. The chrominance signal is broken down along such a pair of axes, then there is a better resolution of the components in the subsequent processing possible. The object of the invention is to provide a To create arrangement for realizing this principle.

The essential features of an arrangement according to the invention are described in claim 1. Beneficial Refinements of the invention are set out in the subclaims marked.

The arrangement according to the invention contains a device

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to transform a first and a second signal, which have a predetermined phase position with respect to a reference phase, into signals that are at a predetermined phase angle are rotated, which is chosen such that copies of the transformed signals have comparable amounts in order to be able to use the dynamic range of subsequent processing circuits more effectively.

According to one embodiment of the invention, the predetermined Phase angle chosen so that there is an effect in the output signal that limits the effects Quantization resolution of the input signals reduced.

The invention is illustrated below using exemplary embodiments explained in more detail with reference to drawings.

Figures 1 and 5 show in block form the scheme of digital signal processing circuit arrangements according to the invention;
20th

Diguren 2 and 3 show in graphical representations the relationships between signals and parameters in the Arrangements according to Figures 1 and 5;

Figures 4, 6 and 7 are circuit diagrams of certain parts of the Arrangements according to Figures 1 and 5

In the drawings, the arrows with small slashes symbolize signal paths for digital signals, which consist of several parallel bits. The numbers entered after the slashes indicate the number of the parallel bits.

A digital signal consisting of N bits can, as is known, represent 2 possible amounts or levels. The values of this digital signal can be organized in such a way that one of them corresponds to the amount 0, while the remaining 2 ^N -1

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Values for amounts other than O apply. In the event of of a "symmetrical" signal, the values can be organized in such a way that they correspond to a mean zero value, 2 ■ loading

N-1 have one polarity and 2 -1 magnitudes the opposite Correspond to polarity. For the present description, the digital Chrominance signals are of the medium zero variety, unless expressly stated otherwise. It is also assumed that the digital signals described here are symmetrical with respect to the zero value, so that for each polarity only 2 ~ -1 amounts actually are available for use (i.e. in the case of N = 8 there are actually only 127 positive and 127 negative amounts available Disposal). The organization of the amounts represented by the digital signals can also be different, and depending According to this organization, the ratio factor K used in the following can also assume other values. Further be mentions that the invention is generally applicable to any type of quantized signals (sample signals), of which digital signals are just one example.

Fig. 1 shows a digital signal processing circuit arrangement for a color television receiver, an analog one Composite video signal (composite video signal) AV is expressed in an A / D converter 10 into an expressed by 7 bits converted to digital video signal DV · The converter 10 requests the video signal AV with four times the Frequency of the color subcarrier signal, i.e. with ^ fqq = 4 · * 3 »58 MHz in the NTSC system, under the control of a Interrogation clock signal 4fg (j · The A / D converter 10 also receives a "dither" signal fjj / p »half its amplitude The value of the least significant bit (1/2 NWB) of the digital word corresponds to the apparent quantization resolution approximately that of an 8-bit A / D converter.

The signals 4fgQ and fjj / o are described further below Way derived. It should be mentioned that the digital signal processing with the frequency (or a

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Multiples of the frequency) of the interrogation signal 4f _{sö is} carried out, which is synchronized in terms of phase and frequency with the color subcarrier signal fg _0.

The digital video signal DV consisting of 7-bit words is applied to a digital comb filter 11 which is designed to generate digital luminance signals Y consisting of 8 bits and digital chrominance signals C consisting of 8 bits. The digital luminance signals Y are fed to a digital luminance processing device 12, which carries out various operations such as steepening the digital luminance signals and multiplying the digital luminance signals to adjust the contrast of the resulting image. The processing device 12 supplies processed luminance signals in the form of 8-bit digital words, which are converted in a D / A converter 44 into corresponding analog luminance signals Y ¹ .

The 7-bit digital video signals DV are also applied to a digital deflection processor 14 which derives the various horizontal and vertical control signals and sync signals required for signal processing, deflection and image display. In detail, the device 14 generates the dither signal Fj ₁ Z ₂ ^m ^ of ^the horizontal line frequency, ie the signal Fjj / p ^ ^s ^ over one horizontal line "high" and over the next horizontal line "low". The device 14 also develops the color strobe pulse OfcP which is "low" (ie, effective) each time during the appearance of the color burst. This color burst is known to be a reference oscillation pulse of the color subcarrier frequency which is transmitted during the horizontal blanking intervals of the video signal.

The digital chrominance signals G are applied to a digital chrominance bandpass filter 16 which, for example, only approximates signals

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_ _'14 : "■! 1: 31758

the color subcarrier frequency f _SCJ passes. Since this filter contains several accumulators (adders), it generates a filtered chrominance signal consisting of 14-bit words on the output side and has a peak gain of approximately 64.

The filtered digital chrominance signals from the filter 16 are fed to a digital circuit 18 for automatic chrominance control (ACR), in which they are brought to a normalized amount. The AOR unit 18 effects one Attenuation by a factor of at least 2 and shortens the digital chrominance signals to 8 bits. The normalization of the amount these 8-bit digital signals from the output of the AOR circuit 18 happens through a negative feedback loop that a burst sensor and comparator 20 contains. The burst button probes under the control of the OKP color button 20 from the color burst in the digital chrominance signal at the output of the AOR circuit 18. The sampled values are compared with a reference value, e.g. the desired amount of the color burst and the digital peak values which can be accepted by the digital chrominance signal processing means. as As a result of this comparison, the burst sensor and comparator 20 supplies a gain control signal to the ACR circuit 18, in order to set their gain factor (more precisely their attenuation) so that the amount of the color burst gets the normalized value. This damping setting is then maintained by the magnitude of the chrominance signals supplied by the ACR circuit 18 adjust. About out-of-range values of the (R-Y) digital signals to avoid which have a higher magnitude than the (B-Y) digital signals, the maximum range of the (R-Y) digital signals becomes normalized to a level less than the equivalent of -127 digital values. From below Reasons to be described below are assumed to be about $ 85, which corresponds approximately to ^ 10.8 digital values.

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A digital chrominance demodulator 22 decomposes the normalized digital delivered at the output of the ACR circuit 18 Chroma signals in mutually perpendicular components (R-Y) and (B-Y). Because these components simply are alternate copies in the sequence of the chrominance digital words, the demodulator 22 can be a simple demultiplexer and contain a low-pass filter.

The components (RY) and (BY) of the color burst, each consisting of 8-bit digital words, are phase-compared under control of the color strobe pulses OKP in a phase comparison and filter circuit 24- with the fgß clock signal having the color subcarrier frequency. The circuit 24- generates a signal which is representative of the phase error between the actual phase of the fgß clock signal and the desired phase that this signal should have relative to the color burst. The phase comparison and filter circuit 24 also filters this error signal and applies it to the clock generator 26, which contains a voltage-controlled oscillator which oscillates at the frequency 4-f qq. The frequency of this oscillator is adjusted so that it is exactly four times the frequency of the color subcarrier and is phase-synchronized with it. The clock generator 26 further includes a digital frequency divider _{to divide the interrogation frequency 4fg G} by 2 and by 4 · and thereby generate the clock signal 2fgQ and the clock signal fg _C.

The demodulated (R-Y) color component appearing in the form of 8-bit digital words from the output of the demodulator 22 includes only the middle £ 108 values of the possible ii27 Values of an 8-bit signal. The demodulated (B-Y) component includes (4-3 * 9 / 61.4) x 108 = 77.2 values, of which -77 values are actually delivered. For the reasons mentioned above, it is particularly advantageous to use the To increase the number of values encompassed by the (B-Y) component. The digital values transmitted by the (B-Y) component uro-

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Ί correspond to the mean ^ 77 values and the Zero value.

A digital phase rotation circuit that rotates around a fixed phase dimension 70 receives the digital chrominance components (R-Y) and (B-Y) from demodulator 22 and develops therefrom modified digital chrominance components C1 and 02. The Components 01 and 02 are in phase quadrature to one another like components (R-Y) and (B-Y) and are opposite to these latter components by a predetermined amount Phase angle cc rotated according to the following transformation equations:

01 = (R-Y) K cosoo. - (B-Y) K sin / χ (1) and

02 = (R-Y) K sin * + (B-Y) K cos oC (2)

where K is a gain scale factor.

FIG. 2 shows the pointers (phase vectors or "phasors") of the chrominance components (RY) and (BY) and the rotated chrominance components 01 and 02. The criteria for the choice of the angle oC and the scale factor K are explained below. It is important to note that the phases of C1 and 02 do not correspond to the phases of any of the conventional chrominance components such as components I, Q or components (RY), (BY) or components Q, V (in the PAL system) although such a correspondence is not necessarily excluded.

4- shows an exemplary embodiment for the digital phase shift circuit 70 using read-only memories (ROM memories). The digital chrominance components (RY) and (BY) are alternately passed on to one another for addressing the two read-only memories 82 and 84 by means of a multiplexer 80 under the control of the clock signal 4-fg _G. The read-only memory 82 contains 256 7-bit

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Storage locations, each of which stores a digital word which stores the product of its address, the gain factor K and the sine of the angle oC. Read only memory 84 similarly contains 256 7-bit memory locations, each of which stores a digital representation of the product of its address, the gain factor K and the cosine of the angle -oC. The read-only memory 82 is activated to deliver output signals when the clock signal 2fg _{C has} the binary value (logic value) "0" (as indicated by the circle at the activation input EN of the memory 82), and the read-only memory 84 is activated to deliver output signals when the clock signal 2f _{ß0 has} the binary value "1".

.15 I ⁿ a 4 periods of the clock signal 4FG _C continuous portion of the operation processed first, the read only memory 84, a (RY) -Adressenwort and then a (BY) -Adressenwort, and then 82 processes the read-only memory (RY) -Adressenwort and then a (BY) address word so that the 4 terms of equations (1) and (2) above are applied to the input of demultiplexer latches 86 in a predetermined order. The demultiplexer latches 86 decode the clock signals 2fg _C and 4f _S q in order to store the 4 mentioned terms in 4 digital memories, which are then applied to a subtracting circuit 88 and an adding circuit 90, respectively, in order to add the modified chrominance components C1 and C2 according to the above Form equations (1) and (2).

.

Referring to Fig. 1, the digital phase rotation circuit 70 described above is followed by a digital hue control circuit 72, which depend on the phase angle of the modified chrominance components C1 and 02 in a controllable manner shifted by a control signal FT. The control range of circuit 72 is from 0 to about -50 degrees. The control signal FT can be set by the user to provide an additional

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to cause positive or negative phase rotation and thereby shift the hue of the displayed image more towards red colors or more towards green colors, as the user likes. The result are samples of chrominance components C1 _T and C2 _m , each of which has been rotated in phase by an angle of ad ^ 50 ° with respect to the chrominance components (RY) and (BY) by the action of the circuits 70 and 72.

A digital circuit 40 combines the components 01 ™ and C2 _T in multiplex under the control of the clock signal fg _C. The digital circuit 40 also performs a multiplication to adjust the color saturation, which can be done, for example, by means of a single digital multiplier circuit that is operated in multiplex to adjust the amounts of both components C1 _T and 02 ™ according to a saturation control signal SAT that the user can be changed at will in order to make the displayed colors appear more or less vivid. The multiplex signal, which contains the modified chrominance components 01 ™ and 02 ™ combined, is applied to a chrominance demultiplexer 42. In this multiplex signal, the two 7-bit digital words, which represent the chrominance components 01 ™ and 02m after modification according to the saturation control variable SAT (14 bits in total), are transmitted sequentially in the course of one period of the clock signal fg ^, the 4 periods of the interrogation clock signal 4fg ₀ contains. This means that the digital words 01 ™ and 02 ™ are transmitted in the form of 4 parallel bit groups, with 2 groups each containing 3 bits and 2 groups each containing 4 bits and the bits appearing sequentially within the groups. This is advantageous in the event that the multiplexer / multiplier 40 and the demultiplexer 42 form two separate integrated circuits, because the number of circuit connections required can then be reduced from 12 to 4. Furthermore, the type of transmission described is consistent with the data speed

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-j capabilities of the chrominance components that are processed in the band filter 16 and in the ACR circuit 18 with the interrogation _{clock frequency 4f g} Q and then with the clock signal frequency fg ^.

The chrominance demultiplexer 42 receives the two 3-bit groups and the two 4-bit groups in order to again form the 7-bit digital words of the chrominance components 01 ^ and 02 ™ under the control of the clock signal fgß. These digital words are then converted in associated D / A converters 46 and 48 into analog chrominance components C1 'and C2 ¹ .

An analog RGB matrix circuit 50 receives the analog luminance signal X ¹ and the analog chrominance components 01 'and 02' in order to derive the analog drive signals R, G and B for the colors red, green and blue. A conventional RGB matrix circuit, as is customary for processing the chrominance components (RY) and (BY), would generate color control signals with which the colors in a television picture η i t were correctly reproduced, namely because of the in the circuit 70 caused phase rotation. The matrix circuit 50 is therefore modified compared to the conventional embodiments in order to compensate for the imbalance in the drive signals that would otherwise result from the aforementioned phase rotation.

The analog RGB matrixing circuit 50 transforms the luminance signal Y ¹ and the modified chrominance components 01? and C2 ¹ in color control signals R, G and B according to the following equations:

R = Y ' + R _Λ σι ¹ + R ₂ 02 ' (3) G = Y ' "4 * G /, σι ¹ + ^G 2 02 ' (Ό B = Y ' ■ f "Jd _Λ σι ' + B ₂ 02 ' (5)

Here are the values of the coefficients R ₁ , R ₂ , G ₁ ,

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B. and Bp by the standards of the NTSO system and by the Phase rotation angle oc determined. It should be noted that the values These coefficients also have to take into account the special phosphors of the picture tube on which the pictures be reproduced. If, for example, phosphors are used, such as those contained in the picture tubes of the ROA Corporation then components (B-Y) and (R-Y) become 90 or -104 IRE units restored instead of 89 or 70 IRE units, as is the case with the NTSO standard phosphors is required. In the! Ig. 3 are as an example the values of the coefficients B,. and Bp as a function of the phase rotation angle 06 is shown.

The angle oC is chosen so that the quantization jumps in the blue signal B are smaller than when this signal is developed from the chrominance components (RY) and (BY). There are various criteria for a choice of the angle oc which leads to satisfactory improvements. Two of these criteria are described below as examples.

A first criterion is that the angle <= £. to be chosen so that the matrix coefficients are as small as possible. An angle suitable for this can be determined, for example, by calculating the values of all 6 coefficients for various angles eC between 0 and 360 ° and checking the results in order to select the angle which leads to the smallest coefficient. This test is easy to perform by determining which of the coefficient pairs R ^, R ₂ or G ^ ·, Gp or B ^, B _{2 has} the largest possible value, and then determining the smallest value for both coefficients in the pair. When using phosphors from the RCA Corporation, this criterion is met if the coefficients B ^ and B _{2 have} the same amount, which is the case for cc ^ -4-7 °, 137 ⁰ , 227 ° or 317 °, as is the case the vertical dashed lines in FIG. 3 show. It should be mentioned that these angles are equal to 47 ° plus an integral multiple of 90 ° angle steps.

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It is not important which of the four possible phase rotation angles is used because they all lead to equivalent results.

A second criterion is cc to select the angle so that the ^M aximalbeträge that the chrominance components may have C1 and 02 are substantially equal, so that the dynamic range is utilized most efficiently, the maximum number ie of digital values of the range used will. This criterion is fulfilled for 131 °,

221 ° or 311 ° as it is the vertical

dash-dotted lines in Fig. 3 show. Here too it is unimportant which of the four angles is selected.

The values of the matrix coefficients and the values of the quantization resolution are listed in Table I for the angles Ov = 41 ° and OL = 47 °. Suitable values for the amplification scale factor K ^, which was explained above in connection with FIG 70 following part of the arrangement can be adopted.

TABLE I. value = 41 ° 0.828. = 47 ° 0.873 0.787 IRE units
per quantisie
leap coefficient O ₇ 686 -0.202 1.31 -0.227 IRE units value
per quantisie
leap -0.316 1.25 R ₂ -0.288 1.40 -0.971 0.32 -0.850 1.09 0.977 0.50 G ₂ 1.034 0.36 1.48 1.54 1.52 0.46 1.55 ^B 2 1.35 - K 1.66 -

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The values given in Table I for the gain scale factor K ensure that with standard color saturation settings, approximately 85 # of the available Amplitude range are used, so that still about $ 15 as a reserve for those users who remain highly saturated Prefer (intensely colorful) pictures.

FIG. 5 shows a signal processing arrangement which is a modification of the arrangement according to FIG. It is different in FIG. 5 that the digital comb filter 11 is missing. The digital luminance processing device 12 'according to FIG. 5 differs from the device 12 according to FIG. in that it contains a luminance filter which suppresses the chrominance signals in order to produce the digital To deliver luminance signal Y. The digital chrominance bandpass filter 16 of FIG. 5 suppresses luminance signals by in this way to supply the digital 0 chrominance signals.

The demodulated by the digital chrominance demodulator 22 (R-Y) component undergoes low-pass filtering in one. digital (R-Y) comb filter 28 which provides a filtered (R-Y) signal. The demodulated by the demodulator 22 The (B-Y) component is also low-pass filtered in a digital (B-Y) comb filter 30 which provides a filtered (B-Y) signal.

The digital comb filters 28 and 30 are, for example, relatively simple comb filters of the type shown in FIG. The input signals to be filtered are applied to an input of a digital adding circuit 62 and to the input of a 1H delay device 60. The delay device 60 is, for example, a dynamic memory with random access (random memory RAM), which works as a silo register or chronology memory (FIFO type) and causes a delay equal to a horizontal line period (1H) by cyclically generating 227 addresses _{under control of the clock signal fg 0} delivers (with the NTSC system). That delayed

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Signal from the delay device 60 is on the second input of the adder circuit 62 given that a 7-bit sum signal generated. ■

The arrangement according to Pig. 5 contains a digital circuit 40 'which fulfills the punctures of a multiplication influencing the saturation, a hue control and a multiplexer. The circuit 40 'differs from the circuit 40 according to Pig. 1 in that it causes a phase rotation of the chrominance components (RY) and (BY). This phase rotation includes, on the one hand, the rotation around the fixed Winkelet to transform the components (RY) and (BY) into the components C1 and C2, as described above, and, on the other hand, a controllable rotation through an angle (^ corresponding to the hue Control signal PT which can be adjusted by the user at will. In practice this is achieved in an economical manner in that the value of the hue control signal FT is added to the equivalent of the angle oc.

In addition, it is economical to combine the scale factors K and SAT so that only one multiplier circuit is required to perform both multiplications. The hue is controlled by rotating the components (RY) and (BY), which represent two mutually perpendicular vectors, by an angle (oc + ß). For this purpose, the circuit 40 'must multiply the digital components (BY) and (RY) by factors SAT cos (ou + β) and SAT sin (oc + p ») and then combine the products according to known algebraic sum-difference equations. If the signal amounts are to be modified by a single multiplier circuit, then the circuit 40 'must multiply with the factors K SAT cos (^ + ß), K SAT cos (06 + ß), K SAT sin (oc + ß) and K SAT carry out sin (oc + ß). Such a modification of the circuit 40 'requires the addition of two additional latches in order to store the two additional multiplication factors.

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The arrangement described here, in particular the A / D converter 10, the processing device 12 and 14-, the filters 16, 28 and 30, the AOR circuit 18, the burst scanner 20, the demodulator 22, the comparator 24, the clock generator 26 , the multiplier and multiplexer circuit 40, the demultiplexer 42 and the D / A converters 46 and 48 can be of the type contained in the integrated digital signal processing circuits for television receivers, which are manufactured by ITT Semiconductors, Intermetall, Freiburg, Germany and are described in the ITT semiconductor brochure "VLSI Digital TV System DIGIT 2000" from August 1982 · The present invention can be implemented in these integrated circuits, which contain a memory for storing control values, by means of simple interventions . For example, a fixed phase rotation angle oC can be introduced by taking the value corresponding to the predetermined angle oC for the stored value of the control signal FT, which corresponds to a zero degree phase rotation for the hue control. The gain dimensioning with the factor K is introduced by dimensioning the stored value of the control signal SAT or the nominal value of the ACR or both values to achieve the factor K ^- and using the available amount range economically. The analog RGB matrix circuit of the integrated circuits mentioned is then modified by changing the resistance values and by adding a resistor (for the coefficient B ^) so that the matrix coefficients of Table I are obtained. The easiest way to achieve this is to choose 06 = 227 °, because then the signs of the matrix coefficients (but not their values) remain unchanged if the output connections for the color control signals from R, G, B to B, R, G redesignated.

In addition to the exemplary embodiments described, other embodiments or modifications are also possible.

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For example, the area dimensioning carried out by the ACR circuit 18 can be combined with the dimensioning by the factors K and SAT and carried out by a single multiplier circuit 40 or 40 '. ■ The analog matrixing 50 7 illustrated digital, the digital luminance signals Y luminance processing means 12 and digital chrominance components C1 and C2 can be done by in Fig. RGB matrixing circuit 92 to be replaced, of which receives from the demultiplexer 42nd The RGB digital matrix circuit 92 uses digital multipliers and adders to function in accordance with equations (3) through (5). The digital matrix circuit 92 then supplies digital color signals which correspond to the signals R, G and B and which are applied to three D / A converters 94, 96 and 98 in order to develop the analog color drive signals R, G and B therefrom .

It should also be mentioned that the present invention can also be used in connection with chrominance demodulation devices which operate with chrominance components other than the components (RY) and (BY) described here. The invention is thus also suitable for demodulation devices in which the components I and Q or the components U and V are demodulated. The invention can also be used in a system in which the _{hue control takes place by modifying the phase of the interrogation clock signal 4fg G} with respect to the phase of the color burst.

Finally, it should be noted that the objects of the present invention can also be achieved when the chrominance components (R-Y) and (B-Y) can be rotated by different angles.

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Claims (13)

Claims M.JCircuit arrangement for signal processing with a Source for supplying a first and a second 10 signals, each of which has a predetermined phase position a reference phase and with a transformation means, coupled to the signal source, for passing through the first and second signals Phase rotation of these signals by a predetermined 15 phase angle to derive a third and a fourth signal, characterized by such Choice of the predetermined phase angle Gx) that the maximum amounts of the third (01) and fourth (C2) signals are more closely matched than the maximum 20 times the first (R-Y) and second (B-Y) signals, M MD AOIiR-ROO 1431756 2. Circuit arrangement according to claim 1, characterized in that the transformation device (70) has the following having: means (80, 82, 84, 86) for generating signals representative of the products of the first and the second signal each having the sine and cosine of the predetermined phase angle; a device (88, 90) which for generating the third and fourth signals predetermined copies of the Combined product signals. 3. Circuit arrangement according to claim 1, characterized by: a merging circuit (50) which is coupled to the transformation device (70) and the third (C1) and the fourth (C2) signal combined in predetermined proportions to form at least one output signal (R; G; B) to derive; a control device (72) interposed between the transformation device and the combining circuit is coupled to the phases of the third and fourth signals to rotate depending on a control signal (PT). 4. Circuit arrangement according to claim 1, characterized in that the transformation ^{device (40 1} ) contains a control input (FT) for receiving a control signal and a device to control the phases of the first (RY) and the second (BY) signal dependent to rotate from the control signal. 5 · Circuit arrangement according to Claim 1, characterized in that the first and second signals are digital signals which represent analog signals that are in phase quadrature with respect to one another. 6. Circuit arrangement according to claim 5, characterized by: digital-to-analog converter means (46, 48) coupled to the transformation means (70) to convert the third signal (01) into a third analog signal (01 ') and the fourth signal (02) into a fourth analog signal Convert (02 '); an analog matrix circuit (50) which is the third and the fourth analog signal combined in predetermined proportions to form at least one analog Derive output signal (Rj G; B). 7. Circuit arrangement according to claim 5 »marked by: a digital matrix circuit (92) which is coupled to the transformation device (70) and which third and fourth signals (01 and 02) in predetermined Proportions combined to derive first and second digital signals; a digital / analog converter (94, 96, 98) for converting the first and second digital signals into a variety of analog output signals (S, 6, B). . 8. Circuit arrangement according to claim 1, characterized in that in that it is contained in a television receiver comprising: means for supplying television signals; means (24, 26) for Erzeu- · supply of an interrogation signal ^(Zf -fg _{G) i} having a predetermined phase relationship with a color subcarrier reference oscillation in the color television signals; an analog-to-digital converter (10) which generates digital interrogation values (DV) of the color television signals under control of the interrogation signal; a processing device (11, 16, 18, 22) which extracts from the digital interrogation values a first (RY) and a second (BY) digitized chrominance component corresponding to the predetermined phase relationship of the interrogation signal; that the transformation device (70) with the _4- 3 * 31756 processing device (11, 16, 18, 22) is coupled, transformed by a first (01) and a second (02) to derive digitized chrominance components that lead to. first and second digitized chrominance components are related by rotating a predetermined phase angle; that with the transformation device a linking device (50) is coupled which the ers-cen and second transformieibaadigitalized chrominance components combined in predetermined proportions to generate a multitude of analog color control signals (R, G, B) to develop. 9. Circuit arrangement according to claim 8, characterized in that the linking device (50) has the following having: a digital to analog converter (46, 48). for converting the first and the second transformed digitized chrominance components (01 and 02) into first and second analog signals (01 * and 02 ¹ ); an analog matrix circuit (50) which the first and second analog signals in predetermined Proportions combined with each other to obtain the multitude of analog color control signals (R, G, B). 10. Circuit arrangement according to claim 8, characterized in that the linking device has the following having: a digital matrix circuit (92) which the first and second transformed digitized chrominance components (01 and 02) in predetermined proportions combined to produce first and second digital color control signals; digital to analog converting means (94, 96, 98) for converting the first and second digital Color control signal into the multitude of analog color control signals (R, G, B). _5_ 3 * 31756 11. Circuit arrangement according to claim 8, characterized in that that the transformation device (70) has the following: means (80, 82, 84, 86) for generating digital signals representative of the products the first and the second digitized chrominance component with the sine and the cosine of the are predetermined phase angle; means (88, 90) which predetermined copies of the digital product signals combined to transform the first and the second digitized To generate chrominance components (Ch and 02). 12. Circuit arrangement according to claim 8, characterized in that that between the transformation device (70) and the linking device (50) a color tone control device (72) is coupled, which controllably the phases of the two transformed digitized chrominance components (C1 and C2) rotates depending on a control signal (FT). 13. Circuit arrangement according to claim 8, characterized in that the transformation device (AO ') a control input (FT) for receiving a hue control signal and comprises means for transforming the phases of the first and second digitized chrominance component (G1 and 02) dependent to rotate from the control signal.