DE3431259C2 - - Google Patents

Description

The invention relates to a control circuit for a fluorescent display device according to the preamble of claim 1.

From DE-OS 24 49 543 a corresponding control circuit with the features of the preamble of claim 1, but for one Liquid crystal display device known, but line by line is controlled and in each case in a buffer, the display signals stored in a row and in parallel signals are implemented in a buffer get saved.

Fluorescent display devices designed in such a way that they allow that from a filiform cathode emitted electrons on a phosphor-coated anode have been encountered in large to enable an advertisement Scope for display systems in various types of electronic Devices and the like because of the appropriate color of the emitted light, the possibility of having a low Voltage to be controlled, the low energy consumption and the like. In a fluorescent display device, generally as a dot matrix display device several phosphor-coated anodes are known arranged in the form of a matrix and in rows with each other connected while control electrodes above the anodes these are arranged in columns and the Anodes at the intersection of each selected Row and column are arranged, optionally for lighting excited. The current diversity of information, through various electronic equipments generated requires a fluorescent display device at which the display points are arranged with a high density to get a high resolution display.  

To achieve the arrangement of high-density display points, two technical problems must be solved. The first problem is a display error on the edge of the anodes due to a deflection in the passage of the electrons from a cathode due to a negative electric field which is generated by control electrodes which one of the control electrodes opposite the respectively excited anode are neighboring. This is caused by the fact that the distance between two adjacent control electrodes with an anode arrangement with a high density becomes correspondingly narrow. Furthermore, such Fluorescent display device is generally dynamic Driver system used the number of external connections diminish in each anode and the control electrodes whose Number corresponds to the increased number of anodes to scan. Accordingly, the ratio of the selected period becomes one Control electrode to a sampling cycle, which is commonly called Working phase is known, smaller, which has the consequence that the Duration of a pulse to scan a control electrode very much becomes narrow and the brightness of the anodes is reduced. This is the second problem. To reduce the brightness compensate, it is necessary to increase the driver voltage, however, this diminishes the advantage of a fluorescent display device, that they operate at low voltage can be.

To overcome the aforementioned drawbacks of such a conventional fluorescent display device, the inventors have proposed a fluorescent display device as described in Japanese Patent Application No. 86785/1981, which will be described below in connection with FIG. 1.

Fig. 1 shows in the form of a circuit diagram an electrode connection in a fluorescence display device, which has already been proposed by the inventors and in which a fluorescence display area, which is generally identified by the reference numeral 1 , point-shaped anodes A (A ₁₁, -, A _mn ) has the number m × n , which are arranged in the form of a matrix with m rows and n columns. Two electrodes A are always connected to each other in each row. In particular, the anodes are A ₁₁, A ₁₄, A ₁₇, - which are arranged in a position which is defined by the row (3 N -2) with N -1, 2, 3,. . . n is expressed, where N is a positive integer, connected to each other by a first connecting line C ₁. In the same way, the anodes are A ₁₂, A ₁₅, A ₁₈, - which are arranged in a position defined by the row (3 N -1) with N -1, 2, 3,. . . n is expressed, where N is a positive integer, connected to each other by a second connecting line C ₂ and the anodes A ₁₃, A ₁₆, A ₁₉, -, which are arranged in positions by the row (3 N) with N -1, 2, 3,. . . n is expressed, where N is a positive integer, are connected to each other by a third connecting line C ₃.

About the anodes A grid-like control electrodes G (G ₁, G ₂, -, G _k ) with respect to the anodes A are stretched opposite and in a direction perpendicular to the connecting lines C ₁, C ₂ and C ₃ or along the rows of anodes A. arranged such that a control electrode G covers two columns of anodes A. In this way, the total number of control electrodes G is half the number of anode columns. Numeral 2 denotes an anode driver circuit which applies a display signal to the anodes A, and numeral 3 denotes a control electrode driver circuit which applies a scanning signal to the control electrodes G.

In the wiring of the fluorescent display device described above, the control electrode drive circuit 3 is used to simultaneously scan the two adjacent control electrodes G while shifting the selection of the control electrodes in sequential order. In detail, the two adjacent control electrodes G ₁ and G ₂, G ₂ and G ₃, -, and G _{k -1} and G _k are scanned one after the other. The control electrodes G ₁ and G _k at both ends can be controlled independently. Alternatively, these can also be controlled together in order to scan the anodes A in the first and nth columns. In synchronism with the scanning of the control electrodes G in this way, the anodes A , which lie opposite them and are arranged on the inside of the jointly controlled control electrodes G , are supplied with an indication signal from the anode driver circuit 2 in order to make the anodes A light up.

In the fluorescence display device constructed in this way, the anode A , as described above, is designed as a triple matrix. The result of this is that the number of anode lines is three times as large as in a fluorescence display device which is designed in the usual way in a matrix. However, this enables the number of control electrodes G on the scanning side to be reduced by half. It also allows the operating phase of the display (the length of time that an image cell emits light during the time to scan the image plane) to be twice as large as compared to the conventional matrix type fluorescent display device. This indicates that the anodes A can produce a display with double brightness, with an anode voltage with the same amplitude or a display with the same brightness can be achieved with a reduced anode voltage.

Furthermore, the fluorescent display device, which is provided with such an anode A in the form of a triple matrix, enables a high-quality display to be achieved without display errors occurring even if the distance between two adjacent anodes A is remarkably reduced, since the anode A is not influenced by an electric field of the control electrode G opposite it.

FIG. 2 shows an example of such a fluorescent display device in which the anodes A are arranged in eight rows or are arranged to form eight dots in the longitudinal direction and an example of an anode driver circuit which is suitable for displaying on the anodes A. ₁₂ and A ₁₃ to effect.

In Fig. 2, the control electrodes G ₁ and G ₂ are selected together by the control electrode circuit 3 and synchronously with this, a display signal for controlling the lighting of the anodes A ₁₂ and A ₁₃ is applied to the connecting lines C ₂ and C ₃, which with the anodes A ₁₂ and A ₁₃ are connected, which in turn are arranged in the columns within the control electrodes G ₁ and G ₂ opposite. The anodes A ₁₁ and A ₁₄, which are arranged on the outside of the control electrodes G ₁ and G ₂ opposite these, must remain unlit.

It is therefore necessary to apply a display signal to the connecting lines C ₂ and C ₃ and at the same time to apply a dark signal to the connecting line C ₁. In particular, it is necessary to simultaneously apply a control signal to the connecting lines C ₁, C ₂ and C ₃ in the corresponding rows. If a display on the anodes A of the eight points arranged in the longitudinal direction is to be achieved, it is necessary to simultaneously apply a signal with a total of 24 (8 × 3) bits from the anode driver circuit 2 to the fluorescence display area 1 . Now, assuming that a display signal is supplied serially from the anode driver circuit 2 to the fluorescence display area 1 , a display signal is first converted into a parallel signal by means of a shift register SR ₁ and then stored in a memory M ₁, which is known as a D- Flip-flop is formed and works as a locking circuit. The memory M ₁ is hereinafter referred to as "latch circuit".

Subsequently, a parallel signal, into which a display signal has been converted by means of the shift register SR ₂, is supplied to the latch circuit M ₂ and then a parallel signal generated in a similar manner by means of the shift register SR ₃ is supplied to the latch circuit M ₃.

However, in the fluorescent display device, it is required this process described above within a period perform during the the fluorescence display area performs no display, or within a display blanking period of the display area. So if the number the points in a column that are intended for display is, is large, it is practically impossible to get the signal to transmit during the display blanking period.

The present invention is based on the object Driver circuit for a fluorescent display device with which it is possible to display a signal during the display blanking period of a fluorescent display area even then easily and with great certainty, if the number of display points in a column is significantly increased. The driver circuit for the fluorescent display device should not be a long blanking period require to transmit the display signal.

This object is achieved by the characterizing Part of claim 1 specified features solved.  

The driver circuit is suitable either two adjacent control electrodes together to scan while selecting these control electrodes is successively shifted individually and a display signal to apply to the anodes of adjacent columns that opposite the selected two control electrodes. The Driver circuitry includes at least one first stage intermediate buffer, which is suitable, a display signal caching that subsequently within the display period the fluorescent display device and the saved display signal to the next stage during the next display blanking period of the fluorescent display device transmits and a second stage Buffer that is suitable for the display signal to receive that from the buffer forming the first stage is transmitted and the display signal to the anodes who creates gaps that are adjacent to those that are opposite both selected control electrodes.

An embodiment of the driver circuit according to the The invention is explained in more detail below with reference to drawings, corresponding parts by the same Reference numerals are marked.

It shows

Fig. 1 is a diagram showing an example of an electrode connection of a fluorescent display device, in which the anodes are arranged according to a three-fold matrix,

Fig. 2 is a circuit diagram of a conventional anode driver circuit,

Fig. 3 is a circuit diagram of an embodiment of a control circuit for a fluorescent display device according to the invention; and

FIG. 4 is a timing chart showing the display process of the control circuit shown in FIG. 3.

In the circuit diagram shown in FIG. 3, reference number 1 denotes the fluorescence display area which has essentially the same structure and the same mode of operation as that in FIGS. 1 and 2. Reference numeral 3 designates the control electrode driver circuit which operates such that it optionally scans two adjacent control electrodes G (e.g. G ₁ and G ₂ and G ₂ and G ₃) together, as well as those shown in FIGS. 1 and 2 are, while the selection of the control electrodes G is cyclically shifted by one unit.

An anode driver circuit 20 will now be described in more detail, assuming that the number of anodes A is eight or the anodes A are arranged in the form of eight dots in the longitudinal direction when they light up together.

The anode driver circuit 20 is designed such that it enables a display signal S having eight bits can be applied thereto in parallel from a display signal converter 18, which has received an indication signal S for an image sequence or a display signal S using a control signal , which is supplied to it by a control device, not shown. However, when a display signal S is supplied in series, a circuit is required to convert the signal into a parallel signal by means of a shift register, as shown in FIG. 2.

Specifically, a display signal S is summarized, each of the connecting lines C ₁, C ₂ and C ₃, each of which is to be supplied to a row of anodes A in the fluorescent display area 1 , and is supplied in the form of eight bits by the display signal converter 18 .

Accordingly, the driver circuit 20 includes a first stage latch 11 , 12 , 13, hereinafter referred to as "latch circuit", which in turn contains a latch 11 , hereinafter referred to as "latch" for latching a signal which is connected to the Connection line C ₁ each row of the fluorescent display area 1 is applied, a latch 12 for buffering a signal which is applied to the connecting line C ₂ each row and a latch 13 for latching a signal which is applied to the connecting lines C ₃ each row and a latch circuit forming a second stage, which contains the further latches 21 , 22 and 23 , to which the outputs of the latch circuit forming the first stage are connected.

The latch circuit forming the first stage is designed such that the latches 11 , 12 and 13 are operated with takeover signals E ₁₁, E ₁₂ and E ₁₃ in order to store the display signal present.

The latches 21 , 22 and 23 of the latch circuit forming the second stage can be operated by a simultaneously applied scanning signal E ₀ in order in this way to store the output signals of the latches 11 to 13 .

The latches 11, 12 and 13 have to delete clear inputs to which clear signals CL ₁, ₂ and CL CL ₃ tightly around the contents to 0, and to produce a dark signal for the fluorescent display area. 1

The reference numerals 31 , 32 and 33 denote drivers which are connected to the outputs of the latches 21 , 22 and 23 in order to drive the connecting lines C ₁, C ₂ and C ₃ for each row of anodes.

The reference numeral 19 denotes a display control, which serves the takeover signals E ₁₁, E ₁₂, E ₁₃ and E ₀ and the delete signals CL ₁, CL ₂ and CL ₃ and also a command for applying the display signal S for the display signal converter 18 and a Generate sampling timing control signal for the control electrode drive circuit 3 .

The operation of the control circuit, which is designed as described above, will now be described in connection with FIGS. 3 and 4.

First, the control electrode driver circuit 3 optionally touches the two adjacent control electrodes G together, while the selection of the control electrodes G is shifted one by one, as shown in the waveforms G ₁, G ₂, G ₃, - in Fig. 4 . In this example, the control electrode G ₁ is arranged in the first column on the left edge. Thus, it is scanned independently or together with a control electrode G _k , which is arranged on the right edge.

When the display signal from the display signal converter 18 to the connecting line C ₁ for each row is supplied to achieve a display on the anodes A (A ₁₁, A ₂₁, -, A _{m 1} ) in the first column of the fluorescent display area 1 , The takeover signal E ₁₁ from the display controller 19 to the latch 11 , as shown in Fig. 4 (E ₁₁), is applied to the control electrode G ₁ prior to the application of a scanning signal.

In this case, if the control electrode G _k , which is arranged on the right edge and is optionally controlled together with the control electrode G ₁, to achieve a display on the anode, which is arranged on the right edge and connected to the connecting line C ₃ is, the takeover signal E ₁₃ applied to the latch 13 , as shown in Fig. 4 (E ₁₃).

At the time when the anodes A in the first column are illuminated, it is necessary to keep the anodes A (A ₁₂, A ₂₂, -, A _{m 2} ) in a non-illuminated state. Accordingly, following the takeover signal E ₁₁, the clear signal CL ₂ is applied from the display controller 19 to the latch 12 to clear the latch contents of the latch to zero, as shown in Fig. 4 (CL ₂).

When the display blanking period ends and the control signal is applied to the control electrode G ₁, as shown in Fig. 4 (G ₁), the takeover signal E ₀ from the display controller 19 to the latches 21 , 22 and 23 simultaneously with the driven edge r ₁ of the control signal applied as shown in Fig. 4 (E ₀) to transmit the contents of the latches 11 , 12 and 13 at once.

The overall result is that the display signal to be applied to the column of anodes A ₁₁ to A _{m 1} opposite the selected control electrode G ₁, which are taken over by the latch 21 , and that a dark signal in the columns of Anodes A ₁₂ to A _{m 2 is} taken over, which are then applied by the drivers 31 and 32 to the connecting lines C ₁ and C ₂ of each column. This enables the activation of the anodes of the fluorescent display area 1 to be controlled, as shown in Fig. 4 (C ₁) to (C ₃).

The next display signal S is prepared in the latches 11 to 13 during the period T _{D 1 of} the display by the control electrode G ₁. This process is carried out in that first the memory content of the latch 11 is reset to 0 using the clear signal CL ₁, as shown in Fig. 4 (CL ₁) within the display period T _{D 1} , that in the latch 12 of the display signal S is stored, which is applied to the connecting line C ₂ for each row using the takeover signal E ₁₂, as shown in Fig. 4 (E ₁₂) and that finally the latch 13 using the takeover signal E ₁₃ back into a working state returns as shown in Fig. 4 (E ₁₃) to store the display signal S which is applied to the connecting line C ₃ for each row.

This storage process is carried out independently of the display period T _{D 1} . Thus, it does not affect the display process by the control electrode G ₁.

When the display period T _{D 1} ends, a display blanking period is provided, as represented by T _{B 1} to T _{B 3} in Fig. 4 (G ₁) to (G ₃), to overlap the display due to a delay in the decay period to prevent the drive signal of the control electrode G ₂ and / or the anodes A and then the control signal is simultaneously applied to the control electrodes G ₁ and G ₂, as shown in Figs. 4 (G ₁) and (G ₂) to obtain the anodes A ₁₂ to A _{m 2} and A ₁₃ to A _{M 3} in the second and third columns of the fluorescent display area 1 in the display state. At the same time, the takeover signal E ₀ is applied from the display controller 19 to the latches 21 to 23 in accordance with the rising edge r ₂ of the control signal as shown in Fig. 4 (E ₀) to transmit the signal which is in the Latches 11 to 13 is saved. This has the consequence that the connecting lines C ₁ to C ₃ are driven by the drivers 31 to 33 , as shown in Fig. 4 (C ₁) to (C ₃) to achieve a display.

During the period T _{D 2 of} the display by the control electrodes G ₁ and G ₂, the display signal S , which is sent to each of the connecting lines C ₁ and C ₂ during a period T _{D 3 of} the display by the simultaneous scanning of the next control electrodes G ₂ and G ₃ is created, prepared in the latches 11 to 13 using the scanning signals E ₁₁ and E ₁₂ and the delete signal CL ₃.

The above-described process is repeated cyclically in order to selectively drive the adjacent two control electrodes G of the fluorescent display area 1 together, while the selection of the control electrodes G is successively shifted by 1 and by the adjacent anode columns that connect the selected control electrodes G with the display signal supply and effect the display on the anodes A.

In this case, as described above, the display signal S which is subsequently displayed is prepared in advance during the display period in the latch circuit constituting the first stage, with the result that the transmission of the display signal S is carried out easily and smoothly becomes.

In particular, since the transmission of the display signal S applied from the display signal converter 18 need not be performed within the display blanking period, it is not necessary to extend the display blanking period necessary to transmit the data even if the number of bits of the display signal S is significantly increased. This enables a significant increase in the working phase in order to achieve greater brightness and a reduction in the anode voltage with constant brightness.

In the embodiment described above, the memory content of the latch circuit constituting the first stage is cleared to generate a zero signal when the dark signal is applied to the anode columns which are arranged outside of those which are arranged to the adjacent two control electrodes G , which are optionally scanned to prevent the anodes A from lighting up.

However, the generation of such a dark signal in the display signal converter 18 can be carried out by preparing beforehand a display signal S which has data which is always "0" and the data relating to the latches 11 to 13 of the latch forming the first stage -Circuit are transmitted, which are assigned to the connecting lines C ₁ to C ₃ to remain dark together with another display signal S.

As can be seen from the foregoing, the present invention is designed such that the anode driver circuit 20 has two latches of the front and rear stages so that the next display signal in the latch forming the first stage prepares during the display period of the fluorescent display device and the display signal in the first stage latch is transferred to the second stage latch during the next display blanking period of the fluorescent display device. Accordingly, the present invention has the advantage that no time is required to transmit the display signal at the time when the fluorescent display device is performing display, and thus the transmission of the display signal can be easily achieved even when the number of dots is one Display is very large. In other words, the display blanking period required to transmit the display signal is significantly shortened compared to the prior art, with the result that the working phase is considerably longer.

Claims (3)

1. Control circuit for a fluorescence display device with a multiplicity of phosphor-coated anodes, which are arranged in the form of a matrix with rows and columns, the anodes of each row being divided into three anode groups, each of which is electrically connected, the column number of which is determined by the row (3 N -2) to (3 N -1) or (3 N) with N = 1, 2,. . ., n is defined, where n is a positive integer, with a cathode arrangement from which electrons are emitted to the anodes, with a multiplicity of column-shaped control electrodes controlled by an associated driver circuit, one control electrode each in relation to a pair of two adjacent anode columns is arranged at a distance, and a buffer for display signals connected downstream of a display control, which feeds them to the corresponding anode rows, characterized in that the buffer ( 21 , 22 , 23 ) each has a further buffer ( 11 , 12 , 13 ) for storing the signal to be displayed at the next display period, which is fed to the buffer ( 21 , 22 , 23 ) during the next display exchange period, is connected upstream. 2. Control circuit according to claim 1, characterized in that the arrangement of the buffers ( 11 to 13 , 21 to 23 ) in a first buffer group ( 11 , 21 ) for temporarily storing the display signal (S) that the first group of anodes (A is supplied), to a second intermediate storage group (12, 22) for temporarily latching the indicating signal (S) which is the second group of anodes (a) is supplied, and in a third intermediate storage group (13, 23) for temporarily storing the display signal ( S) , which is fed to the third group of anodes (A) . 3. Control circuit according to claim 1, characterized in that the intermediate memories ( 21 , 22 , 23 ) are takeover memory circuits.