DE3426071C2 - Circuit arrangement for monitoring the initiation of a connection setup in a telecommunication terminal connected to a digital connection line - Google Patents
Circuit arrangement for monitoring the initiation of a connection setup in a telecommunication terminal connected to a digital connection lineInfo
- Publication number
- DE3426071C2 DE3426071C2 DE19843426071 DE3426071A DE3426071C2 DE 3426071 C2 DE3426071 C2 DE 3426071C2 DE 19843426071 DE19843426071 DE 19843426071 DE 3426071 A DE3426071 A DE 3426071A DE 3426071 C2 DE3426071 C2 DE 3426071C2
- Authority
- DE
- Germany
- Prior art keywords
- pulses
- pulse
- counter
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M19/00—Current supply arrangements for telephone systems
- H04M19/08—Current supply arrangements for telephone systems with current supply sources at the substations
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Die vorliegende Schaltungsanordnung besteht aus einem flankengesteuerten nachtriggerbaren Monoflop, das dem Zähleingang eines Zählers vorgeschaltet ist. Sein Zeitverhalten ist so dimensioniert, daß Impulse immer mit der vorgeschriebenen Länge dem Zähler zugeführt werden. Durch Störungen verursachte zu kurze Impulse werden dabei zu einem einzigen Impuls zusammengefaßt. Der Zähler wird durch einen Taktgeber vorzeitig zurückgesetzt, wenn beim Impulsempfang zu lange Lücken auftreten. Die Schaltungsanordnung liefert nur dann ein Ausgangssignal, wenn mehrmals eine vorgegebene Anzahl von Impulsen in jeweils einem vorgegebenen Zeitraum empfangen worden sind.The present circuit arrangement consists of an edge-controlled, retriggerable monoflop, which is connected upstream of the counting input of a counter. Its time response is dimensioned in such a way that pulses are always fed to the counter with the prescribed length. Impulse that is too short caused by interference is combined into a single impulse. The counter is prematurely reset by a clock if gaps occur that are too long when receiving pulses. The circuit arrangement only supplies an output signal if a predetermined number of pulses have been received several times in each case in a predetermined period of time.
Description
der Zähler Z in seine Ruhelage geschaltet, bevor er die vorgegebene Schaltstellung erreichen kann.the counter Z is switched to its rest position before he starts the can reach the specified switching position.
Trifft jedoch eine vorgegebene Anzahl von Impulsen in einem vom Taktgeber TC vorbestimmten Zeitraum ein, so erreicht der Zähler Z seine vorgegebene Schaltstellung und stellt das Flip-Flop FFl über seinen Setzeingang 5 in die Arbeitslage. Beim nächsten Impuls vom Taktgeber TG wird die Schaltstellung des Flip-Flops FFl in das nachgeschaltete nächste Flip-Flop FF2 übernommen. Danach wird das erste Flip-Fiop FFl und auch der Zähler Z wieder zurückgestellt Trifft nun erneut eine vorgegebene Anzahl von Belegungsimpulsen ein, so wird auch das erste Flip-Flop FFl erneut gesetzt Da nun aber bereits das zweite Flip-Flop FF2 gesetzt ist wird das Verknüpfungsgatter VG erfüllt, so daß am Dateneingang D des dritten Flip-Flops FF3 ein Signal erscheint das .mit dem nächsten Takt des Taktgebers TG an den Ausgang A gelangt Bei diesem Ausführungsbeispiel wird nur dann ein zur Inbetriebnahme des Fernmelde-Endgerätes geeignetes Signal A gebildet, wenn mindestens zweimal eine vorgegebene Anzahl von Impulsen als Belegungssignal jeweils innerhalb eines vorgegebenen Zeitraumes empfangen wird. Damit ist bereits eine sehr große Sicherheit gegenüber durch Störungen verursachten Fehlbelegungen gegeben. Durch Zwischenschaltung weiterer Flip-Flops oder eines Zählers kann natürlich die Sicherheit weiter erhöht werden, jedoch ergeben sich dann auch längere Reaktionszeiten beim Empfangen von echten Belegungsinformationen.If, however, a predetermined number of pulses arrive in a period predetermined by the clock TC , the counter Z reaches its predetermined switching position and sets the flip-flop FF1 to the working position via its set input 5. With the next pulse from the clock generator TG , the switch position of the flip-flop FFl is transferred to the next downstream flip-flop FF2. The first flip-flop FFl and also the counter Z are then reset logic gate VG satisfied so that the third flip-flop FF3, a signal appears at the data input D of the .with the next clock of the clock generator TG to the output a arrives in this embodiment is only an appropriate commissioning of the telecommunications terminal signal a is formed, if a predetermined number of pulses is received as an occupancy signal at least twice within a predetermined period of time. This already provides a very high level of security against incorrect assignments caused by faults. By interposing further flip-flops or a counter, the security can of course be further increased, but then longer reaction times result when receiving real occupancy information.
Hierzu 1 Blatt Zeichnungen1 sheet of drawings
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Claims (1)
dadurch gekennzeichnet, 15 Wenn aber Störungen auftreten, wobei Impulse ent-Circuit arrangement for monitoring the input signal sequence is fed in parallel. A connection establishment with a telecommunication-supplying flip-flop connected to a 5, the switch-on signal for the power supply digital connection line only responds if a pre-end device, whereby on the connection line ankom- given number of occupancy pulses within eimende signals is determined and evaluated, ner time period is received, which is determined by the nachtrigdie, when correctly recognized, to start up the gabel timer or monoflop. Telecommunication terminal lead, whereby it depends on 10 malfunctions are only excluded if the digital pulses arrive in the correct length, the pauses between the individual pulses too large and correct number, with the arriving, with the monoflop before When the given pulse is reached, the counter reading recorded by a pulse shaper returns to its rest position and is taken, which is connected upstream of a counter, thereby resetting the counter or a shift register
characterized by 15 If, however, faults occur, whereby pulses
entsprechen, daß der Ausgang des Monoflops (MF) 20 Aus der DE-OS 23 03 582, wo ein Codeempfänger in mit dem Zähleingang eines Zählers (Z) verbunden einer Personenrufanlage beschrieben wird, ist es beist, wovon ein Zählausgang mit dem Setzeingang (S) kannt, einen Impulsformer vorzusehen, der Ausgangseines ersten bistabilen Flip-Flops (FFi) verbunden impulse konstanter Länge auch dann liefert wenn mehist, so daß dieses in seine Arbeitslage gerät, wenn rere kürzere Impulse empfangen werden. Diesem Imeine vorbestimmte Anzahl von Signalimpulsen emp- 25 pulsformer ist ein Zähler zur weitergehenden Impulsfangen worden ist, Verlängerung nachgeschaltet Dieser Zähler wird durch daß der Rücksetzeingang (R) des ersten bistabilen einen Taktgeber weitergeschaltet und jeweils von ei-Flip-Flops (FF 1) mit dem Ausgang eines Taktgebers nem empf&ngenen Impuls zurückgesetzt. Es wird damit (TG) verbunden ist der in zeitgleichen Abständen eine zeitliche Überwachung jedes einlaufenden Signaldieses Flip-Flop (FFX) und auch den Zähler (Z) zu- 30 impulses erreicht und von einem weiteren Impulszeitrücksetzt, überwacher festgestellt, ob ein überlanger Startimpuls daß mindestens ein weiteres bistabiles Flip-Flop angekommen ist Bei dem in der DE-OS 23 03 582 be- (FF2)mit dem Ausgang des ersten Flip-Flops (FFi) schriebenen Codeempfänger wird das Erkennen eines verbunden ist und von diesem so voreingestellt wird, Startsignals nicht von einer vorbestimmten Anzahl von daß es beim Rücksetzen des ersten Flip-Flops (FFi) 35 Impulsen sondern lediglich von der vorgegebenen Länin seine Arbeitsstellung gerät ge eines einzigen Startimpulses abhängig gemacht,
daß die Eingänge mindestens eines UND-Verknüp- Die Aufgabe der vorliegenden Erfindung besteht darfungsgliedes (VG) mit den Ausgängen der besagten in, eine Schaltungsanordnung anzugeben, die das fälsch-Flip-Flops (FF \ und FF2) so verbunden sind, daß an liehe Erkennen einer Belegung auch dann ausschließt, seinem Ausgang ein Signalwechsel stattfindet wenn 40 wenn durch Störungen verursachte Impulse von kurzer der Zähler (Z) zum wiederholten Male das erste Dauer oder in zu schneller Folge eintreffen. Die Lösung Flip-Flop (FFi) in seine Arbeitslage bringt, dieser Aufgabe erfolgt durch eine Merkmalskombinadaß der Ausgang des UND-Verknüpfungsgliedes tion, wie sie im Patentanspruch angegeben ist.
(VG) mit einem Eingang eines dritten Flip-Flops Damit wird in vorteilhafter Weise erreicht, daß eine (FF3) verbunden ist, und 45 erhöhte Sicherheit gegen Fehlbelegungen dadurch gedaß dann mit einem Impuls des Taktgebers (TG) das geben ist, daß eine echte Belegung erst dann erkannt dritte Flip-Flop (FF3) eingeschaltet wird, welches an wird, wenn die richtige Signalfolge mehrmals hintereinseinem Ausgang (A) ein Signal zur Inbetriebnahme ander empfangen worden ist.that a retriggerable mono stand as a pulse shaper is used in a shorter sequence than with a real flop (MF) , whose time behavior is the occupancy signal, so a counter can still be set so that the output pulses can be reached in their lerstand an incorrect switch-on length results in the standardized pulse durations of real signals from the power supply
correspond to the fact that the output of the monoflop (MF) 20 from DE-OS 23 03 582, where a code receiver is described in a paging system connected to the counting input of a counter (Z) , it is a part of which a counting output is connected to the set input (p ) knows to provide a pulse shaper that delivers the output of a first bistable flip-flop (FFi) connected pulses of constant length even if more, so that this comes into its working position when rer shorter pulses are received. Is this Imeine predetermined number of signal pulses EMP 25 pulse shaper is a counter for further pulse catch been extension downstream of this meter is that the reset input (R) of the first bistable further connected a clock and each of egg-flip-flop (FF 1) with the output of a clock is reset with a received pulse. It is connected to it (TG) that a temporal monitoring of every incoming signal of this flip-flop (FFX) and also the counter (Z) is reached at the same time and is reset by a further pulse time, a monitor determines whether an excessively long start pulse that At least one other bistable flip-flop has arrived In the case of the code receiver written in DE-OS 23 03 582 (FF2) with the output of the first flip-flop (FFi), the detection of one is connected and is preset by this, The start signal does not depend on a predetermined number of 35 pulses when the first flip-flop (FFi) is reset, but only on the given length of its working position.
that the inputs of at least one AND link- The object of the present invention is allowed member (VG) with the outputs of said in to specify a circuit arrangement that the fake flip-flops (FF \ and FF2) are connected to borrow Detection of an occupancy also excludes a signal change at its output if the counter (Z) repeatedly receives the first duration or in too fast a sequence if impulses caused by disturbances are short of short. The solution brings flip-flop (FFi) into its working position, this task is carried out by a combination of features of the output of the AND logic element, as specified in the claim.
(VG) with an input of a third flip-flop This advantageously ensures that a (FF3) is connected, and 45 increased security against incorrect assignments because a pulse from the clock (TG) then gives a real one Occupancy is only recognized when the third flip-flop (FF3) is switched on, which is switched on when the correct signal sequence has been received several times behind its output (A), a signal for commissioning has been received.
und richtiger Anzahl eintreffen. Es ist außerdem ein Taktgeber TG vorgesehen, derThe invention relates to a circuit arrangement for the downstream counter Z, a pulse is supplied to monitor the initiation of a connection set-up 55, which has the length of a real pulse. If, when connected to a digital connection line, impulses appear at input E , the signal end of the telecommunication terminal device, which is shorter than the standardized device as a result of a disturbance, is detected and evaluated, then these become a single impulse which, if recognized correctly, are taken into operation, so that the counter Z does not have the switch position me of the telecommunication terminal, whereupon it can reach 60, which it comes across when it receives a real notification, that the? digital l! ii "u! s p in right ^ ir Lan"? (T Uü tF s - !! n n u! Ss p ri p p.rr? Ichpn would,
and the correct number arrive. There is also a clock TG is provided that
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19843426071 DE3426071C2 (en) | 1984-07-14 | 1984-07-14 | Circuit arrangement for monitoring the initiation of a connection setup in a telecommunication terminal connected to a digital connection line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19843426071 DE3426071C2 (en) | 1984-07-14 | 1984-07-14 | Circuit arrangement for monitoring the initiation of a connection setup in a telecommunication terminal connected to a digital connection line |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3426071A1 DE3426071A1 (en) | 1986-01-23 |
DE3426071C2 true DE3426071C2 (en) | 1986-11-27 |
Family
ID=6240698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19843426071 Expired DE3426071C2 (en) | 1984-07-14 | 1984-07-14 | Circuit arrangement for monitoring the initiation of a connection setup in a telecommunication terminal connected to a digital connection line |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE3426071C2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2021519A6 (en) | 1990-04-19 | 1991-11-01 | Telefonica Nacional Espana Co | Modular public telephones management system. |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE365681B (en) * | 1972-02-09 | 1974-03-25 | Ericsson Telefon Ab L M | |
SE384115B (en) * | 1973-11-22 | 1976-04-12 | Ericsson Telefon Ab L M | DEVICE FOR VERIFYING THAT A RECEIVED SIGNAL CONTAINS A CERTAIN PULSE Sample |
DE2940617C2 (en) * | 1979-10-06 | 1982-08-12 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Circuit arrangement for initiating a connection setup in a telecommunications system |
-
1984
- 1984-07-14 DE DE19843426071 patent/DE3426071C2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE3426071A1 (en) | 1986-01-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: TELENORMA TELEFONBAU UND NORMALZEIT GMBH, 6000 FRA |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: TELENORMA GMBH, 6000 FRANKFURT, DE |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: ROBERT BOSCH GMBH, 70469 STUTTGART, DE |
|
8339 | Ceased/non-payment of the annual fee |