DE3417825A1 - Circuit arrangement for monitoring a program sequence in a microprocessor - Google Patents

Abstract

In the case of the circuit arrangement according to the invention, a reset input (R) of the microprocessor (1) is connected to one output of a first time element (2), and a reset input of the first time element (2) is connected to an output (P1) of the microprocessor (1). The delay time of the first time element (2) is longer than the undisturbed program delay time. Whenever the program is run, a test signal is emitted at the output (P1) of the microprocessor (1). The first time element (2) is reset and started again whenever a test signal occurs. In its initial state, the microprocessor is reset when the first time element (2) elapses. In consequence, the microprocessor can start the program sequence from the start again if it has been blocked in the meantime by an interference pulse. <IMAGE>

Description

Circuit arrangement for monitoring a

Program flow in a microprocessor The invention relates to a Circuit arrangement for monitoring a program sequence in a microprocessor.

In devices with microprocessors it can happen that, for example a program is interrupted by a glitch, d. H. not processed properly will. The microprocessor may then block itself, i. H. he is taking care of no more tasks at all. To prevent this, there is a program monitoring necessary that the microprocessor, especially its program counter, to a resets the defined start address. In known monitoring procedures takes place this with the software routines built into the program. However, there are disturbances possible, which also make these monitoring routines ineffective.

The object of the invention is therefore to provide a circuit arrangement for monitoring of the program sequence in such a way that it is largely independent of the microprocessor himself works.

This object is achieved according to the invention in that a reset input of the microprocessor with an output of a first timer and a reset input of the first timer is connected to an output of the microprocessor that the The runtime of the first timer is longer than the undisturbed program runtime that at the output of the microprocessor with each program run a test signal is output that the first timer each time a test signal occurs reset and restart and that the microprocessor is in its initial state is reset when the first timer expires. The error criterion is evaluated that the microprocessor within a predetermined time a certain Program step in which the test signal is output not reached. Through the combined solution of hardware and software is achieved that in particular errors, which, for example, lead to a complete blocking of a program sequence Security can be recognized.

The first timing element can be easily operated with an astable multivibrator be implemented, which is reset when the supply voltage is switched on.

In a circuit arrangement in which the microprocessor increases when its supply voltage by a supply voltage with a limit value comparative comparator and a downstream second timer released with a delay and is reset when its supply voltage drops below a limit value, can advantageously the comparator and the first timing element on the output side via a conjunctive link and via the second timing element with the reset input of the microprocessor. This allows the program monitoring and the Supply voltage monitoring for the microprocessor combined with little effort will.

The second timing element can be implemented particularly simply as an RC element its resistance is bridged with a diode so that the microprocessor is reset immediately as soon as the supply voltage falls below its limit value falls or the first timer expires.

In an advantageous embodiment, the first timing element can be be controlled by a clock counter that when the supply voltage is switched on or is set to a first count by the test signal and the at Reaching a second count the microprocessor in its initial state resets. The use of a counter as a timing element is particularly advantageous when if a clock is already present in the circuit.

In a circuit arrangement in which the microprocessor increases when its supply voltage by a supply voltage with a limit value comparing comparator and a delayed timer downstream of this released , two counters can be connected in series, whereby the clock input of the first counter with a clock, the reset input of the first counter with the Output of the microprocessor, the blocking input of the first counter with the comparator, the reset input of the second counter also with the comparator and the output of the second counter are connected to the reset input of the microprocessor. This enables the functions of supply voltage monitoring and program monitoring combined using counters.

Advantageously, between the output of the microprocessor and a differentiator inserted into the first timing element. Since the program monitoring thus only responds to a signal change, this prevents a signal at this output The pending fault signal of the microprocessor blocks the function of the circuit.

The invention is explained below with reference to two, in FIGS. 1 and 3 Exemplary embodiments shown and a diagram shown in FIG. 2 explained in more detail.

Fig. 1 shows a first embodiment in the form of a simplified circuit diagram, in which program monitoring and supply voltage monitoring are combined are.

The one required for the microprocessor 1 and the other modules The power supply is only shown schematically in FIG. 1. From a voltage source U, a charging capacitor 11 is charged via a charging resistor 10. On the charging capacitor 11 is the smoothed but unregulated supply voltage Uv. With a Fixed voltage regulator 12 becomes a regulated supply voltage Uv 'for the Microprocessor 1 and the other components are formed. The smoothed supply voltage Uv is compared with a comparator 4 with a voltage setpoint U5. The exit of the comparator 4 is connected to an input of an AND gate 5. The exit the AND gate 5 is via an RC element 3 with the series connection of a resistor 3a and a capacitor 3b connected to the reference potential. The resistor 3a is bridged with a diode 3c, the cathode of the diode 3c being the AND gate 5 faces. The connection point of resistor 3a and capacitor 3b is with a reset input R of the microprocessor 1 connected.

A differentiating element 6 is an output P1 of the microprocessor 1 downstream, which consists of a capacitor 6a and a resistor 6b. Of the The connection point of capacitor 6a and resistor 6b is with a reset input of an astable multivibra- tor 2 connected, its reset output is connected to a second input of the AND gate 5. The astable multivibrator is designed so that it is in the reset position when it is switched on.

The program of the microprocessor 1 is designed so that in the frame of the normal workflow or as a separate test step at output Pl in regular A test signal is issued at intervals, provided the program is running normally. the Tilting time of the multivibrator 2 in the set state is greater than the time between two test signals at output Pl.

The function of the circuit according to FIG. 1 is described below with reference to the Diagram of Fig. 2 explained. Fig.2 shows the time course of the smoothed Supply voltage Uv and the regulated supply voltage U when switching on and off the voltage source U. When switching on, the charging capacitor 11 is charged. In order to avoid errors, the program sequence of the microprocessor 1 must first be released when the microprocessor has been powered up for sufficient time. Before the release the internal oscillator must start to oscillate, the internal supply voltages must be set up and various memories set. When switching to Fig. 1 is therefore the smoothed supply voltage Uv with a target voltage U5 compared, which is above the fixed voltage Uv 'set on the controller 12.

As long as the comparator 4 has not responded, i.e.

its output carries a zero signal, is also available at the output of the AND gate 5 and thus at the reset input R of the microprocessor 1 zero signal. The microprocessor However, 1 is only enabled with a "one" signal at its reset input R.

At the point in time designated by t2 in FIG. 2, the supply voltage exceeds Uv the threshold value Us. So that the output of the AND gate 5 goes to one, there too the output of the astable multivibrator 2 and thus the second input of the AND gate 5 is on one. As soon as the delay time t2 has expired, namely appears at the point in time denoted by t3 in FIG. 2 at the reset input R of the microprocessor 1 a "one" signal and the microprocessor 1 is thus released.

When the device is switched off or in the event of a power failure the microprocessor must go into the reset state before its supply voltage collapses. This makes it possible to execute the last command correctly. This is absolutely necessary for devices with data recovery through an external RAM with battery backup or for devices with "stand-by mode". The reset when the supply voltage collapses is achieved by the output signal of the comparator 4 goes to zero as soon as the supply voltage UV falls below its threshold value U5 sinks. This means that the AND condition at AND gate 5 is no longer met and that The output signal of the AND gate 5 also goes to zero. This becomes the capacitor 3b discharged practically instantaneously via the diode 3c and the microprocessor 1 is reset.

However, the microprocessor 1 receives until the time t5, at which the Supply voltage Uv drops below the setpoint for the regulated voltage Uv ', still sufficient tension to properly execute his command. The between The time span lying in time t4 and t5 is due to the discharge of the charging capacitor 11 determined.

As long as the microprocessor 1 is processing its entered program correctly, is at its Output P1 issued a test signal. This is differentiated with the differentiator 6 and resets the astable multivibrator 2. Because the time between two test signals is shorter than the tilting time of the astable multivibrator 2, this can be on his with the AND gate 5 connected output not toggle to "zero", so that the output of AND gate 5 remains at one.

However, if the microprocessor, for example, by a glitch is blocked, no more test signal occurs within the specified time and the astable multivibrator 2 tilts to zero at its output. This also works the output of the AND gate 5 to zero, so that the capacitor 3b via the Diode 3c is discharged quickly as if the supply voltage collapses and the microprocessor is reset. As soon as the monostable flip-flop 2 again switches to the output signal one, the microprocessor 1 is enabled again and can start the program from the beginning.

With the circuit according to FIG. 1, both the supply voltage and the program sequence of the microprocessor 1 is monitored.

A second embodiment in which both timing elements with counters are realized is shown in FIG. 3. Two counters 7 and 8 are connected in series, d. H. the clock input of the second counter 8 with an output of the first counter 7 connected. The clock input of the first counter 7 is connected to a clock generator 9. This circuit also contains a comparator 4, which is the same as in the circuit according to FIG. 1, the supply voltage Uv with a threshold U5 compares. The output of the comparator 4 is connected to a blocking input of the first Counter 7 and connected to a reset input of the second counter 8. Further is as in Fig. 1, the output Pl of the microprocessor 1, a differentiator, consisting downstream from the capacitor 6a and the resistor 6b.

A diode 6c, which is switched in this way, is provided in parallel with the resistor 6b is that at the output of the differentiator 6 there are only positive pulses. That Differentiator 6 is on the output side with the reset input of the first counter 7 connected. Furthermore, an output of the second counter 8 is connected to the reset input R of the microprocessor 1 connected.

When the arrangement is switched on, both counters are initially at zero. As long as the supply voltage Uv is less than the threshold value U5, is on The output of the comparator 4 has a one signal which blocks both counters. Only when the supply voltage Uv exceeds the threshold value U5, both counters released and the pulses of the clock 9 counted.

As soon as the output of the counter 8 reaches a one signal, the Microprocessor 1 enabled. The delay time when switching on is therefore dependent on in this case on the clock frequency of the clock generator 9 and the product of the reduction ratios of the two counters 7 and 8.

In this circuit, the counter 7 is cyclically via a test signal reset at output P1 of microprocessor 1. Otherwise the counter would be 7 the pulses of the clock generator 9 always continue to count and - accordingly in frequency scaled down - pass on to the counter 8. After a number of pulses from the value of the selected output of the counter 8 depends, the microprocessor would then 1 reset will. The time interval between two test signals however, is chosen so that the counter 7 is always reset before his Output a signal change takes place again.

When the supply voltage Uv breaks down, the counter 8 is instantaneous reset as soon as the supply voltage Uv falls below the threshold value US.

This then also results in the desired instantaneous resetting of the Microprocessor 1 in the event of a power failure.

With the circuit according to FIG. 3, both the supply voltage and the program sequence of the microprocessor is monitored. This digitized The circuit version is particularly suitable when a clock pulse is already present is.

- blank page -

Claims (7)

Circuit arrangement for monitoring a program sequence in a microprocessor (1), that a Reset input (R) of the microprocessor (1) with an output of a first timer (2) and a reset input of the first timer (2) with an output (P1) of the Microprocessor (1) is connected that the running time of the first timer (2) is longer is than the undisturbed program runtime that at the output (P1) of the microprocessor (1) A test signal is emitted with each program run that the first timer (2) is reset and restarted every time a test signal occurs and that the microprocessor is reset to its initial state when that first timer (2) expires. 2. Circuit arrangement according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the first timing element (2) is an astable multivibrator that is reset when the supply voltage is switched on. 3. Circuit arrangement according to claim 2, wherein the microprocessor when its supply voltage increases by one the supply voltage with one Limit value comparing comparator (4) and a downstream second timing element (3) released with a delay and when its supply voltage drops below one The limit value is reset, so that the Comparator (4) and the first timing element (2) on the output side via a conjunctive Link (5) and via the second timer (3) with the reset input of the microprocessor are connected. 4. Circuit arrangement according to claim 3, d a d u r c h g e k e n n z e i c h n e t that the second timing element (3) is an RC element, its resistance (3a) is bridged with a diode (3c) so that the microprocessor (1) is instantaneous is reset as soon as the supply voltage (Uv) falls below its limit value or the first timer (2) expires. 5. Circuit arrangement according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the first timing element (2) is controlled by a clock (9) The counter is that when the supply voltage is switched on or by the test signal is set to a first count and when a second count is reached resets the microprocessor (1) to its initial state. 6. Circuit arrangement according to claim 1, wherein the microprocessor at Increase in its supply voltage by one the supply voltage with one Comparator (4) comparing the limit value and a timer connected downstream of this is released with a delay, that is, two Counters (7, 8) are connected in series that the clock input of the first counter (7) with a clock (9), the reset input of the first counter (7) with the Output (Pl) of the microprocessor (1), the lock input of the first counter (7) with the comparator (4), the reset input of the second counter (8) also with the Comparator (4) and the output of the second counter (8) with the reset input of the Microprocessor (1) are connected. 7. Circuit arrangement according to one of claims 1 to 5, d a d u r c h e k e n n n z e i c h n e t that between the output (Pl) of the microprocessor (1) and the first timing element (2, 7) a differentiating element (6) is inserted.