DE3417358A1 - Device for software correlation - Google Patents

Abstract

The invention relates to a device for software correlation in data transmission systems, for example in the radar receiver of a mobile radio network. By means of the software correlation, the received phase and the signal offset are intended to be determined from the received data read into a memory, from which the clock generation can be supplied and the subsequent data stream can be read. The invention provides for this purpose that the received analog signal is converted into a binary data stream in a threshold value detector (2) assigned to the receiver (1) and this data stream is clocked with a multiple of the bit frequency and read into a memory (5). The memory (5) is connected to a processor (6) which determines the phase and the offset of the received signal relative to the clock reference of the receiver (1). The received bit stream is regenerated and read through adjustment of the phase value and correction of the offset. <IMAGE>

Description

Software correlation facility

The invention relates to a device for software correlation in data transmission systems, for example in the radio test receiver of a mobile radio network.

Such a mobile radio network is for example in DE 30 09 309 C2 described. This mobile radio network is a synchronous network, in which the data and voice traffic between the mobile radio subscriber stations and the stationary base stations are handled with a fixed radio area assignment. Before a conversation can be established, there is an organizational data exchange Necessary between mobile subscriber and base station, such as registration, rebooking or dialing number transfer. A separate radio channel is provided for processing, in which several base stations have multiple access, i.e. with fixed time slot allocation can work.

Using this assignment, the mobile subscriber has the option of using the reception quality control with the radio range most favorable for him an organizational one Record data connection. After this structure, however, all time slots will continue the reception quality and the setting criteria are recorded so that if the radio field parameters change, due to the change of location of the mobile subscriber, the now optimal radio range immediately to recognize and to have the necessary setting information ready. By means of a The correlation receiver becomes bit and block synchronization from an asynchronous state carried out for the cheapest radio range. On the other hand, it is in synchronous operation the setting criteria for the current radio area and in the event of a rebooking those of all other possible radio areas are supplied.

By means of the software correlation should be read into a memory from the Receive data, the receive phase and the signal offset can be determined. With these The clock generation can supply values and thus read the subsequent data stream will. The software correlation therefore requires the measurement of the DC signal voltage offset and the bit phase reference of a binary data stream related to a receiver reference clock the state change on an analog channel with finite edge steepness, if on The recipient knows the fixed preamble of the sent message.

The invention is based on the object of a device for software correlation to create, with which the determination of the reception phase and signal offset and reading of the data stream are possible simply and securely.

This task is described above for a facility Kind according to the invention solved in such a way that in one associated with the receiver The threshold value decider converts the received analog signal into a binary data stream and this data stream is sampled at a multiple of the bit frequency and converted into a Memory is read, that this memory is connected to a processor, the phase and offset of the received signal relative to the clock reference of the Receiver determined, and that by adjusting the phase difference and correction of the offset the received bit stream is regenerated and read.

Advantageous refinements and developments of the subject matter of the invention are specified in the subclaims.

The invention is illustrated below with the aid of one in the drawing Embodiment explained in more detail.

In the figure, the receiver, to which an analog signal is fed, is denoted by 1. The receiver 1 is followed by a threshold value decider 2, a second input connected to a processor 6 for setting a Has threshold value. The output of the threshold value decision maker 2 is via a Counting circuit 3, which is driven by an n-fold bit clock of a clock generator 7 is connected to a serial / parallel converter 4 to which a clock line of the Clock generation 7 is connected. The serial / parallel converter 4 is a memory 5 downstream, which is connected via a bus to the processor 6, the next the connection to the threshold value decider 2 is a further connection for clock generation 7 for phase correction.

The following is carried out on how the circuit works: The received The analog signal is converted into a binary data stream by means of a threshold value decision. This data stream is clocked with a multiple (n-fold bit rate) of the bit frequency and read into memory 5. The processor 6, which accesses the memory 5 can, determines the phase and offset of the received signal relative to the clock reference Recipient. It is made from the received data read into the memory the reception phase and the signal offset with an accuracy of i / n of the reception bit period determined. The clock generator 7 and thus the subsequent one can be supplied with these values Data stream to be read. A subsequent fine correlation determines the phase with increased accuracy (1 / m of the bit period) and checks the correlation (detection of the fixed transmission code). For reasons of storage space and processing speed and accuracy is advantageously chosen n = i6 and m = 128.

The received data are clocked into the with the m-fold bit rate Memory 5 read in. One bit in the memory corresponds to the duration of the lim Received signal b, it period. One byte in memory (8 bits wide) corresponds to the Duration of l / n bit periods, since here m = 8n.

The edges of the signal are stored in the memory for phase determination searched and the addresses of the edges converted into phase values. The phase values are then averaged separately for positive and negative edges. The mean the phase value is obtained from the averaged positive and negative edge phases. The difference between the averaged positive and negative edge phases gives a measure for the DC offset of the received analog signal.

Search areas are stored in a table for the search for the edges. The table contains all information about the edge search for each search area and for converting the address of a found edge into the associated phase value. With the help of this table, the search areas can be determined depending on the form of the preamble To be defined. This means that the edge search can be carried out with a minimum of computing time.

The phase determination takes place in such a way that the phase values of the Edges can be averaged separately for positive and negative edges. The mean, worth it the receive clock phase results from the two phase values. This value can be used as a setting value can be used for the reception clock generation.

The difference between the averaged phase values of the positive and negative Edges provide a measure for the offset of the signal. The determined value is proportional to the correction value for the threshold setting. The proportionality factor becomes from the slope of the Analog signal and from the the factors resulting from the software correlation are determined.

3 claims 1 figure

Claims (3)

Device for software correlation in data transmission systems, for example in the radio test receiver of a mobile radio network, characterized in that that in a threshold value decider (2) assigned to the receiver the received Analog signal converted into a binary data stream and this data stream with a Multiples of the bit frequency are clocked and read into a memory (5), that this memory (5) is connected to a processor (6) which the phase and determines the offset of the received signal relative to the clock reference of the receiver, and that by adjusting the phase value and correcting the offset, the received bit stream regenerated and read. 2. Device according to claim 1, characterized in that for phase determination the phase values of the edges of the analog signal separately for positive and negative Edges averaged and from the receive clock phase of the resulting as an average value Setting value for the reception clock generation is obtained. 3. Device according to claim 1 or 2, characterized in that the offset as the difference between the averaged phase values of the positive and negative Edges of the analog signal is obtained.