DE3402257A1 - Circuit arrangement for converting a binary signal into a ternary signal - Google Patents

Abstract

A circuit arrangement is constructed of a logic circuit having an input, a first and second output and a transformer with a secondary winding and two series-connected primary windings. The first output of the logic circuit is connected to the gate electrode of a first and second field effect transistor. The second output of the logic circuit is connected to the gate electrode of a third and fourth field effect transistor. The source electrode of the first field effect transistor is connected to the source electrode of the fourth field effect transistor and to one terminal of a voltage source, the other terminal of which is connected to the mutually connected source electrodes of the second and third field effect transistor and to the junction between the two primary windings. The drain electrode of the first field effect transistor is connected via a first diode to one primary winding and via a third diode to the drain electrode of the second field effect transistor. The drain electrode of the fourth field effect transistor is connected via a second diode to the second primary winding and via a fourth diode to the drain electrode of the third field effect transistor. The ternary signal is picked up across the connections of the secondary winding.

Description

Circuit arrangement for converting a binary

Signal into a ternary signal.

The invention relates to a circuit arrangement for converting a binary signal into a ternary signal with a transformer that has a secondary winding has, at which the ternary signal can be removed, and in which a first and a second primary winding are connected in series, and with a logic circuit whose Input the binary signal is fed to its first and second output Emits signals with the binary value 11011 when the binary signal assumes the binary value 8, and those which are complementary to one another alternately at their first and second output Outputs binary values when the binary signal assumes the binary value "1".

A circuit arrangement for converting a binary signal into a ternary signal is from Bell Telephone Laborartories, Transmission Systems for Comrnunications, revised forth edition, December 1971. In the circuit arrangement, in FIG. 27 - 36 is shown on page 667 of the cited literature, the binary signal is sent via a wire to the first input of a first and a second AND gate and the input of a modulo-2 counter. The non-inverting one The output of the modulo-2 counter is connected to the second input of the first AND gate connected while the inverting output of the modulo 2 counter is connected to the second input of the second AND gate. The outcome of the first AND gate is via two series-connected primary windings of a transformer connected to the output of the second AND gate. The connection point of the two Primary winding is grounded. At the two connections of the secondary winding of the The ternary signal is tapped from the transformer.

When transmitting data signals in the baseband is between the Logic circuit in the known circuit arrangement from the modulo-2 counter and the two AND gates, and to provide a driver circuit for the transformer. With the help of the driver circuit and the transformer, the two outputs the logic circuit pending binary signals in the transmission line as ternary Signal are fed. Thereby occur at the two outputs of the logic circuit either the binary values "1" alternately or the binary values 11011 at the same time. On the other hand, the logic circuit prevents that at its two outputs at the same time the binary values 11111 occur. When the ternary signal at the output of the transformer assumes the value 11 + 111 or "-1", the output resistance of the circuit arrangement should Seen from the transmission line, the internal resistance of a voltage source on the other hand, it should be high resistance if the ternary signal has the value 11911 accepts. This makes it possible to use several such circuit arrangements a logic circuit, a driver circuit and a transformer are constructed, parallel to connect a transmission line. There are those Secondary windings of the transformers connected in parallel and with the transmission line tied together.

In the Integrated Services Digital Network, or ISDN for short, are such circuit arrangements for converting a binary signal into a ternary one Signal provided as interfaces, the properties of which are precisely specified. In addition to the resistance conditions already specified, the circuit arrangements have a high earth symmetry, only require a low control power and ensure a high edge steepness for the ternary signal.

The object of the invention is therefore. a balanced circuit arrangement to convert a binary signal into a ternary signal, specify its output resistance If the ternary signal assumes the value 11911, its output resistance is high on the other hand, it is low-resistance when the ternary signal assumes the value n + l or "-1", and which requires a low control power and a high edge steepness of the ternary signal causes.

The invention solves this problem in that the first output Al the logic circuit L with the gate electrode of a first and a second field effect transistor F1, F2 is connected that the second output A2 of the logic circuit L to the gate electrode a third and fourth field effect transistor F3, F4 is connected that the source electrode of the first field effect transistor F1 with the source of the fourth field effect transistor F4 and connected to one pole of a voltage source U. is that the source electrodes of the second and third field effect transistor F2, F3 are connected to one another and to the other pole of the voltage source U as well as connected to the connection point of the first and second primary winding Pl, P2 are that the drain electrode of the first field effect transistor F1 has a first Diode D1 is connected to the terminal of the first primary winding P1, which is not is connected to the second primary winding P2 that the drain electrode of the fourth Field effect transistor F4 via a second diode D2 to the connection of the second Primary winding P2 is connected, which is not connected to the first primary winding P1 is that the drain electrode of the first field effect transistor F1 via a third Diode D3 connected to the drain electrode of the second field effect transistor F2 is that the drain electrode of the fourth field effect transistor F4 via a fourth Diode D4 connected to the drain electrode of the third field effect transistor F3 is that the first field effect transistor Fl in push-pull to the second field effect transistor F2 works that the third field effect transistor F3 in push-pull to the fourth field effect transistor F4 works that the first diode D1 in the circuit from the voltage source U, the first primary winding P1 and the drain-source path of the first field effect transistor F1 is forward polarized that the second diode D2 in the circuit from the Voltage source U, the second primary winding P2 and the drain-source path of the fourth field effect transistor F4 is polarized in the forward direction that the third Diode D3 in which the voltage source U and the drain Source routes of the first and second field effect transistor F1, F2 formed circuit in the forward direction is polarized and that the fourth diode D4 in the from the voltage source U and the Drain-source paths of the third and fourth field effect transistors F3, F4 are formed Circle is also polarized in the forward direction.

The subclaims contain advantageous embodiments of the invention specified. The figure shows an embodiment that was first described and will then be explained with reference to the figure.

The binary signal is fed to the input E of the logic circuit L. The output A1 of the logic circuit L is connected to the gate electrode of a field effect transistor F1 and a field effect transistor F2 connected, while the output A2 of the logic circuit L to the gate electrode of a field effect transistor F3 and a field effect transistor F4 is connected. The source electrode of the field effect transistor F1 is with the Source electrode of the field effect transistor F4 and with the negative pole of a Voltage source U connected, whose positive pole is connected to the interconnected Source electrodes of the field effect transistors F2 and F3 is connected. The connection point the first and second primary windings P1 and P2 is also positive Pole of the voltage source U connected. The drain electrode of the field effect transistor F1 is connected to the cathode of a diode D3 and a diode D1. The drain electrode of the field effect transistor F4 is connected to the cathode of a diode D4 and a diode D2 connected. The anode the diode D3 is connected to the drain electrode of the field effect transistor F2 is connected, and likewise the anode of the diode D4 is connected to connected to the drain electrode of the field effect transistor F3. The anode of the diode D1 is connected to the connection of the primary winding P7 via a resistor R1, which is not connected to the second primary winding P2, while the anode of the Diode D2 connected to the connection of the primary winding P1 via a resistor R2 which is not connected to the primary winding P2. At the two connections B1 and B2 of the secondary winding, the ternary signal can be removed. To these two A transmission line can be connected to terminals B1 and B2. The logic circuit L can, for example, be structured like that in FIGS. 27-36 of the cited literature reference circuit shown. The field effect transistors F1 and F4 are normally off n-channel field effect transistors, while the field effect transistors F2 and F3 are normally off p-channel field effect transistors acts. The Miller capacitances CM of the field effect transistors F1 and F4 are in the figure drawn in dashed lines. The resistors R1 and R2 are equal in size selected low resistance.

When explaining the mode of operation of the exemplary embodiment, initially assumed that at the input E of the logic circuit L as a binary Signal is a sequence of ones. Then the logic circuit gives L to both of them Outputs A1 and A2 alternately produce complementary signals: If on the first Output A1 outputs a logical "1", the second output A2 outputs a logical "1" 11011 from. At the next logi- between "1" at input E gives the first output A1 a logical 11911, on the other hand the second output A2 now a logical one lllfl from.

It is now assumed that at the first output Al of the logic circuit L a logic "1", i.e. high potential, and a logic 11911 at output A2, so low potential is applied. Because the field effect transistor F1 is therefore conductive is, while the field effect transistor F2 is blocked, a current can be in the loop flow from the voltage source U, the primary winding Pl, the resistor R1, the diode D3 and the drain-source path of the field effect transistor F1 will. The tasks of the field effect transistors F2 and F3 will be explained later. Despite the conductive field effect transistor F3 can because of the diodes D2 and D4 and because the field effect transistor F2 is blocked, no current through the primary winding P2 flow.

From the outputs B1 and B2 of the secondary winding is viewed the primary winding P2 operated in this case in no-load mode because of the diodes D2 and D4. The ternary signal at the output of the secondary winding assumes the value "+1". In the The next logical 11111 at the input E of the logic circuit L reverses the potential relationships at the outputs A1 and A2. At output 1 there is now a logical "8", that is low potential, while at output A2 because of the logic "1" high potential is present. Because the components F1, F2, D1, D3, R1 and P1 are symmetrical to the components F4, F3, D2, D4, R2 and P2 are arranged, the ratios also reverse the field effect transistors and the primary windings. Because the field effect transistor F1 is now locked, now flows a current through the second primary winding P2, while the first primary winding P1 despite the conductive field effect transistor F2 is operated in no-load mode because of the diodes D1 and D3.

The field effect transistor F2 has the task of the dashed line in the figure indicated Miller capacitance CM of the field effect transistor F1 to discharge when the Field effect transistor F1 changes from the conductive to the blocking state. as well the field effect transistor F3 discharges the Miller capacitance CM of the field effect transistor F4, when the field effect transistor F4 changes from the conducting to the blocking state. If there is a high potential at the output A1 of the logic circuit L, the field effect transistor is F1 conductive. In the conduction phase, the Miller capacitance CM, which is between the gate electrode and the drain electrode is charged so that it is high at the gate electrode the drain electrode, on the other hand, has a low potential. As soon as the exit Al der Logic circuit L is applied again low potential, the field effect transistor blocks F1. The transition from high to low potential at output Al takes place at the one connected to the gate electrode of the field effect transistor F7 electrode the Miller capacitance CM is a charge equalization. The opposite electrode of the Miller capacity is still low because of the previous charging process Potential. Without the field effect transistor F2, a charge exchange would occur between this electrode and the positive pole of the voltage source U via the resistor R1 and the primary winding P1 take place. This would have a worsening of the edge steepness of the ternary Signal. But because the field effect transistor F2 is now conductive, the charge exchange does not take place via the resistor R1 and the primary coil P1 but via the diode D3 and the field effect transistor F2. on the same way is the Miller capacitance of the field effect transistor F4 via the Diode D4 and the drain-source path of the field effect transistor F3 recharged.

By reloading the Miller capacitances using the field effect transistors F2 and F3 are the slope of the ternary signal at the transition of the field effect transistors F1 and F4 increased from the conductive to the blocking state. The transition from the blocking in the conductive state is not critical because the Miller capacitance over the Drain-source path of the field effect transistors F1 and F2 are reloaded. this does not affect the slope of the ternary signal in a negative way.

Finally, consider the case that at both exits A1 and A2 of the logic circuit L a logic "8", i.e. low potential, is applied. The field effect transistors F1 and F4 are blocked, while the field effect transistors F2 and F3 are in the lead phase. Because of the diodes D1 and D3, the first winding becomes primary P1 and because of the diodes D2 and D4, the second primary winding P2 is also connected to the Secondary winding is operated in no-load mode.

When the field effect transistor F1 is conductive, flows in the loop from the voltage source U, the source-drain path of the field effect transistor F1, the diode D1, the resistor R1 and the primary winding P1 a current. The ternary Signal has thereby the value "+1". The primary winding P1 is then if you consider the internal resistance of the voltage source U, the resistance of the source-drain path of the field effect transistor F1 and the resistance of the diode D1 neglected, with the precisely definable and low-resistance selected resistor R1 completed. because the resistor R2 - as already mentioned - chosen to be the same size as the resistor R1 is, the same applies mutatis mutandis to the primary winding P2.

Therefore, when the ternary signal takes the value "+1 or ~ 1 # 111 the output resistance of the circuit arrangement seen from the secondary winding low-resistance, while it is high-resistance because of the diodes D1, D2, D3 and D4, if that ternary signal assumes the value 11911. By means of the field effect transistors F2 and F3 increases the slope of the ternary signal. Good earth symmetry results from the symmetrical structure of the circuit arrangement. The control power is low because field effect transistors are used.

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Claims (4)

Circuit arrangement for converting a binary signal into a ternary signal with a transformer (Ü) that has a secondary winding, at which the ternary signal can be removed, and at which a first and a second Primary winding (P1, P2) are connected in series, and with a logic circuit (L), the input (E) of which the binary signal is fed to the first and second Output (Al, A2) emits signals with the binary value A8 "if the binary signal is the Binary value "o" assumes, and that at their first and second output (A1, A2) alternately outputs complementary binary values when the binary signal has the binary value ~ 1 ", characterized in that the first output (A1) of the logic circuit (L) to the gate electrode of a first and a second field effect transistor (F1, F2) is connected that the second output (A2) of the logic circuit (L) with the Gate electrode of a third and fourth field effect transistor (F3, F4) connected is that the source electrode of the first field effect transistor (F1) with the source electrode of the fourth field effect transistor (F4) and with one pole of a voltage source (U) is connected that the source electrodes of the second and third field effect transistor (F2, F3) are connected to each other and to the other Pole of Voltage source (U) and at the connection point of the first and second primary winding (P1, P2) are connected that the drain electrode of the first field effect transistor (F1) via a first diode (D1) to the connection of the first primary winding (Pl) is connected, which is not connected to the second primary winding (P2) that the drain electrode of the fourth field effect transistor (F4) via a second diode (D2) is connected to the terminal of the second primary winding (P2) that is not connected to the first primary winding (P1) is connected to that the drain electrode of the first Field effect transistor (F1) via a third diode (D3) to the drain electrode of the second field effect transistor (F2) is connected to that the drain electrode of the fourth Field effect transistor (F4) via a fourth diode (D4) to the drain electrode of the third field effect transistor (F3) is connected that the first field effect transistor (F1) works in push-pull to the second field effect transistor (F2) that the third Field effect transistor (F3) works in push-pull mode to the fourth field effect transistor (F4), that the first diode (D1) in the circuit from the voltage source (U), the first primary winding (P1) and the drain-source path of the first field effect transistor (F1) in the forward direction is polarized that the second diode (D2) in the circuit from the voltage source (U), the second primary winding (P2) and the drain-source path of the fourth field effect transistor (F4) is polarized in the forward direction that the third diode (D3) in the one from the voltage source (U) and the drain-source paths of the first and two th field effect transistor (F1, F2) formed circle is polarized in the forward direction and that the fourth diode (D4) in which from the voltage source (U) and the drain-source paths of the third and fourth field effect transistor (F3, F4) formed circle also in the forward direction is polarized. 2. Circuit arrangement according to claim 1, characterized in that a first resistor between the first diode (D1) and the first primary winding (P1) (R1) and between the second diode (D2) and the second primary winding (P2) second resistor (R2) is located. 3. Circuit arrangement according to claim 2, characterized in that the first and second resistors (R1, R2) are selected to be of low resistance and the same size. 4. Circuit arrangement according to claim 1, 2 or 3, characterized in that that the first and fourth field effect transistors (F1, F4) are normally off n-channel field effect transistors and that the second and third field effect transistors (F2, F3) are normally off are p-channel field effect transistors.