DE3364915D1 - Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate - Google Patents

Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate

Info

Publication number
DE3364915D1
DE3364915D1 DE8383401017T DE3364915T DE3364915D1 DE 3364915 D1 DE3364915 D1 DE 3364915D1 DE 8383401017 T DE8383401017 T DE 8383401017T DE 3364915 T DE3364915 T DE 3364915T DE 3364915 D1 DE3364915 D1 DE 3364915D1
Authority
DE
Germany
Prior art keywords
implantation
simplify
substrate
manner
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383401017T
Other languages
English (en)
Inventor
Jacques Meyer
Roger Cru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Application granted granted Critical
Publication of DE3364915D1 publication Critical patent/DE3364915D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8383401017T 1982-05-25 1983-05-20 Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate Expired DE3364915D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8209052A FR2527868A1 (fr) 1982-05-25 1982-05-25 Circuit integre logique concu de maniere a simplifier son implantation sur un substrat

Publications (1)

Publication Number Publication Date
DE3364915D1 true DE3364915D1 (en) 1986-09-04

Family

ID=9274297

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383401017T Expired DE3364915D1 (en) 1982-05-25 1983-05-20 Integrated logic circuit conceived in a manner such as to simplify its implantation on a substrate

Country Status (3)

Country Link
EP (1) EP0095418B1 (de)
DE (1) DE3364915D1 (de)
FR (1) FR2527868A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4880754A (en) * 1987-07-06 1989-11-14 International Business Machines Corp. Method for providing engineering changes to LSI PLAs
TW250580B (en) * 1994-08-16 1995-07-01 Holtek Microelectronics Inc Layout method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140967A (en) * 1977-06-24 1979-02-20 International Business Machines Corporation Merged array PLA device, circuit, fabrication method and testing technique

Also Published As

Publication number Publication date
FR2527868A1 (fr) 1983-12-02
EP0095418A1 (de) 1983-11-30
EP0095418B1 (de) 1986-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee