DE3347478A1 - Method and circuit arrangement for reducing written characters - Google Patents

Abstract

The conversion from an old raster allocated to the original character height or width into a new raster corresponding to a nominal height or width is carried out in such a manner that, beginning with a first negated new-raster unit (-N), such a number of old-raster units (n) are added that a compensation or a first excess ( DELTA 1) is produced, that when a first excess ( DELTA 1) occurs, a second negated new-raster unit (-N) is called up and, taking into consideration this excess, such a number of further old-raster units (n) is added that a new compensation or a second excess ( DELTA 2) is formed and so forth, that from the whole or proportional old-raster units, in each case allocated to one new-raster unit, with black picture content an aggregate black component value is formed and that this aggregate black component value is compared with a threshold value (SW) in such a manner that when this threshold value (SW) is exceeded, a black value is obtained for the respective new-raster unit. <IMAGE>

Description

Method and circuit arrangement for reducing the size of

Characters The invention relates to a method for reducing the size of characters according to the preamble of claim 1 and a circuit arrangement to carry out the procedure.

The classifiers used in machine character recognition generally only deliver satisfactory results if the Characters do not exceed a certain standard size. For hand block letters with usually widely varying and much too compared to machine fonts large character height is therefore a character classification only after appropriate Processing of the scanned image patterns is possible.

Processes and circuits are therefore already known (DE-AS 22 36 382, DE-OS 30 36 711), in which the height and / or width of characters by reducing the number of real pixels within the framework of fixed grid ratios can be reduced into a smaller number of transformed pixels.

The present invention is based on the object of a method to shrink characters in such a way that characters of different Size can always be reduced to a uniform standard size, with the implementation of a any height or width different numbers of old grid units to an always the same number of New raster units as little character information as possible should be lost.

The solution to this problem results according to the invention by the characterizing Features of claim 1 The inventive method has the advantage that in the case of character reduction, any and thus also odd numbers, depending on the requirements Grid ratios are possible, with those in the overlap area of the old and new grid each overhanging old grid unit according to the selected grid ratio Proportionally offset against the current or the following new grid unit will.

Advantageous further developments of the inventive concept are set out in the subclaims In the following an embodiment of the invention is based on the characters now explained in more detail. 1 show the principle of character reduction based on a comparison of the Altraster and Neuraster, FIG. 2 shows the basic circuit diagram a character reduction circuit according to the invention, FIG. 3 shows an example circuit for a circuit according to FIG 2.

The figure 1 shows a number 3, which for the purpose of reduction an Altraster AR is converted into a Neuraster NR. Due to the character height relationship ZH = N x ARE = n x MRE where N is the number of old grid units ARE and n mean the number of neural grid units NRE, results for Altraster AR and New grid NR a common sub-grid dimension SR.

ARE NRE SR = - N n It follows from this that each old grid unit ARE from n sub-raster units and each neuro-raster unit NRE from N sub-raster units composed. Because of this sub-grid size common to the old grid and the new grid SR it is possible to determine the blackening quantities from the old raster according to their sub-raster components to be distributed to the corresponding neural grid units.

A basic circuit for rasterizing a character is shown in FIG 2 shown. The starting point of this circuit are two signals tlnt and "N", due to the relationship ARE = n x SR and NRE = N x SR to the old grid AR or to the Neuraster NR belong. N means the extension of the character in the old grid, i.e. the number of old grid units ARE above the character, while n is the number of the new grid units NRE the desired extension of the character in the new grid indicates. Due to the above relationship, however, N is the new grid and n is the old grid assigned. "n" is always smaller than "N". Both are simple numbers and in this one The numerical ratio is to be reduced in size, i.e. rasterized again. With A so-called grid offset tracking circuit RVV is now on hand of the two signals "N" and "n" determined how many black sub-grid units SR fall into the respective neural grid units. Since the neuraster is coarser than the old grid, there are also more sub-grid units included. Starting from a first new grid unit is now examined, how many old grid units quite or partly in this NeurastereinEew all this is done in such a way that so many old grid units are added up until the new grid unit is full or an overflow occurs in the case of odd grid ratios. This overhanging one Part g is the number of sub-grid units that are at the new grid boundary in overhang the next following new grid unit. This excess # becomes continuous registered as A1, # 2 ..... (see FIG. 1) and the next following new raster unit will be added to the determination of the excess b at a new grid limit the respective black components are calculated in the new grid. This happens in a so-called Black component summing circuit SAS, in which the content of the in a Neurastereinheit completely or partially falling old grid units due to the image signal, doho provided the corresponding image signal is black, is summed up. This sum signal BS is finally in a subsequent comparator circuit KOMP with a threshold value SW compared, with a black value when this threshold value is exceeded for the respective image output signal BA results. In the other case, the image output signal BA 'iweiB "rated details of the circuit according to FIG. 2 are those shown in FIG Block diagram can be found. According to the condition: NRE = N x SR becomes the new grid given as signal "N" and via a first NAND gate NDG1 as a negative numerical value fed to a second adder ADD2. At the same time, an assigned to the old grid arrives Signal 'tn "also to the second adder ADD2 via a first adder ADD1 The respective subtotals at the output of the second adder ADD2 are each via a first accumulator ACCU1 to the first adder ADD1 fed back until there is a positive value at the output of the first adder ADD1 results. This changes the sign bit, i.e. the most significant bit B7, from i to "O". This new sign bit "O" is negated in a first inverter INV1 and triggers a new signal "N" via the first NAND gate NDG1, i.e. another new raster unit the end. While the work cycle is always assigned to the old grid, the cycle TA for the newly rasterized image signal BA for each overlapping process in the AND element UG4 newly formed.

The positive signal appearing at the output of the first adder ADD1 is also used as excess d in the subsequent black component summing circuit SAS further processed. This excess signal A is in this case via a second NAND element NDG2 fed as a minus value to a fourth adder ADD4. That fourth adder ADD4 are also ADD3 via a third adder and via a first AND element UG1 continuously supplied n-signals due to the image signal and there with the content of a second accumulator ACCU2 is added as long as the content of the first accumulator ACCU1 remains negative. As long as this negative state exists, the signal will be "n" in each case in full length to the picture signal-related black component sum (see the AND link with the image signal BE).

If the accumulator content is positive, i.e. if there is an excess A, is via the AND link UG4 of the negated sign bit "-B7" with the input clock TE released an output cycle TA. At the same time, both the current Black components sum via the AND link UG3 through image signal-related addition of the portion n - g completed, as well as with the over- shot d a new summation started. For the latter purpose, care must therefore be taken that the content of the second accumulator ACCU2 is no longer taken into account. the new summing is started by the excess signal d from the output of the first adder ADD1 via the second NAND gate NDG2 and via a second Inverter INV2 and via an input S = 1 of a multiplexer MUX directly into the second accumulator ACCU2 is clocked in. At the same time stands at the exit of the fourth Adder ADD4 the completed black components sum (contents of ACCU + n - ß) of the completed new grid unit. This sum signal is then used in a comparator circuit COMP compared with a threshold value SW, the level of which determines whether the output signal BA is taken over as black level or as white level in the new raster. The signal SYNC is used to standardize the first accumulator ACCU1 and via the D flip-flop DFF to prevent output clocks TA before the beginning of each picture column or picture line

Claims (4)

Claims method for reducing characters that by means of a row of photodiodes, columns and / or rows are scanned and can be stored in the form of a digital image pattern matrix, the original Old raster assigned to the character height in a target height or width corresponding New grid is implemented, that is, starting with a first negated new grid unit, as many old grid units are added until a balance or a first surplus arises that with the emergence of a first excess, a second negated neural grid unit is retrieved and taking into account this excess, as many other old grid units are added until a new balance or a second surplus is formed, etc. from the whole or part of the old grid units assigned to a new grid unit a black component sum value is formed with black image content and that this black component ° sum value is compared with a threshold value in such a way that that when this threshold value is exceeded, there is a black value for the respective New grid unit results in a second circuit arrangement for carrying out the method Claim 1, by a) a raster offset tracking circuit (RVV), beginning with a common start for Altraster and Neuraster each time the new grid limit is exceeded by an old grid unit, another New grid clock is triggered and in which the excess occurring at the new grid limit is assigned to the following new raster unit, b) a black component summation maintenance (SAS) that made the whole falling into a new grid unit and proportional old grid units with black image content a black component summation value forms and c) a comparator circuit (KOMP), which the respective black component sum value compares with a threshold value and, if the threshold value is exceeded, a black value supplies for the respective neural grid unit. 3. Circuit arrangement according to claim 2, d a d u r c h g e k e n n note that the raster offset tracking circuit has a first adder (ADD1), via the first input of which the desired number of new grid units, over which the character is to extend, supplied as the first binary signal (s) is that the output of the first adder (ADD1) with the first input of a second Adder (ADD2) is connected, via its second input according to the number of old grid units, over which the mark extends, second, by means of a first NAND gate (NDG1) negated binary signals (N) are supplied and that the The output of the two adder (ADD2) is connected to a first accumulator (AKKU1) whose output is fed back to the second input of the first adder (ADD1) is. 4. Circuit arrangement according to claim 2 or 3, d a -d u r c h g e it is not indicated that there is a third in the black component summing circuit Adder (ADD3) is provided, via its first input as a function of black components in the image signal (BE) corresponding black signals assigned to the old grid units (n) are fed that the output of the third adder (ADD3) with a first entry a fourth adder (ADD4) is connected, the second input of which has a second NAND gate (NDG2) to the output of the first adder (ADD1) of the raster offset tracking circuit is connected that the output of the fourth adder (ADD4) with first inputs (S = 0) of a nultiplexer (MIX) is connected, via its second inputs (S = 1) a black excess signal (A) is supplied from the output of the first adder (ADD1) that the output of the multiplexer (MIX) via a second accumulator (ACCU2) is fed back to the second input of the third adder (ADD3) and that the output of the fourth adder (ADD4) is connected to a comparator circuit (KOMP) is that when a value is exceeded at the second input of the comparator circuit (KOMP) supplied threshold value (SW) is assigned to the respective new raster unit Black level output signal (BA) supplies, whereby the associated image output clock (TA) by changing the sign in the total value of the first adder (ADD1) is triggered.