DE3334579A1 - DEVICE FOR STORING IN A CACHE - Google Patents

Description

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Applicant: Stuttgart, September 23, 1983

Data General Corp. P 4417 R / C vieatboro, Mass. 01581

Representative:

Kohler - Schrfindling - Späth Patent attorneys iiohenWielstraße 41 7000 Stuttgart 1

Before direction for storing in a cache

Cross-references to related_ registrations

The present application is related to U.S. Patent Application No. 266,539, filed May 22, 1981, and US patent application Mr. 301 999 »registered on September 11, 1981, and others refer to these patent applications related patent applications.

H invention ackground of Fiction

1 Field of the invention:

The present invention relates generally to digital computer systems that use caches in their CPUs and more specifically to digital computer systems that use caches to interpret operands in instructions.

2 Description of the prior art - Pig 1 and 2 2.1 Introduction to the caches:

Many known computer systems use caches in their CPUs. A cache is a fast memory within the CPU used to store data items frequently used by the CPU when executing programs. Access to data items stored in the cache is

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faster than accessing data items stored in the Main memory of the computer system contain 3ind, and consequently can store frequently used data elements in a cache (hereinafter referred to as "caching") speed up the execution of programs by the computer system.

A cache is accessed using a key. Data elements that can be cached are with Keys are connected, and the key is entered into the cache. If the cache is the one associated with the key Contains data item, the cache outputs the data item; otherwise the cache generates a cache miss signal. The CPU responds to the cache miss signal by loading the data element corresponding to the key into the cache.

In general, caches are used for two types of data items: those that hold copies of in main memory and for those that are the result of operations performed by the CPU are. Figure 1 is a block diagram illustrating both uses of Cachee in known computer systems. A Computer system 101 has two main components: a CPU 102 and a main memory 103. The main memory 103 contains Data items and commands (instructions) and the CPU 102 performs operations on the data items in main memory 103 as a sequence of commands. The CPU 102 includes two caches, a result cache 105 and a data copy cache 10 ^. The main memory 103 contains a table 109, contains the table entries (TEs) 111 (1) to 111 (n), a Table 109 'with TEs 111 (1)' to 111 (k) ', a table Calculation data (TCD) 117 and cacheable data 113> aie single

contains editable data elements (EDI) 115 (1) to 115 (ft). the TEs 111 are identified by table keys (TKs) 110 and EDIs 115 are identified by data keys (DKs) identified.

The result cache · 105 contains result entries (REs) 106. Each RE 106 contains a VR PeId 104, which indicates whether the RE 106 is valid. A valid RE 106 corresponds to a ^: single TE 111 (a) and contains results obtained from calculations using the TE 111 (a) and the TCD 117. A valid RE 106 (a) corresponding to a TE 111 (a) can be accessed using the TK 110 (a) corresponding to the TE 111 (a).

The data copy cache 107 contains copy entries (CE) 108. Each CE 108 contains a VC field 114 that indicates whether the CE 108 is valid. If so, the CE 106 contains a copy of the data in a single EDI 115 (b) and is via the DK 112 (b) in accordance with EDI 115 (b) accessible.

A cache miss signal occurs in both data copy cache 107 and result cache 105 if the cache has a key is offered and the cache either does not have an entry corresponding to the key or the one corresponding to the key corresponding entry is invalid. The CPU 102 responds to the cache miss signal by making the cache entry charges according to the SchhlüS3el. In the case of the data copy cache 107, nothing more happens than that the data is in the correct one EDI 115 can be retrieved from memory and transferred to the Data copy cache 107 can be stored in a CE 108, which is accessed by the corresponding DK 112. in the

Pall desresultcaohe 105 need data from the correct TE 111 and TCD 117 are called up, calculations are required and the result must be stored in the correct RE 106 in the result cache 105.

.2.2 Limits of the known caches:

The use of caches in any digital computer system is limited by the fact that the cached Data elements can become invalid. In the caches of FIG. 1, a cached data element can be of three types Wisely become invalid:

If there is a data item in main memory 103, the cached data item becomes invalid when the data item in main memory 103 changes value.

When a key changes its meaning, it becomes cached Invalid data item accessed by the key.

- Whom. a cached result is calculated using another data item and that If the data element changes its value, the cached resilience becomes invalid.

Pig. 1 shows all of these possibilities. If the EDI 115 (b) changes value, then the CE 108 (b) is no longer a copy of the EDI 115 (b) and CE 108 (b) must be invalidated. The TK 110 likes to be used as a key either serve for table 109 or table 109 '; if the

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CPU 102 terminated the use of table 109 and with the If the use of table 109 'begins, the REs 106 correspond not the TEa 111 'and all REs 106 in the result cache 105 must be made invalid; if a data element is in the TCD 117 changes its value, all REs 106 must im , Result cache 105 that depend on that data item will be invalidated. In the latter case, e3 is in general impossible to determine which RE 106 depends on a given data item in TCD 117, and so in general, any change will require 'invalidation' of all REs 106.

Sometimes it is possible to invalidate the 3n cache entry reload if invalidated. In general, however, the invalid cache entry will be loaded when a Cache miss occurs. Therefore, after a change in the TCD 117 has made the result cache 105 invalid, the result cache 105 step by step, corresponding to the display of incorrect signals in the TKs 110 are reloaded with the results calculated by the new value of the TCD 117. if the / **>. · TCD 117 does not change its value often, that outweighs by that Use of result cache 105 performance gained, the time required to load result cache 105; when, however, the Changes occur frequently, the REs 106 are generally invalid and the use of the result cache 106 in the CPU 102 leads to no gain or even a loss of effectiveness.

2.3 Caching of memory addresses depending on Operands - Figures 2 and 2A

The difficulties of caches just described in connection with certain characteristic properties of Standard coin computer architectures make the use of Caches have so far been difficult in one key field: the translation of an operand specifying data in an instruction into the memory address of this data. Like in Pig. 2 includes a typical instruction 201 for the CPU a command: ilscode 203 and one or more operands 205- Der Instruction code 203 specifies one to be executed by the CPIT 102 with the operand 205 identified Surgery. In general, the operand is a relative address operand 207 · There are at least one such operand two fields: an RS field 209, which is a multipurpose register specified in the CPU 102, and a DISP field 213 which contains a binary integer. The integer specified relative addressing, and the specified register in CPU 102 contains a base address. the Address of the data represented by the relative address operand 207 is obtained by adding the data represented by the DISP field 203 related address to the in the general purpose register specified by the RS field 207 Ba3isadres3e. In addition, the relative address operand 207 may contain other fields. Here contains the relative address operand 207 still has an indirect bit IB 211, which indicates that the address in the main memory 103 which is carried out by Addition of the value of DISP field 213 to that in the by the RS field 207 specified value contained in the register is not the address of the data represented by the operand, but rather the address of a pointer that

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pointing to the data. A pointer is a data element whose value is the address of data.

Fig.2 B gives an example of how an address is made up of operands "that specify a register that receives a base address and a relative address. The GPU 102 includes a general purpose register set GPRS 225, the Contains general purpose registers R 223 (O) through R 223 (n). For the purposes of this discussion, each is a general purpose register Register that an instruction executed by CPU 102 can set to an arbitrary value. The content of a Register R 223 is indicated in Fig. 2A by cont (x), where χ is the number of R 223. The memory 103 contains a storage section 215 which in turn is a data item 217 contains. The data element 217 is represented in an instruction by BDO 219, a relative address operand (Base-Displacement Operand) 205 of the type just described. In BDO 219, b represents the value of RS field 209, and c is the value of DISP 213 · R (b) indicated by the RS field 209 is specified, the address in the memory section 215 contains »specified by cont (b). Of the Arrow 221 identifies the memory location in memory section 215 specified by cont (b). GPU 102 receives the address of the data element 217 by executing the invoice cont (b) + c.

The relative address operand 207, which relates to the data element 217, may appear again and again in a computer program that runs in the CPU 102 and the address of data element 217 does not change. However, it is impractical to convert the address of data element 217 into a Cache, the relative address operands 207 as

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Key used. It is because of such a cache is actually a result cache similar to the result cache 105 of FIG. 1. The content of each entry in the Cache is calculated using the value of the R 223 "specified in the operand. However, the Instructions executed by CPU 102 change the value of that R 223 at any time and in a random manner, and so is the specified R 223 in the same proportion to the cached address as a data element in the TCD 117 in relation to a RE 106 calculated from it. Just like the R 106 every time the data element in the TCD 117, from from which it is derived, changes its value, must be invalidated, the cached address must be invalidated every time the R 223 specified in the operand corresponding to the address changes its value.

The present invention seeks to provide an improved computer system that in which the addresses translated from operands can be cached, and a caching device at that certain changes in the values used to calculate the cached data will not invalidate the cached data do. The present invention therefore overcomes the above mentioned disadvantages of the known computer systems and Caching devices.

ORiGiNAL INSPECTED

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Zusamme nfassende Dars tellung of Erf iiidung

The present invention "is concerned with a caching device in a digital computer system for caching values made up of component values "residing in Change depending on various operations of the digital 'computer system. One type of component value becomes kept in a cache, along with specifiers that specify another type of component value. Depending on a key, the first cache gives a first Component value of the first type and a specifier; the specifier is then used to represent the second kind of Component value from a second cache or register. The two component values then become simultaneous output from the first cache and the second cache or register to a combining device, for example an alder, and the combining device combines the values to form the desired value. A register or cache, the one A given type of component must only be reloaded when the digital computer system carries out an operation that changes that component, and consequently the device has to cach in less frequently than known cache devices completely reloaded.

The device for caching of the type just described is particularly advantageous in a digital computer system, that uses operands that represent data by specifying an entry in a table. The table entry specifies a direct relative address using a base specifier which is a base a ·. rease identi-

ORIGiNAL INSPECTED COPY

adorned, and a spenaifier for an address offset, from which an address offset from the base address can be calculated. Those represented by the operand Data is located at the address obtained by adding the address offset ju to the base address rfird.

In some digital computer systems that use direct relative addressing, certain base addresses change with every call and return operation, whereas certain address offsets only occur with certain call and return operations change. In such a digital computer system comprising a caching device of the just is used, a cache responsive to the operands may contain address offsets derived from table entries and cache base specifiers that have the same Base address as specifying an address specified in the table entry are calculated. Am register set may contain the base addresses. The addresses from the registers and the address offset from the cache 'will both be to a tvomb inier device that contains an adder, issued. A controller responsive to the cache base specifier selects those specified by the cache base specifier specified base address, and the adder adds the selected base address to the address offset. While certain base addresses in the registers can be changed with each call operation and each return operation must, the cache only needs to be invalidated for the relatively infrequent call and return operations that the Change table.

A related type of caching device is advantageous when using a digital computer system of the type just described using indirect relative addressing used by base pointers whose values do not change between certain operations of the digital computer system. With such a relative addressing, the table entry contains a base specifier, a first Address offset specifier and a second address offset specifier. Am from the first address offset specifier The calculated first address offset gives the address offset of the base pointer compared to that of the Base address specifiers identified base address, and a second address offset calculated from the second address offset specifier gives the address / substitute of the Data that corresponds to the table entry Operands are represented opposite the address specified by the base pointer. The caching device may have a first cache containing the first address offset and the second address offset, and a second cache connected to the first, containing the base pointers and the first address offset from the first Cache receives. The outputs of both the first cache and the second cache are connected to a combiner tied together. When an operand is presented to the first cache, the second address offset and that by the first Address offset specified base pointers are simultaneously output to the combining device. Again, α must be the first cache can only be invalidated if an operation of the digital computer system changes the table, and the second The cache only needs to be invalidated if an operation used the one to locate the base pointer Base address changes.

The two types of incaoh devices just described can be combined into a single device for caching both directly and indirectly derived addresses will. Such a device consists of a first cache, a second cache, a set of registers, a Combination device and a control device. The first cache receives the operands and responds to them. Contains br Cache base specifiers that specify a base address and specify whether a direct or indirect relative Adressiervoag must be used, the first address offset and, if the base specifier so specifies, the second address offset. The second cache contains the base pointers and receives the second address offset from the first cache. The set of registers contains base addresses. The outputs of the first cache, the second cache and the Register seat are all connected to the combining device. The control dll device receives the cache base specifier from the first cache and selects leading to the combining device Inputs off. If the cache base specifier specifies direct addressing, the control unit chooses the appropriate one Basic address from the set of registers, and the combining device combines them with the first address offset. If the base specifier is indirect addressing specified, the control unit selects the output of the second ciche, and the combiner combines the through the base pointer returned as a function of the second cache from the second address offset to the first address offset.

Certain base pointers in a digital computer system using the caching device may be contained within the scope of a stack in the memory of the digital computer system. One of the base addresses in the digital computer system specifies the top frame 'of the stack '. The cache, which contains copies of the base pointers contained in the framework of the memory stack, can itself contain a stack. Frames of the cache stack correspond to frames of the stack in memory. A cache stack frame corresponding to a storage stack frame contains copies of the base pointers from the storage stack frame to which it corresponds. The order of the base pointers in the cache stack corresponds to their order in the corresponding memory stack. A current frame in the cache stack corresponds to the top frame of the memory stack. As described above, address offsets from the base address specifying the top frame serve as keys to the base pointer cache. When the key is presented to the base pointer cache, the cache returns the base pointer in the current frame, which is a copy of the base pointer specified by the address set.

Each time a digital computer system operation adds a new top frame to the memory stack, a new cache frame is added to the cache stack and loaded with copies of the base pointers to the new top frame. The new cache acquisition would then become the current frame. Each time a Operatim the digital computer system the current top Rahme \ removed and the previously top frame running the new! makes the uppermost frame, the cache frame corresponding to the previously uppermost frame becomes the net current frame. The cache stack

is circular: there is a fixed number of frames in that Cache stack, and if the current frame is the last frame in the cache stack and a new top frame to the When the memory stack is added, the first frame in the cache stack becomes the new current frame. To prevent, that new cache stack frames overlap old cache stack frames every time the current frame changes, invalidated the data in the frame above the current frame.

Using a cache stack in the base pointer cache has two advantages. First, if a new one top frame is created, the cache stack frame corresponding to the new top frame by the same Instruction that creates the new top frame so that copies of the base pointers in the new top Frames are available in the current frame of the cache stack upon completion of the command. Second, it is because of this because a number of cache stack frames corresponding to the storage stack frames preceding the top frame, are contained in the cache, generally not required to load a cache stack frame if a previous one The storage stack frame becomes the new top frame.

The cache device further contains a device or a device to quickly invalidate cache frames and a Arrangement of the registers for the base addresses, which enable the base addresses to be output quickly to the combining device permitted.

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It is therefore an advantage of the present invention that aie creates an improved digital gomputerayatem.

Another advantage of the invention is that a Apparatus or a device for caching data is provided which consists of components whose values aioh as Sequence of different operations of the computer system change.

Another advantage of the invention is that it is a device or a device for caching relative addresses achaff, which also consist of a base address component, which is in each call operation and each Return operation changes, and from an address offset component, which only changes with certain call operations and certain return operations.

Another advantage of the invention is that it is a Provides device that responds to operands specifying table entries, base address stores and Address offset encoders included for use The relative addresses calculated from the table entries must be cached.

Another advantage of the invention is that it provides an apparatus for caching using base pointers creates calculated indirect relative addresses.

Another advantage of the invention is that it provides an in-cache device that has a stack and that responds to keys by issuing only data contained in a current frame of the stack are.

Bin another advantage of the invention is that it is a improved device for invalidating cache entries creates ·.

Further features and advantages of the invention emerge from the following description of a preferred exemplary embodiment of the invention with reference to the drawing, which shows essential details of the invention, and from the claims. The individual characteristics can each individually for themselves or several in any combination in one embodiment of the invention be realized.

Brief description of the figures

Pig. Fig. 1 is an illustration showing oaching at shows known computer systems;

Fig. 2 is a diagram showing known operands with shows indirect addressing;

Fig. 2A is a diagram showing a prior art translation points from the operand to the address;

Fig. 3 is a conceptual block diagram of a improved computer system using relative and indirect relative addressing and name tables;

Pig. 4 i3t a representation of names in de α improved The computer system of Figure 3;

Figure 5 is a block diagram of the enhanced address caches; those in the improved computer system of the Fig. 3 can be used;

6 is a conceptual illustration of the logical structure of the argument base cache of the i? Ig. 5;

6A is a conceptual diagram of the logical structure of the source material name cache of FIG Fig. 5;

Figs. 7 and 7A are logic diagrams anticipated Embodiment of the argument base of FIG. 5 show;

Figure 8 is a block diagram showing a preferred one Embodiment of the original material name caohes Fig. 5 shows; and

Figure 9 is an illustration of an exemplary raw material name cache entry.

Description of the preferred. Execution examples

The description of the preferred embodiments begins with an overview of an improved digital one Computer system (ICP, also simply called computer system in the following), which caches data addresses and the the derivation of which permits the required information then shows an overview of a caching device that is particularly can be used advantageously in the computer system, and Finally, it provides a detailed description of a preferred embodiment of the caching device or the Eincachge "äts.

1. An improved digital computer system that supports the Caching of data addresses permitted

The computer system (ICS) is detailed in US patent application Kr. 26,539 »filed on May 22, 1981, and U.S. Patent Application No. 301,999, filed September 11 1981, and in other Pafcentanmldungen related to these patent applications, and it is here only in that described in the scope necessary to understand the present invention.

1.1 Overview of the Compute rays system (ICS) 301 - Figure

3 shows a conceptual blocted diagram of the computer system 301. The computer system 301 has two main components: A memory 305 for storing data η and commands, and a processor 303 for performing operations to the data received from the memory 305 in response to the commands received from memory 305. The processor 303 is connected to memory 305 through a memory output bus 323, the one stored in memory 305 Provides data and instructions to processor 303, through a Memory input bua 341 that carries data from processor 303 to the Memory 305 supplies, and through a memory signal bus 339, the memory signals from processor 303 to memory 305 transported. The memory signals specify at least one memory location in memory 305 and whether the content of the Storage space is to be brought by an access from the memory 305 to the processor 303 or whether data from the Processor 303 must be stored in that memory location.

1.1.1 Content of memory 305:

When the computer system 301 is in the process of executing commands for a user, the memory 305 contains at least the executable code 307 and a stack 317, and it can also contain static data 313. The executable code contains at least one procedure 311 and at least one name table 309. The procedure 311 contains a sequence of instructions that can be executed by the processor 303, and the name table 309 contains information table entries JJTEs (310)

corresponding to certain operands contained in instructions in procedure 311. The one corresponding to an operand NTB 310 contains information from which a descriptor for the data element represented by the operand can be derived. In the computer system 301, a specified Descriptor the address of the data element, its length and other information. The following discussion "deals with now with that part of the descriptor that specifies the address.

Instructions executable by processor 303 include Call command and a return command (return command). if the processor 303 a call command in a procedure 311 executes, it stops further execution of commands in procedure 311 and begins executing commands in a procedure 311 '' specified in the call command •is. When processor 303 executes a return command in procedure 311 ', it stops executing commands in procedure 311' and resumes execution of commands in procedure 311 again.

A command execution of the procedure 311 ¹ begins with the execution of a call command in a procedure 311 'which specifies the procedure 311', and ends with the execution of a return command in the procedure 311 '· If the procedure 311' itself contains a call command, that specifies a procedure 311 ", the execution of procedure 311" is suspended during the execution of procedure 311 "and all other procedures 311" that have been called as a result of that execution. Thus, at any given time, there is only one single procedure whose execution is not suspended, that is, the procedure whose commands are currently being executed.

In addition to specifying the procedure to be carried out 311 ' a call command can also specify arguments that means data available for the execution of the procedure which executes the call instruction, len that execution to the execution of the procedure 311 'started by the call command. Procedure 311 ' in the same Section of Executive Code 30 7 as the Procedure 311 must be included, or in an anterior section of Executable God 307, and she may use the same name table 309 as Procedure 311 or a different one Name table 309

The stack 317 contains a sequence of frames 319 · Each frame 319 contains data that is used in a single execution a procedure 311 can be used. The top frame 321 is a frame 319 which contains data which is currently being used in the execution of the procedure 311 for which the Processor 303 is currently executing instructions. The remaining Frames 319 contain data used in procedures 311 in suspended or deferred instruction executions if a call command is executed in procedure 311 a new frame 319 'is created for the execution of the Procedure 311 'was created which is specified in the call command and the frame 319 'becomes the top frame 321; when executing a return command in procedure 311 ' the execution of the procedure 311 'corresponding to the top frame 321 ends, the deferred execution of the Procedure 311 resumes and frame 319 The uppermost frame 321 becomes again below the uppermost frame 321. The former uppermost frame 321 opens exist, and the area it occupies in memory 305 can be used for new frames 319 or other data will. · ■

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Each frame 319 likes areas for three different types of data included. A local storage area 314 contains data elements whose values change during execution of the Change procedure 311 corresponding to frame 319. A return area 318 contains data elements that are in a Return command can be used to initiate the execution of the dem The procedure 311 'corresponding to frame 319 is terminated in order to complete the Resume execution of procedure 311. An argument pointer area 316 contains argument pointers, i.e. pointers containing the addresses of the data elements that are used as arguments in the call commands that ■ execute the procedure corresponding to frame 319 311 have started. In the computer system 301, only the Call command, the execution of which results in the formation of a frame 319 results in the values of data elements in the return area 318 and the values of the argument pointers in the Set argument pointer area 316; other commands can do not assign values to these areas. As a result, the values of the pointers and data elements in these areas change not during the lifetime of frame 319.

A stack 317 can contain one or more static data areas 313 must be assigned. Each static data area 313 contains data relevant to one or more of the executions of procedures 311 »which have frames 319 on stack 317 are available. The static data area contains areas for two different types of data. The writable static data area 320 contains data the values of which can change during the lifetime of the static data area 313. The link pointer area 315 contains connection pointers, i.e. pointers to

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Procedures 311 and pointers to data elements, iie "at · a Execution of a procedure 311 will be used i that a Frame 319 has on the stack 317, but each in the to Automatic data 3H belonging to that frame 319 still in the writable static data area 313 are included in accordance with the instruction execution. The computer system is in place automatic connection pointer in connection pointer area 315 »when static data area 313 is created is. No instructions to computer system 3'01 allow fourths to be transferred to link pointer area 315 and thus the pointers in the link pointer area change 315 their values during the lifetime of the static data area 313 do not.

1.1.2. Components of processor 303

The components of processor 303 operate under the control of a controller 327. In a present embodiment of the computer system 301, the controller 327 executes sequences of microinstructions. Micro-commands in the micro-commands specify operations performed by the hardware devices which form the processor 303, and decoders decode the microcommands to provide signals which activate or deactivate the hardware devices as required. Controller 32 executes sequences of microinstructions in response to commands from procedures 311 and for signals generated by the processor 303 forming Hardware devices are generated.

For the purposes of the present discussion, the processor has 303 in addition to the controller 327 the following functional elements Departments: an instruction reader 325, an instruction code (opcode) decoder 326, a descriptor processor 329, a memory signal generator 335 and a data processor 337 · The divisions are in the order given above discussed.

Command reader 325

The command reader 325 divides commands into command codes and Operands and puts the opcodes and operands on a name bus 328. The instruction reader 325 also provides one Descriptor for the next command that it is in a descriptor vs 333 brings.

Opcode decoder 326

The opcode decoder 326 receives each opcode from the Instruction reader 325 and decodes it, thereby retrieving the location of the sequence of microinstructions making up the instruction executes. Br provides this memory location to controller 327 which then executes the microinstruction sequence.

Descriptor Processor 329

Descriptor processor 329 receives operands representing data items in memory 305 from the instruction reader 325 via name bus 328 and addressing data from memory output bus 323

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ten pointers and other values used to calculate addresses. With operands corresponding to NTBs 31C, the addressing data include those corresponding to the Nairen NTE 310. Descriptor Processor 329 translates the operands and pointers to descriptors and translates Descriptors in pointers. Descriptors from the descriptor processor 329 are placed on the descriptor bus 333, while pointers from descriptor processor 329 are brought onto memory input bus 341.

Memory signal generator 305

The memory signal generator 305 receives descriptors the descriptor processor 329 and instruction reader 325 · The Store signal generator 305 'responds to the descriptors and signals from controller 327 by adding -ar store signal generated on the memory signal bus 339.

Data processor 337

Finally, data processor 337 receives data items from memory output bus 323, subprocessing them Control of the controller 327 and brings the results to the memory input bus 341.

1.2. Calculation of addresses in the computer system 301

The computer system 301 uses relative addressing. However, the base addresses are not contained in general-purpose registers that allow them to be stored at any time and in to change any rate. In the computer system 301, addresses are set using architectural base addresses calculated. The architectural base addresses of computer system 301 only change when the computer system. 301 one Executes a call command or a return command, and the The way in which they change is beyond the control of the programmer. Instead, it is set by the controller 327 in response to a call or return command executed microcode returns the architectural base addresses, as is the case for the execution of a procedure 311 is required, started by a call command is resumed or by a return command

1.2.1 Architectural base addresses

There are three architectural ones used by computer system 301 Base addresses, namely FP, SDP and PBP. In Pig. 3 show arrows in memory 305 that are labeled with the hams of the architectural. Base addresses are identified by these specified storage locations. PP specifies that lower line of the automatic data 314 in the uppermost frame 321; 3DP specifies the lower end of the writable 3DA 32O in. The static data area 313, which is determined by the Execution of Procedure 311, which can be used by the top frame 321 is represented; PBP represents

a location in the Executable Code 307, the one or more procedures 311 are assigned. Address offsets from FP cannot specify addresses outside of top frame 321; Address offsets from SDP can do not specify addresses outside of the current static data area 313; Finally, address offsets from PBP cannot specify addresses outside of the 311 procedures associated with that PBP. Another The important address is NTP, which represents the storage location of the frame table 309 used by the procedure 311. Address offsets from NTP can only specify storage locations in the name table 309.

The values of FP, SDP, PBP and NTP only change when a call command or a return command is executed by the computer system 301. Since each execution of a procedure 311 has its own frame 319, FP changes every time a call command or a return command is executed, SDP changes every time a call command causes a procedure 311 'to be executed Statisehe data Grebiet used 313, which differs from the command return terminates the procedure 311 that contains the call instruction, or a an embodiment of a procedure 311 'that uses a static data area 313, from that of the Procedure 311 different i3t. PBP changes whenever a call command specifies a procedure 311 'that does not have the same PBP as procedure 311, or a return command terminates execution of a procedure 311' that does not have the same PBP as that of procedure 311. Finally, NTP changes whenever a call command specifies a procedure 311 'that uses a nare table 309 that is used by the procedure 311

ORIGINAL INSPECTED

Sc,

is different, or a. Return command an execution a procedure 311 '"which has a name table 309 is terminated, which is different from that used by procedure 311. Most of the time, calls and returns change in the computer system 301 PP only.

When processor 303 is at it, "instructions" on execution to execute the procedure 311 represented by the uppermost frame 321, the base registers 331 in the Descriptor Processor 329 PP, SDP and PBP. Another register, the name table register 332, contains NTP. The values in these registers only change as a result of execution an up: * uf command or a return command. In the The processor 303 executes a call command Values of those ^ r addresses in these registers, the values of which are Change the sequence of the call command in the return area 316 of the top frame 3-1, which is caused by the execution of the call command gäschaffen was calculated new values for the architect irish base addresses, such as this for the called Procedure 511 'is required and sets the registers to these new values. When executing a return command Processor 303 sets base register 331 and name table register 332 to the values that are in the return area 316 his top frame 321 was saved.

1.2.2 Relative addressing using architectural base addresses

The computer system. 301 uses two different ones Methods of calculating addresses using

'ORIGINAL INSPECTED

architectural base registers. With the direct relative Addressing is the architectural basic address the basic address, and the address offset is calculated and added to it to obtain the address of the data.

In the case of indirect relative addressing, the base address is not an architectural base address, but instead a pointer which is located offset by an address offset with respect to one of the architectural base addresses. The descriptor processor 329 first calculates the address of the pointer, the base address for die.direkte relative addressing as described above, and then calculates the address of the data by adding an address offset to by the pointer i specif ed address.

1 .3 operands in the computer system 3OI - Pi,; ur 4

The operands in the computer system 301 are called names designated. A name may itself specify a base address and address offset, or it may like an NDE 310 which specifies the base address and the air food offset. Figure 4 shows an overview of those features the name 4OI and the name table entrant 310, the. In order to understand the present invention:? are ordered; a detailed discussion of names and name table entries in computer system 301 can be found in U.S. Patent Application No. 301,999.

1-3-1 names 401 in computer system 301

There are two types of names 4-01 in computer system 301, namely table names 403 specifying an NTE 310, and immediate name 409, which is directly an architectural Specify the base address and an address offset. Both types of names 401 contain an NTY PeId 405, the codes that specify whether a name 401 is a table name 403 or an immediate name 409, and if that is The latter applies which architectural base address must be used when calculating the address. The table names 403 have another field, namely the field NT-IND 407, which is the index of NTE 310 corresponding to the table name 403 in the name table 309. The address of NTE 310 corresponding to the table name 403 is obtained by adding the value of the NT-IND field 407 to the value of NTP calculated. The immediate names 409 have two other fields: a DISP field 413 and an IB field 411. The DISP field 413 specifies an address offset with respect to the architeque base address indicated by NTY 405 will. Daa IB-PeId 411 indicates whether the data element in the obtained by adding the specified address offset to the specified architectural base address Address is a pointer to the data item represented by the immediate name, or the data item self.

In an existing embodiment of the computer system 301, the names 401 contain a number of 16 bits. The NTY-PeId 405 contains a two-bit code with the following Meanings:

ORIGINAL INSPECTED

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Code meaning

00 Immediate name; Basis = PP

01 Immediate name; Basis = SDP

10 Immediate name; Base = PBP

11 Table name

In the case of table names 403, the remaining 14 bits form the NT-IND field 407 the other 14 bits the IB-PeId 411 »a reserved bit, and a DISP-PeId 413 with 12 bits. In the present embodiment of the computer system 301, the DISP-PeId 413 contains one represented in two-complement notation signed integer. When multiplied by 32 (i.e. with a left shift by 5 places) the fourth in DISP-PeId 413 supplies the additional address offset Formation of a descriptor from an immediate name 409 required information is taken from the context or Context derived in which the unraittelbire name 409 appears. In other embodiments of the computer system 301, names 401 may have different lengths and other means of specifying a base address and an address offset.

1.3-2 Name table entries (NTEs) 310 in the computer system 301

Name table entry 310, as in Pig. 4 shown, idt. a schematic representation of the four types of information

ORlGINAL INSPECTED

fr.

mation included in an NTE 310 of the present embodiment may contain:

Entry Interpretation Information (EII) 417 specifies such as a descriptor from the one in NTE 310 contained information must be derived.

Basic information (BI) 419 is information from which the descriptor address to be calculated is used used base address can be derived.

Address offset information (DISPI) 421 is one Information from which the address offset used to calculate the descriptor address can be derived.

Descriptor information (DESCI) 423 is information from which another for the descriptor required information can be calculated or obtained.

BI 419, DISPI 421, and DESCI 423 like constants or names 401 or combinations thereof. For example: Specified in an NTE 310 for an element of a field BI 419 the address of the field. It can do this by specifying an architectural base address and an address offset, which provide the address, by specifying an architectural base address and an address offset, which supply the address of a pointer to the field, by means of an immediate Namer-a 409 »which is the base address supplies, or by means of a table name 403, which is based on

a ΝΤΕ 310 in the same name table 309. That one NTE 310 contains information that provides the address of the field. DISPI 421 in an NTE 310 for a field element mag contain a constant value representing the scope of the field element specified, and a name 401 which supplies a descriptor for data, the value of which is the index of the field element is. DCI 421 may contain a constant specifying length, or it may contain a name 401, which supplies a descriptor for data whose value is length.

T.4 Name resolution in the computer system 301

Name resolution is the operation performed by descriptor processor 329 when it derives a descriptor for a data item represented by a name 401 from the name 401 using of the architectural base addresses contained in the base registers 331, of pointers, and in the case of a table name 403 of the NTE 310 for the table name 403 and from

NTEs 310 for any table names 403 contained in that NTE 310

In the case of an immediate name 409 that directly specifies a base and an address offset, the resolves Descriptor Processor 329 to immediate Naiien 409 by adding the address offset specified in DISP field 413 to the content of the register in the base registers 331 which is specified by the NTY field 405 Contains architectural base address.

In the case of an immediate name 409 ', its IB field 4-11 indicates that the base is being specified indirectly, the descriptor processor 329 obtains the address of the by data specified by the immediate name 409 ' Addition of the address offset specified in the DISP field to the architectural base address as specified above to get an address and then the pointer to be retrieved from memory 305 at that address. The pointer is then used to form the descriptor.

The descriptor processor adds in the Pall ^ on table name 403 329 the value of the NT-IND field 407 to the value in Name table register 332 to get the address of the NTE 310 corresponding to the table name 40;) calls the NTE 310; i from memory 305 and then derives the address of the data element represented by the table name 403 the end; the information contained in the NTE 310 in the W e advances through the EU field 417 and the content of the NDE. If NDE 310 immediate names 409 or contains tab names 403, they will be resolved in the manner just described.

2 · Cache addresses in computer system 301.

The following are the properties of addresses in Gomputeraysten 301, which make them cacheable, and an overview of an improved cache device that can be used for the Cachea of addresses used in a present embodiment of computer system 301 is given .

2.1 Cacheable addresses

In known computer systems in which the base addresses were obtained from general-purpose registers, addresses obtained by adding a constant address offset to a base address could not be cached in operand-responsive caches because the values of the base register «· *. could change at arbitrary times and in arbitrary ways. In the computer system 301, such addresses can be cached in caches responding to names 401 because the architectural base addresses and M ¹ P change their values only when a call command or a return command is executed. The addresses in the cache therefore remain valid at least during the period between the execution of a call command or a return command and the execution of another call command or. Return command. Addresses that remain valid during this period are referred to herein as cacheable addresses.

Cacheable addresses are generated in the course of each name resolution operation. In some cases it is the address of the data represented by name 401 cacheable; in other cases this address cannot be cached, but intermediate addresses used to determine that address can be cached.

Ea are two cases where the address of the Name 401 represented data can be cached:

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If so, an immediate name 409 or an NTE 310 for a table name 403 an architectural base address 3S3e and specifies a constant address offset.

If an immediate name 409 or an NTE 310 is a constant address offset and a base address specified which is a pointer to a negative Address offset compared to FP or SDP.

In the latter pail are those by adding the constants Adrea.3enveraätze to the pointers calculated addresses can be cached, because the pointers keep their values during the lifetime of the static data area 313 or the one containing them Frame 319 does not change, and PP and SDP only differ when the execution of a call command or a return command change.

In all other cases only intermediate addresses can be cached. BispLelaweise can then, if a direct Name 409 specifies a pointer as the base address, and if the pointer is opposed to a positive address offset PP or SDP instructs to change the value of the pointer. Clear addresses derived from learning pointers cannot be cached. However, the pointer has a constant address offset against an architectural base address, and hence the address of the pointer is cacheable. Once the Pointer address is cached, the descriptor processor 329 can obtain the immediate name 409 by retrieving the pointer au3 resolve the memory 305 at the memory location specified by the cached address.

2.2 Cache device for cacheable addresses ι

To take full advantage of cacheable addresses, a present embodiment uses a computer system 501 a special cache device or a special one Cache device. The following discussion first describes the limitations of the known cache device, if used for cacheable addresses and then describes the cache device that is used for user - / *** ■ cacheable addresses or in other situations where cacheable values depend on other values that are not subject to arbitrary changes, is particularly suitable.

2.2.1 The known device in the computer sysbem 301

The utility of the known cache device or apparatus in embodiments of the computer system 301 is limited by two facts:

Cacheable addresses depend either directly or indirectly on values of PP, PBP, SDP and NTP, and these values are when running each ;? Call or return commands are subject to change.

In modern programming practice, large programs Constructed from a large number of short procedures, and call and return commands occur often on.

© RIGJNAU INSPiECTED

In a prior art cache device, a Cache entry that is accessed by a key is either invalid or contains completely calculated Addresses; consequently, if one is used to calculate the Addresses value used changes, the entry accessed with the key will be made invalid. Thus, if the prior art cache device contains cacheable addresses, all cache entries that FP contain derived cacheable addresses, are invalidated each time a call or return command and cache entries that contain cacheable addresses derived from PBP or SDP must always be invalidated when a call command or a return command changes those values. However, it is impossible to say which of a cached address the base register 331 is used in generating the adrease and it is also impossible to tell of a table name 403 which base registers 331 its NTE 310 must be specified. Thus, when cachable addresses are cached in the prior art caching device, all cache entries are required To be invalidated whenever a call command or a return command is executed. Since these commands start with occur at high frequency in programs executed by the computer ayatem 301, the cache entries are at the cache facility generally invalid in the prior art, and most of the benefits of caching go lost.

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2.2.2 Improved address caches in the computer system 301 Figure 5

. 5 provides a conceptual illustration of an improved address cache 501 used in one embodiment of computer system 301. In the pig. 5, solid arrows indicate input signals, input signals or output signals from the improved address caches 501, and dashed arrows indicate control signals. The improved address caches 501 make advantageous use of three properties of relative addressing in computer system 301:

The address offset is constant for cacheable addresses, and only the base address is influenced by the execution of call commands and return commands. The relationship between a name 401 and a constant address offset remains unchanged as long as the name table 309 is still used. Venn Namentaballe a new 309 replaces the earlier name table 309, NTP changes its rfert. This means that cached addresses / replacements do not have to be made invalid, unless the execution of a call command or a return command changes the fourth of NTP.

Addresses consisting of argument pointers and Vsrbinding pointers and constant address offsets can be derived, are during the lifetime of the ra-imen.j 319 or of the static data area 313 »which contains this, cacheable.

Ar, * umentzeiger serve in a given frame 519 al.3 Baaiaadreaaen only if FP that frame 319 is specified, and connection pointers in a given static data area 313 are set in the computer system 301 is only used if SDP specifies that static data area 313.

The improved address caches of the present embodiment of computer system 301 take advantage of this the first property by caching basic addresses that can be cached separately from the constant address processing values and then add the cached address offset to the cached base address to generate the relative address. The address offsets are contained in a Raw Materials Name Cache (RMNC) 517, the Table name 403 used as key. The RMNC 517 will ao because it contains Uraprunga materials from which addresses can be formed.

The base addresses are contained in two base address caches. One, the Architectural Base Register Cache (ABRC) 504 contains the current values of FP, SDP and PBP. The other, the Baaiscache (ABC) 502 argument, contains base addresses, the pointers contained in Ln in frame 319 are derived are. The ABC 502 uses representing argument pointers immediate name 409 as a key. As explained above specify these immediate names 409 only Argument pointer in top frame 321. In response to these immediate names 409, ABC 501 generates addresses that aas argument pointers specified by these direct names 409 can be derived. The address book

--33345

Code3 assigned to sentences in RMMG 517 specify which of the base address cache contains the base address which is combined with the address offset. If the code specifies an argument pointer as the base adrease, then is; The address offset is further assigned a key to which the ABC 501 responds in the same way as it responds to an immediate Hamen 409.

The improved address caches make advantageous use of the second and third properties, as will now be explained: First, because SDP is very much changes less frequently than PP, and because the connection pointer their fourth never change, complete addresses derived from the connection pointers together with the address offsets in the RMNC 517 cached. The RMN 517 will thus · each time completely invalidated when SDP, PBP, or NTP changes. Second, because the argument pointers never change their values, the ABC 502 does not just contain argument pointers au3 the top frame 321, but aach argument pointer from frame 319 below the uppermost frame 321. He therefore does not have to be invalidated when executing each return command.

2-3 Overview of the improved address cookies 501 in computer system 301

Ü3 is now Pig. 5 considered in more detail; there will be first the relationship between the improved address caches 501 and the coraputer system 301 is described, and then the structure and operation of the improved address caches 501 are described.

2.3-1 Correlation of the improved. Address cache 501 with the computer system 301

The enhanced address cache 501 is in the descriptor processor 329 of the computer system 301 included. The improved Address caches 501 receive names 401 via name bus 328. Names of fields in names 401 appear as marks on input signals for components of the enhanced address cache 501 in FIG. 5 to indicate which Sections of a name 501 are received by that component. The improved address caches 501 provide addresses and other data to descriptor processor 329 via descriptor bus 333 · A cache load bus 527 within descriptor processor 329 enables caches in the improved address caches 501 to be created with data elements from the Memory 305 and with by descriptor processor 329 generated values are loaded. The enhanced address caches 501 operate under control of the controller 327 and 327 of signals generated by CTL 515 in response to name 401, hit signals from ABC 502 and KMNC 517, and in the Codes contained in RMNCEs 519 ". Sequences of microinstructions again performed by controller 327 in response to signals from CTL 515 and to codes contained in RMNCEs 519.

2 x 3 x 2 components of the enhanced address cache 501

The major components of the improved address caches 501 are the following:

/ 104.

The ABC 502, which has two main components: BAC addressing logic 533 and ABC registers The ABC registers 504 contain ABC entries (ABCEs) 503, in which base addresses are stored from argument pointers contained in stack 317 are derived are. The ABC addressing logic 533 derives addresses in the ABC registers 504 from keys which they either from name bus 328 or from EMC 517. The ABC 502 responds to the key by sending base addresses to a base multiplexer 511 and ABC hit / miss signals to the CTL issues. The ABC addressing logic 533 also likes the address of the ABC entry 503, which was last given by the Descriptor bus 333 was addressed.

The ABRC 504, which contains three registers: FPR 505, the contains the current TSfert from PP; SDPR 507, which supports the contains current value of SDP; and PBPR 509, which contains the current value of PBP.

RMNC 517, which contains RMNC entries (RMNCEs) 519 and responds to key from name bus 328. The RMNCEs like constant values that are used to calculate address offsets can be used or derived from the connection pointers complete addresses included. The RMNC 517 outputs an RMNC hit / miss signal to CTL 515, and at a hit signal can send data from an RMNCE 519 corresponding to a key directly to the descriptor bus 333, or parts of an RMNCE 519

can be output to address offset multiplexer 525, OTL 515, ABC 502, and controller 327 will.

A name control (Name Trap) 531> which the value of the last name 401 entered into enhanced address caches 501;

An address adder 513, the base addresses obtained from the base multiplexer 511 and those from the Address offset multiplexer 525 received address offsets added, or either a base or an address offset can pass unchanged.

A base multiplexer 511 which selects a base address given by the ABC 502 or one of the registers 505 to 509 is output from the ABRC 504.

An address offset multiplexer 525 that has an address offset value falls out of the address offset, selects an RMNC 515 or from the name bus 328.

A CTL 515, which receives input signals from name bus 328, from the RMNCE 519 specified by a key, from the RMNC 51? and receives from the ABC 512 and on those Input signals by generating control signals for the base multiplexer 511, the address offset multiplexer 525, the address adder 513 and the controller 327 responds.

2.3 · 3 Mode of Operation of the Improved Address Caches 501

Generally speaking, the improved address caches work 501 as follows: If a name 401 is on the name bus appears, CTL 515 receives the NTY field 4-04, the IB field 411 and certain bits of the UISP field 413. CTL 515 determined the values of these fields to which of the following classes a name 401 belongs:

Immediate names 409> die an architectural Specify the base register as the base.

- Immediate names 409, which take an argument pointer as a specify a base

Immediate names 409 that have a writable pointer specify as a basis.

- Table names 403.

The discussion first turns to the operation of the enhanced address caches 501 in response to immediate Frame 409 and then with its operation in response to table name 403.

2.3 · 3 · 1 Mode of Operation of the Improved Address Caches 501 in response to immediate names 4-09

In the case of an immediate name 409, which is an architectural

real base register specified as a base speaks GTL 515 on the NOJX field 405 of the immediate name 409 by causing the base multiplexer 511 to select the register in ABRC 504 that has the current value of the architectural base address specified in the immediate name and it causes the Address offset multiplexer 525, the DISP field 413 of the immediate Name 409. The address adder 513 then adds the value from the specified register in the ABRC 504 to the value from the DISP field 413 to obtain the through to generate the immediate name 409 specified address. In the present embodiment of the computer system 301 converts the address offset multiplexer 525 also converts the DISP field 413 to a 32-bit value. He does this by shifting the DISP field 413 by five places to the left and by adding characters to the resulting value to 32 bits.

In the case of an immediate name 409 specifying an argument pointer, then, if the received by the Argument pointer specified address in ABC 502 cached is, CTL 515 is a hit signal from ABC 502 and responds to the hit signal and the NTY, IB, and DISP fields of the immediate name 409 by causing the base multiplexer 51Ί to select ABC 502 and the address adder 513 the value received from the basic multiplexer 511 unchanged to descriptor bus 333.

In the case of an immediate name 4-09 that has a writable Pointer specified as a base, that is, a pointer to a positive address offset with respect to SDP or FP, the writable pointer cannot be cached. CTL 515 represents the positive value of DISP field 413 fixed and generates a signal for the controller 327 · Die through the controller 327 in response to the signal executed microcode sequences extracts the immediate name 409 the name control or name trap 531 again uses the architectural specified by the NTX field 405 Base address and the value of the DISP field 413 to form the address of the pointer, and then fetches the pointer from memory 305 and converts it into a descriptor for the data represented by the immediate name 409.

2.3.3.2 Mode of operation of the improved address caches 501 in response to table name 403

In the case of table names 403, the behavior of the improved address caches 501 depends on codes that are in the EMNCE 519 are contained, to which the table name 403 is accessed. If there is an SMNCE 519 corresponding to a table name 403 and the table name 403 corresponds to the BMNC 517 is offered, the code is in the table name 403 corresponding RMNCE 519 is output to CTL 515. The code then determines the manner in which the enhanced address caches 501 respond to the table name 403.

The code contained in an HMDTCE 519 is supported by the Microinstruction sequence set that loads the EMEJCE 519.

The simplest case is an EMNCE 519 for a table name 4-03, which represents a connection pointer. the end Addresses derived from connection pointers are completely cached in EMITCE 519, and so CTL 515 responds to the such an EMITCE 519 specifying code by it causes address offset multiplexer 525 to select EMITC 517 and causes address adder 513 to do the Input signal from the address offset multiplexer 525 unchanged to descriptor bus 333 passes.

If the EMITCE 519 contains a constant address offset, to one of the architectural base addresses for If the desired address is added to the generation of the desired address, the code further specifies which base address is to be generated the address must be used. CTL 515 answers to the code specifying that type of entry by causing the base multiplexer 511 to open the register of the ABRC 504- selects the specified base address contains, and by causing the address offset multiplexer 525, the RMC. to select. The address adder 513 then adds the base address and the address offset to generate the address represented by the name.

If EMNCE 519 contains a constant address offset that is added to a base specified by an argument pointer to generate the address, then HMITCE 519 also contains a value which is equivalent to the DISP-FeII of an immediate Hamens 413. This value is output to ABC 502. When a table name 40 5 appears on name bus 328, ABC 50 selects RMNCE 519 as its input and outputs the value of ABCE 503 corresponding to the value received from EMNCE 519. As with other types of EMNCE 5I9, the code specifying the type of EMNCE 519 is output to CTL 515 which "responds" by causing base multiplexer 511 to select ABC 502 and address offset multiplexer 525 to select EMNC 517 selects. The result is that address adder 513 adds the constant address offset value cached in EMNCC 519 to the address indicated by ABC. ^[ 502 was generated in response to the value it received from that BMNCE 519.

In more complex cases, EMNCE 517 contains information from the addresses can be derived from micro-command sequences can. This information is output to the control 327, the subsequent execution of the EMNCE 517 specified microinstruction sequence responds. The specified Microinstruction sequence uses the contents of EMNC corresponding to the table name 403 to construct the address represented by table name 403.

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For example, when using the address offset of the address represented by table name 403 from data stored in memory 305 are included, the BMNC entry 519 may accordingly the table name 403 itself a representing the data Table names 4-03 'included, and those by GTL 327 selected microinstruction sequence may compute the address offset by sending the table name 403 'to BMWC 517 supplies, in order to obtain the address of the data, that it fetches the data from the memory 305 and sends the data to the Calculation of the address offset used.

If, as described above, no valid ABGE 503 accordingly one from the name bus 328 or the BMNC 517 received key is present, receives. CTL 515 a Missing signal from ABC 502. CTL 515 replies to the Missing signal (Miss signal) by supplying a signal to the controller 327, to which the controller 327 by executing responds to an ABC miss microinstruction sequence. Under The descriptor processor 329 receives the address of the valid ABCE 503 from the control of this microinstruction sequence ABC addressing logic 533 via the descriptor bus 333, uses the address to form the immediate name 409, that caused the miss uses the immediate name 409 to locate the one caused by the immediate Names 409 represented argument pointers in the top one Frame .521, and then uses the address to load the argument pointer m to the appropriate location in ABC 502.

GKusMÄt INSPECTED

i-:

:. ": 33345

After that, the operation that caused the false signal becomes has repeated.

Similarly, if not a valid BMCE 519 receives accordingly a table name 403 is present, GTL 515 a feble signal from the EMNG 517 and generates a signal to the the control 32? by executing an RMNC ehl microinstruction sequence answers. Under control of this sequence of microinstructions, the descriptor processor 329 wins the table name 403, which caused the faulty signal, from the Name control 531 again, calls NTE 310 according to the Table names 403 from memory 103, uses the Table names 403 to locate the corresponding RMNC entry 519 and makes a BMCE 519 using of the data contained in the NTE 310. Once the BMNC entry 519 is loaded according to the table name 403 is, the operation that is causing the error signal becomes has repeated.

2.4 Invalidation in the improved address caches 501

In the improved address caches 501, FPR '505 must be updated every time a call or return command is executed, and SDPR 507 and J ³ BPR 509 must be updated every time a call- or return commands require that they be changed.

In ABC 502 a complete validation is so long not required, as computer system 301 does Stack 317 used. When executing a call command addresses must point to ABC 502 according to the arguments arranged in the uppermost frame 321 loaded, but the argument pointers in the earlier Frame 519 does not change its values, and therefore exists no need to use the ABCEs 503 invalidate. Since the argument pointers from earlier frames 319 are kept in ABC 503, the Return command merely retrieves the argument pointers from the invalidate previous top frame 321 containing ABCEs 503

In the RMNC 517 a full invalidation is only done required if the execution of a call or return command changes the value of SDP, PBP or NTP, or when the computer system 301 needs a new batch. Complete addresses in the RMNCEs 519 will be never derived from JTP and therefore they do not become invalid if EP changes. The RMNCEs 519 that only Contain address offsets are only invalid if a call or return command calls a 311 procedure or returns to it, which has a name table 309 different from that of procedure 311 which controls the Contains call or return command, or if the computer system 301 is executing a program that another Stack 517 used. Calls and Returns that are PP only

change are far more frequent than other calls and returns, and calls and returns that change more than PP often change more than one of the addresses PBP, SDP or NTP. Consequently, in a present embodiment of the computer system 301, EMNC 517 is always invalidated when the computer system 301 executes a program that uses a different stack 317, or when a call or return brings about ^{more than one change in the value of I 1 P.} In other embodiments EMCTC 517 may not contain complete addresses, and in such embodiments RMKC 517 need only be invalidated if a call or return command requires a different name table 309 or if the computer system 301 is executing a program, that uses another stack 317

Other Embodiments of the Improved Three-Way Caches may contain separate caches for cacheable pointers that are different from the argument pointers. Such Caches could be shared with the base multiplexer 511 connected to ABC 502 and ABRC 504, and could Keys from name bus 328 or EMNC 517 in the same Way like ABC 502 received. Codes in the RMNCEs 510 could also select such additional caches as the sources of base addresses *

ORIGINAL INSPECTED

2.5 Detailed logical structure of ABC 502 and BMC 517 - Figures 6 and 6A

The discussion now turns to the detailed logical structure of ABC 502 illustrated by FIG is, and that of the EMNC 51? » the through the • Fig. 6A is shown.

2.5.1 Detailed logical structure of ABC 502 - Fig. 6

Fig. 6 shows the detailed logical structure of the ABC 502 and illustrates the relationship between the ABC 502 and the stack 317- Fig. 6 contains a representation of the contents of the ABC 502, namely a representation of the ABC content 613, a detailed representation of the running ABC frame 6Ο7 in a detailed representation 615 ₅ and a representation of the stack 317

First, consider the ABC content 613. The ABC 502 consists of ABC frames 603. Each ABC frame contains a number of ABCEs 503 · In a present embodiment the ABC 502 has 16 ABC frames 603, and each ABC frame 603 contains 16 ABCEs 503. The number the ABC frame 603 in ABC 502 and the number of ABCEs 503 in a frame may in other embodiments may be different, and in some embodiments likes the number of ABC frames 603 and the number of

copy

"h za ABGEs 503 in an ABC frame 6Ο3 not i'esi ;. Each ABCE 503 contains two separately loadable fields: An address field 609 contains an address that is derived from an argument pointer if ABCE 503 is valid and a .validity (V) -PeId 611, which indicates whether ABOE 503 is valid. If all ABCEs 503 forming an ABC frame 603 are invalid, then this ABC frame 6Ο3 is invalid.

Each valid ABC frame 6Ο3 corresponds to a frame 319 in the stack 317 · The current ABC frame 607 corresponds to the top frame 321, and the ABC frames 603 below the current ABC frame 6Ο7 correspond to the frames 319 below the top frame 321. So Corresponds ": in Fig. 6 the ABC frame 6Ο3 (4) to the frame 319 (1), the jJ3C frame 603 (3) to the frame 319 (2). j ^u * Ld so on. Within an ABC frame 6Ο3 addresses specified by argument pointers in frame 319 corresponding to ABC frame 603 are arranged in an order corresponding to that of the argument pointers in frame 319. In detail 615 of the current ABC frame, arguments own 601 are in the top frame in the sequence 601 (0), 601 (1) and 601 (2), and in the current ABC frame 6Ο7, the ABGEs 503 containing addresses from these argument pointers 601 are arranged in the same order. However, each corresponding order is, for example one to the order in the frame n 319 reverse order, possible 1.

. COPY

ABCEs 5 ⁽⁾ 3 »<ϋβ contain no address are invalid, and if an Estinnen 319 contains more than 16 argument pointers 601, only addresses from the first 16 are cached in the ABC frame 603. CTL 5 ^ 5 detects immediate warnings 409 specifying argument pointers 601 that cannot be cached in ABC 502 from the value of DISP field 413 and responds to such immediate names 9 by causing controller 327 to generate a microcode to execute 'similar to that described in the discussion of immediate names 409, Ä. ± a specifying writable pointers as base addresses. The next ABC frame 605, above the current ABC frame 607, is always invalid. Thus, in the present exemplary embodiment, ABC 502 can contain addresses from argument pointers only in the top 15 frames 319 of the stack 321. The stack in ABC 502 is closed in a circle; that is, if ABC frame 603 (0) corresponds to frame 319 (a), then ABC frame (15) corresponds to frame 319 (a + 1).

When processor 303 executes a call instruction, Addressers corresponding to argument pointers 601 for the in the Call-i-command arguments used in the next ABC frame 605 loaded. Then the next ABC frame 605 becomes the new current ABC frame 607, and the ABC frame 603 above the new current ABC frame 607 is invalidated by moving it to the new next ABC frame 605 power. When a return command is executed, the

ABC frame 603 below the current ABC frame 6Ο7 of the new running ABC frame 6Ο7, and the previous running ABC frame 607 is invalidated by adding it to the makes new next ABC frame 6Ο5 · Thus, the current ABC frame 6Ο7 always corresponds to the top frame 321.

As mentioned above, the DISP field 4-13 of the immediate names 409j specifying the argument pointers 601 as bases is used as the key for ABC 502. All argument pointers 601 that can be specified by the DISP field 413 are contained in the uppermost frame 321 corresponding to the current ABC frame 67, and consequently only the current ABC frame 6Ο7 responds to the keys. Because the vert of the DISP field 413 depends on the storage location of the argument owner 601 in the top frame 312 and the order of the addresses in an ABC frame 603 that of the arguments show ¹ ? 601 in frame 319 corresponds to the ABC frame 603, the DISP field 413 can be used to directly address the -U3CEs 503 within the current ABC frame 6Ο7. If the ABCE 503 addressed by the DISP field 413 is valid, it contains the address from the argument pointer 601 specified by the immediate name 409.

In a present embodiment of the computer system 301, only bits 8 through 11 de ;; DISP field 413 used as a key to the ABC 502. The less significant bits of DISP field 413 are not needed because

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the argument pointers 601 in the computer system 301 with negative address offsets with respect to FP are stored, which are divisible by 128 without Best. In two complement notation, which is used in the DISP field 413, Address offsets of argument pointers 701 have zeros in their seven least significant digits. Bit 12 of the DlSP-Jj'elds 413 is not required because it is an ABC frame in the preferred embodiment 701 no more than 16 can hold argument pointer 601.

If the ABCE 503 specified by the DISP field 413 is valid, ABC 502 outputs a "hit" signal to CTL 515; if this is not the case, ABC 502 emits an error signal and CTL 515 generates a signal on which the controller responds responds by having an ABC miss microcode sequence code using the value of DISP field 413, to reconstruct the immediate name 409 that caused the miss signal use that immediate Name 409 to locate the argument owner 601 represented by immediate name 409, and loads the address derived from the argument pointer 601 in the appropriate ABCE 503 in the current ABC picture 6Ο7. Veil Addresses in the current ABC frame 6Ο7 are loaded when executing a call »command, such false signals occur only on if the result of a return command is an invalid ABC frame 603 for the current ABC frame 607 or if any operation of processor 60-j requires invalidation of all ABC frames 603 has made.

2.5.2 Logical structure of the EMNC 519 - Figure 6A

The BMNG 519 includes a plurality of EMNCKs 519. The logical form of the EMNCE 519 is at a preferred Embodiment of the present invention: shown in Figure 6A. Each EMNCE 519 consists of four EHNCE enthusiasts 627, referred to herein as EMNCEE 627 (0 ... 3) ". In addition, a set of control fields 620 is the EMNCEE 627 (0) assigned to each EMNCE 519. A valid one EMNCE 519 corresponds to a single NTE 310 in the name table 309 being used by procedure 311 which is currently being executed by processor 303. The EMNC 519 becomes the valid EMNCE 519 through the Accessed table name 4-03 specifying NTE 310, to which the valid EMNCE 519 corresponds. An address can be generated from the data contained in a valid EMNCE 519 in two ways: Directly from the data in the BMNCEE 627 (0) and by means of a microcode intervention from data stored in each EMNCEE 627.

2.5 2.1 Direct generation of addresses from the EMNCEE 627 (0)

If an address is obtained directly from the BMNCEE 627 (°), different fields go from EMNCEE 627 (0) and Control fields 620 to different parts of the enhanced address cache 501. The fields and their destinations or destinations

are the following:

A. Address offset field 629 which is output directly to address offset multiplexer 525.

A. Base field 641 which is output to the CTL 515 will. The base field 641 contains two subfields:

a) A BS field 635 that contains a value that represents the ABH, if available, is specified that must be used when creating the address.

b) A (6) field 637, ias indicates that the base is a Pointer is.

An ADISP field 639 containing bits 8 to 11 of the DISP field that leads to an immediate Famen 409 belongs to an argument pointer 601 represented in the NTE 310 corresponding to the BMTiTCE 519. The ADISP field 639 is output to the ABC 502, and if the base field 641 so specifies, the contained in the ABCE 503 according to the ADISP field 639 Address used as the base address.

The control fields 620 control the manner in which the enhanced address caches 501 store the information in the BMCE 519 under the control of the CTL 515 or by the controller process executed microinstructions. The subfields

_ ", 33345

V / t «1.

are the following:

An ABOF field 621 indicates whether the name 401 is appropriate dem, EMNCE 519 is resolved using of the ABC 502 and also of the EMNO 517. The ABCF field 621 is output to CTL 515.

-. JDaä V-Field 622 indicates whether EMNCE 519 is valid and is output to CTL 515.

The ID. Field $ 62 contains data from which the Controller 327 a sequence of microinstructions for processing des. Contents of the EMCE 519, for which the ID field 623 heard, localized. The ID field 623 is output to the controller 327.

The BC field 625 contains a copy of the base field 64- < in EMEfCEE 627 (0) and is output to CTL 515. CTL 515 responds to BC field 625 in that it selects targets for the output of EMNCEE 627 (0) as indicated by the contents of EMNCEE 627 (0) is required.

6A includes an exemplary EMNCEE 627 (0) and its associated control fields 620. The exemplary EMNCEE 627 (0) corresponds to an NTE 310 which has an address specified with a constant address offset with respect to an argument pointer 601. The address offset

ORiGINAL INSPECTED

field 629 contains the vert of the constant address offset, the BS field 655 contains the code 00, which specifies IT, the (S) field 657 contains the value 1, whereby it indicates an indirect reference, and the ADISP field 659 contains a negative value specifying the address offset of the argument pointer 601 from FP. In the control panels 620 specifies ABOF that ABC 502 will supply the base address, the V field 622 that the entry is valid, and the ID field 625 "that no microcode intervention" is required will. The BC field 625 contains a copy of the base field 641.

If a table name is 4-05 according to the EMNCER 627, the the exemplary RMNCER 627 (0), which is provided overall with the reference numeral 645, is input to the RMNC 517 the following happens: The ABCF field 621 and the BC field 625 are output to CTL 515, the ADISP field 659 is output to ABC 502 and the address offset field 629 is passed to the address offset multiplexer 525 issued. The ABC 502 outputs an address in response to the ADIilP field 659, and CTL responds to the BC field 525 in that it causes the base multiplexer 511 Selects ABC 502 as its input, and the address add? 515 adds the value of the address offset field to the base address issued by ABC 502.

2.5 · 2.2 Generation of addresses from the HMNCE 519 with microcode intervention

By controller 327 in response to codes in ID 623 executed microinstruction sequences can the contents of each EMNCER 627 in an EMNCE 617 according to the Table name 403, which is currently on name bus 328 can be used in two ways: By allowing the devices and facilities of the improved address caches 501 is supplied as an input signal, and in that it is output directly to the descriptor bus 333. In the first Pail, EMNCER 627 contains the address offset field 629, the Base field 64-1 and the ADISP field 639. The code in the base field 641 is output to CTL 515 and determines how the Devices and facilities of the improved address caches 501 process the content of EMNCER 627. For example, would an RMNCER 627 »whose fields are set in the same way as in the" exemplary EMNCER 627 (0) 643, in the same way Way to be processed. In the second case, RMNCER is treated as a single field that is sent directly to the descriptor 333 is issued.

3 Detailed description of a preferred embodiment of the improved address caches 5C1

The following are detailed descriptions of preferred Embodiments of all components of the improved address cache 501 are given.

3.1 Description of a preferred embodiment of GTL 515

Cl ¹ L 515 consists of standard logic elements. The manner in which the CTL 515 responds to inputs from the name bus 328, the RMIiC 517, and the ABC 502 has already been described. The technique of combining standard logic gates to achieve the functions described is well known to those skilled in the art and CTL 515 is therefore not described further here.

3.2 Description of a preferred embodiment of the ABRC 504

In a preferred embodiment of the ABR (J 504-can Ji ¹ PR 505 »SDPR 50y and Ji ¹ BJr ¹ R 509 each consist of four TM.state-D flip triops with 8 bits from

Type 74-S374 exist. The input signals for each of the Registers 505 to 509 come from cache load bus 527 and the Output signals go to the base multiplexer 511. The registers 505 to 509 are always activated for reading. To the Writing is activated under microcode control. FPR 505 goes to FP for a new top frame 321 set by microcode sequences executed in response to all call and return commands; if PBP or SDP as a result of a call command or a Return command changes, set microcode sequences, which executed in response to those call and return commands will return, SDPR 507 and PBPR 509. With others "

Embodiments may implement ABRC 504 using a ram including registers 505 through 509 and a single connection between base multiplexer 511 and ABRC 505. The use of separate flip-flops for the registers 505 to 509 and of separate connections between the flip-flops and the base multiplexer 511 makes it possible to activate all registers 505 to 509 continuously for reading and thereby eliminate a delay caused by the need the addressing of a single register of the RAM. \

3.3 Detailed description of the base multiplexer 511 and the: address offset multiplexer 525

A preferred embodiment of the basic multiplexer may consist of 16 double 4: 1 line multiplexers of the type 74S153 exist. Each multiplexer receives and delivers two-bit inputs from the ABC 502, FPR 505, SDPR 507 and PBPR 509 a two bit output to address adder 513.

A preferred embodiment of the address offset multiplexer 525 may consist of eight quadruple 2: 1 line multiplexers (quad 2-to-1) of type 74S258 exist. Each multiplexer receives 4 bits of the input signal from the RMNCERs 627 and 4 bits of the input signal, which consists of bits from name bus 328 and bits that are always set to 0. Every multiplexer there 4 bits of the selected input signal off, or if no input signal is selected, it outputs 0.

• i

• *

■ fr

• «

In the present embodiment, the address offset multiplexer receives 525 an input signal from the name bus only if an immediate name 409 is on the name bus 328 is · In this case the input signal is that DISP field 413, and the address offset multiplexer 525 creates a 32-bit address offset by actually shifting DISP field 413 5 bits to the left and Character completion by 15 bits to the left. The shift operation is a consequence of the way in which the input signals from name bus 328 to the address offset multiplexer. The 16 most significant bits used by the Address offset multiplexers 525 received from name bus 328 come from bit 4 of name bus 328, which is the most significant bit of DISP field 413 transported. the The next 11 most significant bits come from bits 5 to 15 of name bus 328, the remainder of DISP field 413 transport. The remaining 5 bits are received from grounded inputs and therefore always have the value 0.

3.4 Detailed discussion of a preferred embodiment of the address adder 513

The address adder 513 is a 32-bit adder with carry look ahead. The adder mag consists of eight 4-bit ALUs of the 74S181 type and three look ahead carry generators from Type 74S182 exist. In the present embodiment

ό 3 3 4 b 7 9

the adder is always activated to one of two functions to run: The one from the address offset multiplexer received value unchanged on Deskripcorbus 330 or to pass the value received from the address offset multiplexer 525 to that from the base multiplexer Add 5 * 11 received value. Because the address offset multiplexer 525 generates the vert O if none of the Input signals is selected, the adder 513 can actually the value received from either the base multiplexer 511 or the address offset multiplexer 525 unchanged let through to descriptor bus 533.

3.5 Detailed Discussion of a "Preferred Embodiment of ABG 502 - Figs. 7 and 7A

A preferred embodiment of the ABC 502 is given in Figures 7 and 7A. Fig. 7 contains a preferred embodiment 701 of the addressing logic 533j and Fig. 7 ^ contains one preferred embodiment 772 of the ABC register 5Ο4-. Under Referring to these figures, an overview of the components and operation of the "preferred embodiment" is first provided given by ABC 502 followed by a detailed: lated discussion of its components and working methods.

3.5.1 Input signals for the preferred embodiment 7C the addressing logic 533

The behavior of the preferred embodiment of ABC 502 ·. is controlled by input signals from two sources: _from

Microinstructions and the name bus 328. Vie man in Pig. 7 can be seen in the preferred embodiment for the addressing logic micro-commands that the ABC 502 affect, through the ^ RMREG line 724 and through two Receiving decoder: MDA 702 and MDB 703. The MDA 702 and MDB 703 have three bits of the micro command as input signal and lines 705 "to 717 as outputs. Hur one lines 705-715 is at any given time inactive; the remaining lines 705 to 715 are active. Which of the lines 705 ″ to 715 is inactive is indicated by the three bits of the microcommand input signal for the MDA 702 and MDB 7O3. In the preferred addressing embodiment 7OI are the MDA 702 and MDB 703 8.1 decoder.

Control inputs from name bus 328 are obtained from the NTY field 405 derived from name 401. As described above the codes in the NTY field 405 indicate whether a name a tab name is 403 or an immediate name is 409, and if it is an immediate name 409, whether its ba- sis is FP, SDP or PBP.

3.5.2, i stress-generating components

Continuing with Figure 7, those to include addressing logic 533 components belonging to a next-frame counter (NFG) 7 53 'a current frame counter (CFC) 749

Status registers A (SA) 74-3 and B (SB) 735, a flush counter (FLC) 729, an I-Name multiplexer 718, microinstruction decoder A (HDA) 702 and B (MDB) 703, an FA multiplexer 781, a flush buffer (FB) 730, an ABC control or -trap 770 and associated logic.

As described above, is the ABC cache 50? in 16 ABC frames 6O3, each of which contains 16 ABCEs 503. An address for a given ABCiI 503 is specified both a frame and a register within a frame. In the preferred embodiment of ABC 502 are the addresses for the ABCEs 505 8-bit values; Of these 8 bits, the least significant four are the register address and the most significant four are the Frame address · The addresses are carried by address lines ADDR (O ... 7) 774- (Fig. 7A). The frame address FRA 765 is carried on lines 0 ... 3 of ADDR (0 ... 7), and the register address RA 767 is passed through the lines 4 · ... 7 of ADDR (O ... 7) transported.

FRA 765 and RA 767 are the ABC trap with data inputs DI 770 connected. The ABC trap 770 may have two 74-3194- Shift registers be implemented. The ABC trap 770 is enabled for writing whenever ABC 502 is about to resolve an immediate name 4-09, and hence becomes the current value of ADDR (0..7) latched into ABC trap 770 on each resolve operation. The ABC Trap 770

may be activated for writing at other times by a RABC line 717. The ABC trap 77O is always activated for reading and outputs ADDR (4 ... 7) to the descriptor processor 329. In the event of a missing signal in ABG 502, the ABC-Missing microcommand sequence _{uses the contents of ABC 7} case 770 to form the immediate name 409 that caused the missing signal or the error.

3.5.2.1 Sources of RA 767

There are two sources of RA 767: If a whole ABC frame 6O3 is in the process of being invalidated, the source of RA 767 is the FLC 729; for all other operations is the Source of RA 767 the I-Name-Multiplexer 7I8.

In the preferred embodiment 70I the addressing logic 533 the I-Name-Multiplexer 7I8 is a quadruple 2.1-line multiplexer, such as the 74-S258. The I-name multiplexer 7I8 is activated when its I input is inactive. As will be described in detail below, the Ε input is inactive, except when an ABC frame 603 is just being invalidated, or the entire ABC 501 and RMNC 517 is about to be invalidated. When the I name multiplexer 7Ί8 is activated, it selects input signals from the name bus 328 or the ADISP 639 according to the status of the S input. If the S input is active, the I-Name multiplexer selects 7 ^ 8 input signals from the ADISP 639; if it is inactive, the I-name multiplexer 7I8 selects input signals from the name bus 328. Whether the

- Copy

S input is active is determined by the output of OR gate 726. The OR gate 726 receives input signals from the RRMRßG line, 72 ² I- and an AND gate 725, and consequently the S input is active when the RRMREG line 724- is active, or when both inputs of the AND- Link 725 are active. The RRMREG line 724 is asserted in response to microinstructions; the input signals of the AND element 725 are bits 0 and 1 of the name bus 328, which transport the NTY field 405 of the names 401. If the NTY field 405 has the value 11, that is, if the name 401 is a table name 403, the I name multiplexer 718 selects its input signal from the ADISP 639> in the other case it selects the input signal from the name bus 328.

The inputs from Namebus 328 can either be bits 8-11 of DISP field 413 from an immediate 409 names received from a command, or they can be supplied by the microcode Be values. The ADISP field 639 is entered from one of the RMNCERs 627 (0 ... 3) in the RMNCE 519, which is activated by the value currently on Namebus 328 is specified. The values in ADISP field 639 consist of bits 8 through 11 of DISP field 413 of the immediate Names 409 contained in NDEs 309.

The second source of RA 727 is the FLC 729. The FLC can be a 4-bit counter of the type 743163. The FLC 729 increments the value it contains when its inputs P and T are active and it has a clock pulse on its

CLK input receives. The current value of the FLC 729 is output on lines 0 ... 3. If the L input of the PLG 729 is inactive, the FLC 729 is reset to the value at its data inputs. When used in the preferred addressing embodiment 701, the inputs of the FLC 729 are always set to zero. The FLC 729 outputs its current value to FB 730, which can be a tri-state line driver receiver of the type 74-S244-. FB 730 is activated when its Ε input is inactive. As will be explained in more detail in the description of the flush operation, if an ABC frame 6O3 is currently being invalidated, the I-name multiplexer 7 ^ 8 is deactivated or switched off and the FB 730 is activated. The J ¹ LC 7 ^ 9 counts, and the FB 73O drives the values generated by the FLC 729 to the EA 727. If the FLC 729 is not counting, it outputs the binary value 8, that is, the data output line 3 is active and the other data output lines are inactive. The operation of the FLC 729 is controlled by the SA register 7 ^ 3 and the SB register 735; both registers contain the value 0, except during a flush operation.

3.5.2.2 Sources for FRA 765

As described above, the ABCEs 503 are in only two ABC spaces 603 addressable at any given time. The two addressable ABC frames 603 are the current one

OHO I Ό

ABC frame 607 corresponding to the top frame 321 in the stack 317 and the next ABC frame 6Oy above the current ABG frame 6O7. In the preferred embodiment 701, the addresses of the current ABC frame 6O7 and the next ABG frame 609 are transferred to FRA 76 ^? provided by NFG 753, GPO 749 and the FA multiplexer 761. NFG 753 supplies the address of the next ABC frame 6U9, GFG 749 supplies the address of the current ABC frame 6O7, and the FA multiplexer 761 selects one of the addresses which are supplied by CFC 7 ^ -9 and ITFG 753 , for output to the FRA 765. ·

Both Nü'C 753 and CFC 74-9 can be cyclic 4-bit up-down counters of the type 74-S169. When their P and T inputs are inactive, ITFC 753 and CFC 74-9 count up or down in response to a pulse on their CLK input. The direction of counting is determined by the U / D (up / down, up-down) input; When it is active, the counter counts up. When the counter goes from 15 to 0 or from 0 to 15, the OY output generates a pulse by going inactive for a short period of time. When the L input is active, the counters are reset to the values on their input lines. In the present embodiment, the input lines of the CFC 7 ^ -9 are constantly switched to enter the value 0, and the input lines of the NFG 753 are constantly switched to enter the value 1. As will be described in more detail in the discussion of the flush operation, the L input only becomes active when all ABC frames 6O7 are invalidated.

ORIGINAL INSPECTED

Whenever processor 303 executes a call instruction, one of the microinstructions executed in response to the call command increments the GPC 74-9 and NPG 753 by 1, and every time processor 303 sends a Executes the return command, one of the microinstructions executed in response to the return command decrements the CPC 74-9 and NPC 753 at 1. So the CPC 74-9 will every time incremented when a new frame 319 is added to the stack .317 is added and r is decremented each time a frame 319 is removed from stack 317, and hence the current ABC frame 607 always corresponds to the top frame 321. Furthermore, because the NPC 753 always incremented or decremented at the same time as CPC 7 ^ 9 the next ABC frame 605 is always the ABC frame 603 above the current ABC frame 607 «

Which of the counters CPC 74-9 and NPC 753 has a frame address to the PRA 765, the PA multiplexer 761 determined, the PA multiplexer 761 is a quad ^: 1 line multiplexer, for example one of the type 74-S158. If the S input of the PA multiplexer 761 is active, selects the PA multiplexer 761 the NPC 753; otherwise he chooses the CPC 74-9. The S input is active when there is an input of the OR gate is 7 ^ 3 high. Since these input signals are complemented, the S input is always active when CPL 74-7 or LNEXT 715 is inactive. As more precisely when discussing the operation of the preferred

Embodiment 7OI is explained, CFL 7 ^ -7 is inactive, when the next ABG frame 605 is in the process of being invalidated will. UJEXT 715 is inactive when a microinstruction that loads an ABGE 503 in the next ABC frame 605, just now is performed.

■ 3.5.3 Data RAMs 773

The data RAMs 773 consist of twelve 256 χ 4- IiAfIs, all of them ADDR 777 (0 ... 7) as their address inputs and LABC 771 as its write enable input to have. All of the data RAMs 773 are always enabled for reads and they are for write operations activated when the CE input is inactive, i.e. when LABG 77I is inactive. The data RAMs 773 can of the type 934-22 DC from the manufacturer Fairchild Camera and Instrument Corporation.

Since all data BAMs 773 are connected to ADDR 777 (0 ... 7) a specified value on the address lines ADDR (0 ... 7) also addresses a logic register 4-8 bits formed from a single register in each of the RAMs in the data RAMs 773. This logical Register contains address field 6Ο9 of ABOE 503, and if ABCE 503 is valid, the logical register contains one specified by argument pointer 601 Address. Data outputs (DO) 79O Output data to the base multiplexer 511 and when LABC 77I is inactive Receive data inputs (DI) 776 data from the cache load bus 527 · As detailed below, LABC 771 by load operations on. ABC 502 specifying made inactive.

INSPECTED

3.5 «4- components for storing the validity information

As described above, each ABGE 503 contains a validity field 611, which indicates whether the content of the address field 609 is valid. In the preferred embodiment 501 the validity field 611 is stored in two validity RAMs, namely VRE 797 and VRO 795. VRE 797 and VRO 795 are each 128 χ 1 RAMs, for example of the type 94-325A. The DI input receives in both the VRE 797 and the VRO 795 a single bit of the data and the DO output enters " single data bit off. So that the data can be read from or written to the VRE.797 or VRO 795, the CF input must be inactive, and so that the data can be written to the VRE 797 or VRO 795, the WE input must be inactive.

Each register in VRE 797 and VRO 795 corresponds to a single logical register in data RAMs 773; the 128 registers in the VRE 797 correspond to the 128 even-numbered logical registers in the data RAMs 773, and the 128 registers in the VRO 795 correspond to the 128 odd-numbered registers in the data RAM 773 The value the only bit in each register of the VRE 797 and VRO 795 indicates whether the logical register in the data RAMs 773 corresponding to that register contains a valid address. In the preferred embodiment, 772 is the corresponding or corresponding register valid if the bit has the value 0; otherwise it is invalid.

ο ο ο 4 υ /

The correspondence between the logical registers in data RAMs 773 and the registers in VRE 797 and VRQ 795 is obtained by ADDR (0 ... 6) 793, consisting of lines 0 ... 6 from ADDR (0 ... 7) 774-1 connected to YRE 797 and VRO 795, and ADDR (7) 777, consisting of line 7 from ADDR (0 ... 7) to the Logic is connected which VRO 795 selects when an odd-numbered logical register is in the Data RAM 773 is addressed and the VRE 795 selects when addressing an even-numbered logical register. The way in the AER 797 and VRO 795 depends on whether ABC is currently responding to name 401 or is currently loaded is being or is being flushed and will be described in more detail in the discussion of these operations.

3.6 Operation of the Preferred Embodiment of the ABC 502

The preferred embodiment of the ABC 502 performs the perform the following operation in response to input signals the name bus 328, ADISP 639 and micro-commands:

If the preferred embodiment of the ABC uses either name bus 328 or the ADISP 639 resolves received immediate names, generates the preferred embodiment one Data output signal for DO 790 and a hit / miss (miss) output signal at ABC H / M 7 ^ 05;

ORIGINAL INSF> £ CT £ D

4 ·

In response to a read HMHC register microcommand the preferred embodiment of the ABC 502 on ADISP 639 speaks of a specified RMtTCER 627, as just described, for the release operation.

Incremented in response to an invoke microcommand the preferred embodiment den. OFG 749 and NFC 753 and makes the next ABC frame 605 invalid;

Decremented in response to a return microcommand the preferred embodiment the CFC 7 ^ -9 and NFC 753 and invalidates the new next ABC frame 606;

In response to an invalidate microcommand from ABCE, the preferred embodiment makes a specified ABCE 503 on the fly Frame 6Ο7 invalid;

In response to a "loading" microcommand the preferred embodiment loads a specified one ABCE 503 in. running frame 6O7 and makes «Those ABCE 503 valid;

In response to a "load next" microcommand The preferred embodiment loads a specified ABCE 503 in the next frame 605 and does those ABCE 503 valid;

- In response to a flush micro-command, the preferred embodiment makes the whole ABC 502 invalid.

The operations are loaded in the above order. wrote.

3.6.1 Name resolution

If the preferred embodiment of the ABC 502 is included, Resolving an immediate name 4-09 does not specify • none of lines 705 to 711 and 724 an operation, and everyone is active. As a result, the following conditions apply:

The SFL line 723 is inactive;

FLC 729 outputs the value 1 on its third output line; and

The SA register 74-3 and the oB register 735 contain the value 0.

Because these conditions apply, i.e. the GFL line 74-7 active. In response to this, the I name multiplexer activated and the FB driver 730 is switched off so that

ORIGINAL INSPECTED

RA is supplied by the 767 I-plex name -Multi 718th Furthermore, the LNEXT line 715 is also active, therefore the output of the OR gate 763 is inactive, and the FA multiplexer 761 selects the CFC 759 as the source of the FRA 765.

Which input through the I-Name multiplexer 718 than the Source is selected by RA 767 depends on the value of ΝΤΓ-field 4-05 of the one currently on Namebus 328 Name 401. This field is fed to the AND gate 725 as an input signal. If the name 401 is a table name 403, that is, if it has an NTT field 405 with has the value 11, the output of AND gate 725 is active, the output of OR gate 726 is active, and the I-Name multiplexer 718 selects ADISP 639; otherwise it selects name bus 328. The data RAMs 773 are for reading activated, and they output the content of the address field 609 of the ABCE 503 specified by ADDR 774 at DO 790.

ADDR (0..6) 793 still addresses a register in VRE 797 and VRO 795. 4DDR (7) 777 is used with the DO 796 'with AND element 7101 AND-linked and is activated by the inverter 7IOO is inverted and with the DO 798 of the VRE 795 with AND element 799 AND-linked. The output signals the AND gates 799 and 7IOI are then through the OR gate 7103 for generating the ABC H / M 7105 OR linked. If ADDR (0..7) 774 an even-numbered logical register in the data RAMs 773 addressed, ADDR (7) 777 is inactive. Hence this is

, 02 ^ 3 *.

The output signal of the AND gate 7101 is inactive and the output signal of the inverter 7100 is active. Palis DO 798 is about to output a 1, which indicates that the ABCE 503 specified by ADDR (0..7) 77 * \ is invalid, the outputs of the UlTD element 799 and the OR element 7IO3 "are both active , whereby an ABC miss signal is generated on line 7105,! '"all ADDR (0 ... 7) 774- addresses an odd-numbered logical register in the data RAMs 773, ADDR. (7) 777 is active, which is an inactive output signal of the inverter 7IOO and active output signals of the AND gate 7IOI and the; OR gate 7103 generated if DO 796 is active. An ABC error signal is only generated on line 7105 if ABCE 503, which is addressed by ADDR (0..7) 77 ^ · is invalid.

3.6.2 The Read RMNC Register Operation

This operation occurs when the RRMREG line 72 ^ is active. In this case the I-Name Multiplexer / 7I8 selects ADISP 639 as the source of RA 727 and the preferred embodiment addresses 70I, as just described for the name resolution operation.

3.6.3 The call operation

During the call operation, NFC 753 and CFC 74-9 are incremented and the next ABC frame 605 is invalidated. When a microinstruction specifies a call operation, if CALL 707 is inactive during a fact period,

ORiCiWAL! MSPECTED

and the remainder of lines 705 through 717 remain active. While CALL 'is inactive, the output signal of NOR gate 721, SFL 723 is inactive. The inactive signal Sl ¹ L inactivates the P inputs of the NFC 753 and CFC 749 via the NOR element 755. The U / D inputs of the NFC 753 and CFC 749 are connected to “RET'70y, which is active NFC 753 and CFC 74-9 incremented by 1.

The call microcommand also begins invalidating of the new next ABC frame 6O5. During the invalid In doing so, FRA 765 is delivered by NFC 753, and RA is supplied by FLC 729. Bit 4 of RA 767 becomes supplied by bit O from FLC 729, bit 5 off bit 1 and so on. Thus the most significant bit provided by FLC 729 is the least significant bit. von RA 767 · As will be explained in more detail later, counts FLC 729 only from 0 to 7; Bit 3 therefore always has the value 0 when FLC 729 is counting, and that at RA The values supplied are addresses for even-numbered registers in the data RAMs 773.

As described above, deactivating CALL true: a clock pulse also deactivates "SFL'723 during the same period. SFL 723 is with the L input of the FLC 729 and is complemented and an input of the OR gate 741st. Consequently

then, when SFL 723 becomes inactive, FLC 729 is reset to 0 and the SA register 743 becomes set to 1. When the FLC 729 is reset to O, the output line of the FLC 729 becomes inactive. That output line is inverted by inverter 736 and used as input for NAND gates 745 and 737.

It is started with the NAND gate 745. The other input signal of NAND gate 745 is the output of SA 74-3, which is now 1. Hence the exit CFL * 747 of NAND gate 745 inactive. CFL ~ 747 is with the Ε input of the FB 730, the OR gate 763 and the NOR gate 785 are connected. It is made by the inverter 728 complemented and the Ε input of the I-Nan.e multiplexer 7I8 and the T input of the FLC 729. Hence are FB 730 and FLC 729 activated and the I-Nan.e multiplexer is switched off so that FLC 729 is the source of RA 767 is. Finally, FA multiplexer 761 selects NFC 753 as the source from FRA 763. Furthermore, the output signal of the NOR gate 785 is inactive and both VRO 795 as VRE 797 are also activated for writing.

It continues with the NANd gate 737. At the beginning an invalidation operation, SB 735 contains the value 0; when FLC 729 mxt 0 is loaded, line 3 becomes inactive, its complement becomes active, the NAND gate 737 has an active and an inactive input signal, and the. SF line 739 is active. The FL line 705 is also active and accordingly the output signal of the OR gate 733 is inactive and the SB register 735 becomes 0

INSPECTED

~ GOPY

held. As long as the FB register 735 has the value 0, the output signal of the NAND element 731 is active and the P input of the FLC 729 is active. Because the T input was also activated when the PLC 729 was set to 0, I ¹ LC 729 increments itself at every clock period until. it reaches the value 8 (binary 1000). At this point, line 3 of the FLC 729 changes its value from 0 to 1, the CFL line 739 becomes active, the SA register 735 is set to 0, and the T input of the FLC 729 becomes inactive, causing it to count stops. Furthermore, the FB driver 730 is switched off and the I-Name multiplexer is activated, so that FLC 729 is no longer the source of HA 767.

For each of the FLC 729 during its counting from 0 to 7 ADDR (0 ... 6) 793 simultaneously addresses a register in both the FRE 797 and FRO 795. As already has been written, both FRE 797 and FRO 795 are activated for writing; continue to be INABC line 711 and LABC line 771 are both active. . As a result, the output of the OR gate 783 is inactive, the outputs of AND gates 787 and 789 are both inactive, and the OS inputs of both VRE 797 and VRO 795 are inactive. LABC line 771 is on connected to the DI inputs of both the VRE 797 and the VRO 795, and therefore a 1 written in the.-iegister in VRE 797 and VRO 795, the addressed by AJDR (0..6) 793. Thus become during the eight clock periods required for the FLC 729 to count from 0 to 7, all 16 registers of the

· »♦

VRE 797 and VRO 795 that correspond to the one specified by NFC 753 new next ABC frame 605 belong, invalidated.

3.6.4 · The return operation

During the return operation, NPC 753 and CFC 749 decrements instead of increment, and the new next ABC frame 605 specified by NFC 753 becomes invalidated. The only difference between the return operation and the call operation is that that RET line 709 is inactive during a clock period • instead of the CALL line 707 · As explained above, is the RET line 709 with the U / D inputs of NFC 753 and CFC 749 connected; when it is inactive, NFC counts and CFC 7 ^ 9 downwards. Here it is for a clock period inactive, and consequently NFC 753 and CFC 749 are decremented by 1.

3.6.5 The ABCE invalidation operation

The ABCE invalidation operation does a specified one ABCE 503 invalid in current frame 6O7. the ABCE 6O3 specifying RA 727 becomes from the I-Name-Multipi exer 7 ^ 8 received.

ORIGINAL INSPECTED

/ 7 V if.

During the operation INABG 7II is inactive and all other lines 705 to 717 are active. Because SPL 723 is active and FLC 729 is currently outputting the value 1 on output line 3, SA 743 is set to 1 and CFL is active, as described earlier. As a result, the FB driver 730 is switched off and the I-Name multiplexer 718 is activated to deliver RA 727. As described earlier, the values on the RRTiREG line 724 or the bits 0 ... 1 of the name bus 328 determine whether the I name multiplexer 728 delivers RA 727 from the name bus 328 or from ADISP 739. Furthermore, both CFL 747 and LNEX (P 715 are active, causing FA multiplexer 781 to select CFC 749 as the source of FRA 76 ^r 5. ADDR (0 ... 6) 7 ^ 3 of ADDR (0. ..7) thus deliver addresses to one register each in VRE 797 and 7RO 795. As will be explained here, ADDR (7) 777 selects which of the elements VRE 797 and VRO will be written into.

When INABC 7II is inactive, the output of the OR gate is 783 active. The output of the OR gate serves as an input to the NOR gate 785, cLes AND gate 789 and AND gate 787. An active input signal from the 'OR gate 783 for this mentioned Linking links has the following consequences:

The output of NOR gate 785 is with the WE inputs of both the VEE 797 and the YRO 795 connected; when the output of the "OR" gate 783 is active, these inputs are inactive and VRE 797 and VRO 795 are for writing activated.

If the output of the OR gate 783 is active, "the value of ADDR (7) 780, the value of which is the complement of the value of ADDR (7) 777, determines whether the outputs of AND gates 787 and 789 are inactive.

The output of the AND gate 787 is connected to the CS input of the VRE 797, and the output of the AND gate is connected to the CS input of the VRO 795. Therefore, when ADDR (7) is active, the output of AND gate 789 is inactive and VRO 795 is selected; when ADDR (7) is inactive, the output of AND gate 787 is inactive and VRE 797 is selected. Veil LGUR "7I3 and LNEXT'715 are active, LABG 771 is active and the DI inputs of VRE 797 and VRO 795 are active. Therefore, if ADDR (7) 777 selects VRO 795, the register in VRO 795, that is specified by ADDR (0 ... 6) 793 is set to 1; if ADDR (7) 777 selects VRE, the corresponding register in VRE 797 is set to 1. As a result, this is set by ADDR (O ... 7 ) specified ABCE 503 invalid.

3.6.6 The "loading-in-progress" operation

The load-in-progress operation loads an address derived from an argument pointer 601 into an ABCE 503 in the current ABC frame 603. The address is entered via cache load bus 527 and the source from RA 767 , is the I-Name multiplexer 718. The operation supplies ADDR (0 ... 7) 774 to the data RAMs 773 and ADDR (0 ... 6) 793 to VRO 795 and TRE 797 and select exactly one of the two Elements VRO 795 and VRE 797 corresponding to the value of ADDR (7) 777 in the same manner as described for the ABCE invalidation operation. However is inactive during the loading-in-progress operation LCUR 7 ^ 3. Consequently output LABC 771 of NOR gate 769 is inactive. LÄBCT711 is connected to the I inputs of the VRO 795 and VRE 797 and connected to the WE input of the data RAMs 773 »and its complement serves as an input to the NOR gate 785. The output of the NOR gate 785 is connected to the WE inputs of the VRO 795 and VRE 797 connected. Accordingly, the data RAMs 773, VRO 795 and VRE 797 are all activated for writing. The value at the DI inputs of VRO 795 and VRE 797 is 0, and at the end of the operation will the address on the cache load bus 527 is written into the address field 609 in the ABCE 503, which is processed by CFC 7 ^ -9 and by the value supplied by the I name multiplexer 7I8 is specified and the validity field 611 belonging to ABCE 503 is set to 0, indicating that ABCE 503 is valid.

ό ό ό 4 O /

3.6.7 The "load next" operation

Next, the charging operation is identical to the charge-run end-operation, except that the ABGE 503 that is loaded, is in the next ABC frame 607th LHEXT is inactive during the operation. As a result, the output of OR gate 763 is active and FA multiplexer 761 selects Ni ¹ G 753 as the source of FRA 765.

3.6.8 The flush operation

The flush operation invalidates all ABGEs 503 in ABC 502. Addresses are generated by FLC 729 and NFG 753. FLG 729 is held at 0 while NFG 753 counts from 1 through I5 to 0; then FLC 729 is incremented, and NFG 753 counts again from 1 through 15 to 0. As in the discussion of the invalidate operation ABC, both VRE 797 and VRO 795 have inactive Cü and WE inputs and active Di inputs; thus every time an address is generated by CFG 74-9 and FLC 729, that by ADDR (0 ... 6). specified register in both VRE 797 and VRO invalidated; when FLC 729 reaches the value 8, are all registers in VRE 797 and VRO 795 have been invalidated and the flush operation is terminated.

The flush operation begins when the FL line 705 is inactivated during a clock period. As a result, the UFL line 723 is also inactive. The inactive

SFL line 723 resets FLC 729 to O, resets the SA register 735 back to 1, and inactivates the P inputs of the GPC 74-9 and NFG 753 via the NOR gate 755. The inactive FL line 705 sets the SB register 735 to 1 and sets CFG 74-9 back to 0 and NFC 753 As long as the SB register 735 has the value 1 and the output line 3 of the FLC 729 has the value 0, sF is 739 inactive. SF serves as an input to NOR gate 755j, and thus "both counters are" on every clock period increments until one of the above conditions changes.

Because line 3 of the FLC 729 has the value 0 and SA 74-3 the value 1, CFÜT 74-7 is inactive just like "SF ~ 739. Das inactive CFL 74-9 supplies an active input signal via OR gate 763 to FA multiplexer 761, thereby causing that the FA multiplexer 761 uses the NFC 754 as the Source of FRA 765 selects. The inactive CFL 74-7 switches also turn off the I-Name multiplexer 718 and activate F3 730, and thereby selects the FLC 729 as the source of RA. Finally, the inactive CFL activates the T input of the FLC 729.

While the CFC 74-9 is counting from 0 to 15 and the NFC 753 from 1 to 15 to 0 are the OV output of the CFC 74-9 and the associated CO line 751 active. The CO line 75 '' serves as an input for the

NAND gate 731, and SB 735 supplies the other input. Because SB has the value 1, the output of the NAND gate is inactive as long as the GO line 751 is active and the FLC 729 does not count. If the value in the GPC 749 changes from 15 to 0, however, the OV output of the Ci ¹ C 759 becomes inactive and generates a short pulse. Because SB 735 still has the value 1, the output of NAND gate 731 becomes active and FLC 729 is incremented by 1. The process just described continues until the FLC 729 reaches a value of 8. At this point line 3 of the FLC 729 changes its value from 0 to 1 and the CLD line 747 and SF line 739 both become active. The active CFL line 745 sets the SA register 743 to 0, switches off FB 730 and activates the I-Name multiplexer 718. The active SF line 739 sets the SB register 735 on and causes the P inputs of the NFC 753 and CFC 749 and the T input of the FLC 729 to become active, whereby NFC 753, CFC 749 and FLC 729 are stopped. During the 'standstill, NFC 753 contains the value 1, CFC 749 the' value 0 and FLC 729 the value 8.

3.7 The preferred version of the ABC 502 in the operations of processor 301

The operations of the preferred embodiment of the ABC 502 just described are used in certain Processor 301 operations combined. When processor 301 executes a call instruction, loads that by controller 327 in response to the call command

executed microcode first the argument pointers 601 for arguments used in the call command in the new top frame 321, which is created by the call command was created. Every time it loads an argument pointer 601 into the new top frame 321, is used it does the load next operation to one of the argument pointer to load the corresponding address into the memory location in the next ABC file 605 that corresponds to the memory location of the Argument 601 in the new top frame 321 corresponds. Then the microcode that executes the call instruction performs the call operation. As described, incremented the call operation the CFC 749 and NFC 753 and thereby transports the next ABC frame 605 into the current ABC frame 607, and then makes the new next one ABC frame 605 invalid.

When processor 301 executes a return command, it executes through controller 327 in response to the return command executed microcode from the return operation, which decrements the CFC 7 ^ 9 and NFC 753, whereby the current ABC frame 607 is transported into the new next ABC frame 605th, and then makes the new next one ABC frame 605 invalid.

If processor 301 resolves a name 401 and an ABC miss occurs, control wins 317 microcode executed in response to the ABC miss signal the current value of RA 767 from the ABC trap back, constructs the immediate name 409 from this value, from which RA 767 was obtained, calls the

the immediate name 409 corresponding Argumentζeiger 601 from the top frame 321 from, and uses the charge-Ongoing operation to the the Argumentζeiger 503 for frame ABC 607 in the current ^u invite 601 corresponding address in the address field 609 of the ABCE defined by the Immediate name 409 constructed from ABC trap 770 is specified.

3x8x Description of a Preferred Embodiment of the RMNC 517 - Fig. 8

The discussion now turns to a preferred embodiment of the RMNC 5 ^ 7. Fig. 8 shows a preferred one Embodiment 801 of the RMNC 517 · During the Reference is also made to Figure 6a, which shows the logical structure of an RMNCE 519 for discussion. The hatched ones Portions of Figure 8 show fields in a single RMNCE 519 and show how they relate to the preferred one Embodiment 801 of the RMNC.

The preferred embodiment 801 of the RHNC is a direct-mapping cache with 256 entries, which is addressed by the table names 403 received from the name bus 328. Any valid entry in the preferred embodiment 801 of the RMNC corresponds to a table name 403 with an NTE 310 in the Name table 309 »used by procedure 311. which is being executed by the computer system 301 at this point in time. However, a table of names

14 309 have up to 2 NTEs 310 in the computer system 301, while the preferred embodiment 801 of the RNNC

ORIGINAL INSPECTED

only has 2 ⁸ RMNCEs 519. The 2 ⁸ BMNCEs 519 are addressed by the eight least significant bits of NT-IND field 407 in the menu appearing on the 328 Namenbus table name 403rd These bits form bits 8-15 of name bus 328 and are marked as IND (8..15) 817 in FIG.

• Of course, table _{names 403}} which correspond to up to 2 different NTEs 310 can have identical bits 8 to. Whether an EDiDTCE * 519 actually corresponds to a given table name 403 is determined by an entry tag associated with each valid RMNCE 519 in the preferred embodiment 801 of the RMNC. The entry identifier for a valid RMNCE 519 consists of the six most significant bits of the NT-IND field 407 from the table name 403 corresponding to the RMNCE 519. If a table name 403 of the preferred embodiment 801 of the RMNC is offered, the six most significant bits of the NT- IND field on bits 2 to 7 of the name bus 328. These bits are marked as TAG (2..7) 819 in FIG. The value transported by TAG 819 is compared with the entry identifier assigned to the RMNC 519, which is addressed by IND 8I7. If TAG 819 and the entry identifier are identical and RMNCE is valid, then RMNCE 519 corresponds to table name 403. If TAG 813 and the entry identifier are not identical or if RMNCE 519 is invalid, an RMNC miss signal results.

COPY _

3.8.1 Components of Preferred Embodiment 801 of the BMNC

First of all, we will consider the buses, dio the keys and data on the preferred embodiment 801 of the MC provide and receive output signals from the preferred embodiment 801 of the RMNC. The preferred embodiment 801 of the BMNC receives keys from name bus 328. Name bus 328 is in FIG. 8 in components ^ granted, their values for the preferred embodiment 801 of the EMNC have different functions:

- The bits 0..1 of the name bus 328, which are marked here as NT (0..1) 821, transport the NTf field 405

■ the name 401.

- Bits 2..7 of name bus 328, which are here as TAG (2..7) 819 are marked, transport the most significant bits of the NT-IND field 407 of the table names 403

- Bits 8..15 of name bus 328, which are shown here as IND (8..1Ü ***** 817 are marked, carry the eight least significant Bits of NT-IND field 407.

The preferred embodiment 807 of the RMNC receives Data from cache load bus 527 »VL bus 810, and the ID load bus 808. The function of the cache load bus 527 has already been described; the VL bus 810 provides • validity information for the V field 622 cer RMNCEs 519,

INSPECTED

and ID load bus 808 provides memory location codes for ID field 623. The preferred embodiment 801 of the RMNC outputs data to the address offset multiplexer 525, the descriptor bus 333, the controller 327, to the CTL 515 and at ABC 502, as described in the discussion of RMNCEs 519.

The preferred embodiment 801 of the EMNC consists of the following devices or facilities:

A data memory 813 containing 1024 data storage registers 815. Each EMNCE 519 contains four data storage registers 815 that are used to store EMNCER 627 (0) through (3).

A tag storage (TAG STORE) 806, the 256 tag storage registers 807 contains. Each tag storage register 807 is associated with an RMNCE 519. The tag storage register 807 for a given RMNCE 519 contains the entry tag assigned to the. RMNCE 519 is assigned, and parts of control field 620.

A validity memory 804, the 256 V register 805 contains. Each V register 805 is assigned to an RMNCE 519 and contains a V field 622 for that RMNCE 519

An ABC-FLAG memory 802 containing 256 ABC-FLAG registers 8O3. Each ABC-FLAG register 803 is assigned to an RMNCE and contains an ABCF field 621 for that RMNCE 519 ο

A comparator 811. The comparator 811 compares the entry identifier for the EMCE 519 addressed by IND 817 with the value of TAG 819, and if they match, it checks that that EMCTCE 519 is valid. If the entry identifier and TAG 819 match and that EKNGE 519 is valid, the comparator 811 provides an EMNC hit signal to CTL 515; otherwise it delivers an EMNC-i ¹ ehl (mis) signal.

Each of these components are described in greater detail below, and then operation of the preferred embodiment is described 801 of the EHNC.

3.8.1.1 Data memory 813

In the preferred embodiment 801 of the EMNC-mag 813 data memories consist of 15 static 1024 χ 4-M0ti-EAMs of type 2149 with an access time for read data from 45 ns. The eight most significant bits of the addresses for the IOMs are provided by IND 817 from name bus 328. The remaining two bits are supplied by EM register address 812. The BM Begister address is 812 a default setting of 0. Consequently, the bits supplied by IND 817 specify BMNCER (0) 627 for a given EMNCE 519. The one given by the control 327 executed microcode can the EM register Set address 812 to other values and can therefore each EMNCEE 627 in an RMNüii 519 specified by IND 817 address.

The data inputs to data memory 813 are provided by cache load bus 527; the content of a A given RMITCER 627 may be output completely to the descriptor bus 333, or fields of a given RMNCER 627 can be output in the following way: The address offset field 629 to the address offset multiplexer 525; the base field 64-1 to the CTL 515; and the ADISP field 639 to ABC 502.

3.8.1.2 Number plate memory 806

The identifier memory 806 may consist of 13 1024 χ 1 RAMs of the type 2125 H3 with an access time for a read operation of 30 ns. The eight most significant bits of the addresses for the RAMs in tag memory 806 are supplied by the IND 817; the two least significant bits are held at 0, and hence are only the tag storage registers 807, the correspond to the RMNCERs 617 (0), addressable. Each addressable tag storage register 807 contains an ID field 623 and a BC field 625, a copy of the Base field 641 of RMNCE 619; they also contain an E-TAG field 809, the value of which is the entry identifier for those currently stored at that address in the RMNC 517 RfJNCE is 519. The E-TAG field 806 becomes the TAG 819 loaded, the BC field 625 is loaded from the cache load bus 527 at the same time as the RMNCER (0) 627 in the data memory 813 is loaded, and the ID field 623 is loaded via the ID load bus 808.

With the preferred. Embodiment 801 of the RMNG includes the ID field 623 is a four-bit value from which the controller 327 is the location of the first microinstruction in the Derives micro-instruction sequence that EMITCE 519 processes, to which the ID field 623 belongs. The content of the ID field 623 is provided by a PEOM in the preferred embodiment 801 of the EMNC. In other embodiments The microcode may be set by the ID field 623, depending on the requirements, and the ID field 623 may

read to determine how RMNCE 519 »to aem the ID field 613 heard, must be processed. The data output signal The controller 327 is fed from the ID field 623. The data output from BC field 625 goes to the CTL 515 »the data output signal from the E-TAG field 8O9 is fed to the comparator 8T1.

3.8.I.3 Validity memory 804

The validity memory 804- consists of between 1024 χ 1 RAMs of type 2125 H3 with one access time. a read operation from 30 ns. The validity memory 804- is implemented in the same manner as in the discussion the preferred embodiment 772 of the ABO register has been described. One of the two RAMs holds V-fields 622 for even EMNCEs 519, and the other contains V-fields 622 for odd EMNCEs 519. The seven most significant bits of IND 8I7 are used to ' to form the most significant bits of the addresses for both RAMs, and the remaining bits of the addresses are set to 0. As a result, only every eighth register in any RAM is addressable.

10.

Ass

When RMUC 517 outputs data, one chooses the least significant Bit of IND 817 responsive logic either the output signal from the RAM, the V-fields for even numbers KMNCEs 519 contains, or the output signal from the RAM, which contains V-fields for odd EMNCEs 519, in in the same manner as described for the ABC valid RAMs VRE 797 and 7RO 795. In a similar way selects when data is written to the V-Field 622, logic responsive to the least significant bit selects one RAM or the other depending on the value of the least significant bit. If all RMNCEs 519 are invalid need to be done, both RAMs are selected and the registers in both RAMs are invalidated in parallel. The addresses "for the invalidation operation are generated by addressing logic 733, as described in the discussion of ABC 502.

The validity memory 804 is loaded by means of the VL line 810, which supplies a value 0 if RMNCER 627 (0) of the RMNCE 519 to which the validity memory register 805 belongs is loaded and a value of 1 if that RMNCE 519 is invalidated . The output signal from validity memory 804 goes to comparator 811.

3.8.1.4 The ABC FLAG memory 802

The ABC FLAG memory 802 in the preferred embodiment 801 of the RMNC consists of a single 1024 χ 1 RAM of type 2125 H1 with an access time during the read operation from 20 ns. The ABC FLAG memory 802 is used in

addressed in the same way as the tag store 802 (TAG STORE). Each addressable register in the ABC-FLAG memory 802 contains an ABCP field 621 for the RMETCE 519 specified by IND 817 into the ABC-FLAG memory 802 from the cache - uadebus and they are output to the CTL 515.

3.8.1.5 Comparator 811

The comparator 811 consists of a logic which determines the following:

- Whether the value in the E-TAG field 809 that the DiD 817 is assigned to specified RMCE 517, is the same as the vert on TAG 819.

- Whether the validity field 622 of the RMNCE 51? indicates that RMNCE 517 is valid.

If the value on TAG 819 is the same as that stored in E-TAG 809, and if the validity field 622 indicates a valid RMNCE, the comparator 811 provides an RMNC hit signal, which indicates that the table name 403 has an entry in RMNC 517 for CTL 515. Otherwise, the comparator 811 supplies an RMNC error (mis) signal

In the preferred embodiment 301 dea RMIiG, the comparator 811 is implemented by a first Sata of U ₁ ¹ ID elements which compare the bits of the first au comparing element and the negated bits of the second

Elements received and output to a first NOR gate, and by a second set of AND gates that receive the negated Bit3 de3 element and the bits of the second element and output to a second NOR gate, and by an AND- ¹ JIied, whose input signal are the output signals of the two NOR gates.

3.9 Operation of the Preferred Embodiment 801 of the EMWG

The discussion of the operation of the preferred embodiment 801 of the BMNC turns to theirs first How it works during the name resolution operation and then with their operation under microcode control.

3 x 9 x 1 x nanometer resolution in the preferred embodiment form 801 of the BMNC

The discussion of name resolution in the case of the preferred Embodiment 801 of the EMNC deals first with those cases where the preferred embodiment 801 of the RMNC has a name 401 corresponding to it 519 does not contain, and then with those in which they such an RMNCi) 519 contains.

The first table in which the preferred embodiment 801 of the RMNC does not contain a 519 corresponding to a name 401 occurs when the name 401 is an immediate name 409. In this case, the ^- field 405 has a value that differs from binary 11.

333457

CTL 515 responds to values deviating from 11 by that it activates a source other than EMITC 5I7 for the address offset multiplexer 525, and as above explains, ABC 502 responds to such values by selecting name bus 328 as the source for EA 727. Thus, if this is indicated by values of the NiDY PeIds 405, which differ from binary 11, the address output by the improved address caches 501 is required formed without involving the HMNC 517.

In the second and third pail the NTI field 405 has one Value of binary 11 and EMNC 517 like one of the table. name 403 corresponding to EMNCE 519 included. The missing such an EMNCE 519 may be ascertained in two ways : The EMNCE 519 can have a V-PeId 622, which is set in such a way that it is an invalid EMNCE 519 indicates, or an E-TAG PeId 802 may be assigned to the EMNC 519 that contains a value that differs from that on TAG 819.

In both cases, the identifier memory 806 (TAG STOEE) and the validity memory 622 give a V-PeId 622 and an E-TAG 809 for EMNCE 519 to comparator 811. The comparator 811 detects the fact that EMNCE 519 is invalid and delivers a Pehl (miss) signal CTL 515. In response to this fault signal, CTL 515 generates a signal for controller 327 that the Controller 327 causes an EMNC cache miss microinstruction sequence to be executed to start. As with the description of the validkext memory 804 and the identifier memory 806 was mentioned, they have this

ORlGSiMAL IiSSSPECTgO

Components forming HAMs have a higher speed of operation than those constituting the data memory 8I3. As a result, the cache miss microcode sequence begins execution at the same time the invalid data is supplied to address adder 513, and the invalid data is ignored.

The cache miss microinstruction sequence wins the table name 4-03, which caused the false signal, from the Name trap 4-31 again and then use the current one Value in the name table register 332 and NT-IND-Field 407 for the localization of the NTE 310 according to the Table names 403. The microinstruction sequence then caches Information derived from the NTE 310 in the RMNG 519 specified by IND 819 from the table name 403 that caused the miss signal. The way EMNCE 519 is loaded is in under micro-instruction control and corresponds to the way of how NTE 310 containing the information is loaded. When the loading is complete, processed the microcode sequence contains the cached information, as it does in the case of a hit signal on the BMNG 517 would, and delivers the desired descriptor to the descriptor bus 333.

If RMNC 517 an EMNGE 519 for a table name 403, the operation of the HMNC 517 depends on that Contents of the ID field 623 and the BC field 625 in the RMITCE 519 from. Generally speaking, the ID field specifies 623 whether microcode intervention is required

333457!

j c 3.

to process the content of EMTCE 519, and if this is the case, which microcode sequence is to be executed by processor 303. The BC field 625 specifies the way in which CTL 5 ^ 5 input signals for the base multiplexer 511 and the address offset multiplexer 525 must be selected. In the preferred embodiment 801, the BC field 625 has the following codes:

Code meaning

000 direct address; Base = FP 010 direct address; Basis = SDP 100 direct address; Base = PBP

001 indirect address; Base in ABC 111 complete address

It is started with the cases in which a riikrocodeintervention is unnecessary. If RIINCE 519 has a contains the complete address, the BC field 625 has the code 111 and the address is in the address offset field 629 of the RMITCER 627 (0). The ID field 623 does not specify any microcode intervention and CTL 515 responds to BC field 625 by selecting from RMNC 517 as the input to the address offset multiplexer 525 and in that it is the address adder 513 causes the value from the address offset multiplexer 525 to pass unchanged to descriptor bus 333. As mentioned above, it's through ROTC 517 from IND 817 generated address that of KMNCER 627 (0), and the content of the address offset field 629 from RMNCER 627 (0) is thus via the address adder 513 is output to the descriptor bus 333.

If EMNGE 519 has an address offset from IFP, SDP or contains PBP, the BC field 625 has the codes 000, 010 or 100, the IO field 623 does not specify any micro. Code intervention, and the address offset field 629 of the HMNCER 627 (0) contains the address offset. CTL 515 speaks to the codes in the BC field 625 by selecting the register from ABRC 504, since the BC field 625 contains specified base address as the source for base multiplexer 511 and by selecting RMC 517 as the input to the address offset multiplexer 525 at. As a result, the address adder adds 513 the. Base address in the specified register of the ABRC 504 to the address offset in RMNCER 627 (0) to Generation of the desired address.

If RMNCE 519 has an address offset from a Contains argument pointer 601, the ABCF field becomes 621 set, the BC field 625 has the code 001, the address offset field 629 of the RMNCER 627 (0) contains the address offset, and the ADISP field 639 contains that RMNCER the deviation of the argument pointer 601 from FP. As mentioned above, the ABC FLAG memory is 802 a 20 ns RAM. Consequently, the value of the ABCF field 621 reaches CTL 515 'before the values of the BC field 625, des Address offset field 629 or ADISP field 639 In the preferred embodiment 801, CTL speaks 515 on the ABCF field 621 by generating a signal, this causes the controller 327 to extend the current machine cycle of the processor 301 until the value of the ADISP field 639 can be used as an input to ABC 502.

m λ * *

CTL 515 is responsive to the code in the BC-field 625 of the fact that the base multiplexer is caused to 511 _v to select its input from ABC 502, and that the address offset multiplexer is caused to 525 to select the address offset field 629th As explained in the discussion of ABC 502, the code on NTY 821 causes ABC 502 to select ADISP field 639 provided by BMC 3V as its input. If no microcode intervention has taken place, the ADISP field 639 comes from BMCEE 627 (0). If a valid ABCE 502 exists corresponding to the value of the ADISP field 639, ABC 502 outputs its content to the base multiplexer 511.The address adder 513 then combines the base address from ABC 502 with the value of the address offset field 629 in EMCEB 627 (0) for generation the address represented by the table name 4-03. If ABC 502 does not contain the address derived from the argument pointer specified by ADISP field 639, the result is an ABC cache miss and is handled as described above. After the correct ABCE 503 has been loaded, the described operation is repeated.

3.9.2 'Operations performed under microcode control the preferred embodiment 801 of the BMNC

The preferred embodiment performs under microcode control 801 of the BMC performs the following operations:

- Load RMNCER: EMiTCER 627 O, 1, 2, or 3 of the BMFCE 519 specified by IND 815 is taken from the cache load bus 527 loaded. The microcommand specifies the desired BMCTCEH 627.

- Make RMIiGE invalid: RMNCE 519, specified by IND 817 'is invalidated by setting V field 622 to indicate that RMNCE 5I9 is invalid is.

- Flush: RMNC 517 and ABC 502 are made invalid. The addresses for the invalidation are generated, as described in the discussion of ABC 502.

- Resolve RMNCER: CTL 515 speaks to RMNCER 627 0, 1, or 3 of the RMNCE 519 specified by IND 8I7 in in the same way as it responds to RMNCER 627 0 in the resolve operation.

- Read RMNCER: The content of RMNCER 627 0, 1, 2, or the RFINCE 519 specified by IND 817 is sent directly given to descriptor bus 333. The microcommand specifies the desired RMNCER 627.

The operations are discussed in the order above.

3.9.2.1 Load the RMNCER instruction

The RMNCER load operation is carried out by the RMNC miss microinstruction sequence used. RMNCE 519 being loaded

$ 333,457

is selected by the value on name bus 328 during the load operation; EfJlTGER 62? within . BMNCE 519 is activated by the microcommand for the load command specified. If RMNCER 627 (0) is not specified for the load operation, the result is a EMNC error signal if the value in E-TAG 809 is not included matches the value on TAG 819, or if the V-Field 622 in RMNCE 519 is an invalid RMNCE 519 specified. If a load operation is carried out on RMNCER 627 0, RMNC 517 automatically sets the BC field 625 to the same value as the base field 641, E-TAG 809 to the value of TAG 819, and the V-Field 622 so that it specifies a valid RMNCE 519. If the base field 641 specifies an address cached in ABC 502 as a base, RMNC 517 also automatically sets ABCF so that it specifies so. In the preferred embodiment 801 of RMNC, the ID field 623 becomes automatic set if RMNCER 627 (0) or EMNCER 627 O) the last loaded register is; if RMNCER 627 (2) or RMNCER 627 (3) is the last loaded register, can the microinstruction sequence specify the value of the ID field 623.

3.9 · 2.2 The RMNCE invalidation operation and the flush operation

The RMNCE invalidation operation is used when a single RMNCE is required 519, for example to invalidate an RMNG

mark as invalid "until all BMNCERs 627 are loaded have been. The EMCTGE that was just invalidated is specified by the value of IUD 817; the operation simply sets the "V-field 622 of the specified EMNGE 519 so that there is an invalid EMFCE specified.

The flush operation is used when all entries in the enhanced address caches 501 need to be invalidated. Ni ¹ G 753 and FLC 729 provide addresses of RMNCEs 610 as described in the discussion of ABC 602, and while each EMNCE 610 is being addressed, its V field 622 is set to 0 as explained in the discussion of validity memory 804 became. As explained above, such a general validation is only required if the execution of a call or return instruction results in a change in the value of SDP, PBP or NTP, or if the computer system 301 is executing a program that requires a different stack 317 .

3.9.2.3 Read the RMNCER instruction and resolve the RMNCEE instruction

The read RMNCER instruction returns the contents of the RMNCER 627, which is specified by the microcommand in RMNCE 519 identified by the value on name bus 328 is specified on the descriptor bus 333. If the value in the E-TAG field 809 does not match the value of the TAG

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matches, or if the specified RMNOE 519 is invalid, an RMNC false signal results and it the RMNC miss microinstruction sequence is executed.

When the EPWCEH operation is resolved, the microcommand specifies an RMNCEH 627 in the HMNCE 519, which is carried out by the value is addressed on name bus 328. In the Operation speaks CTL 515 on the content of the base field 641 in the specified HMNCER 627 in the same way as it relates to the content of BC field 625 during the resolution operation appeals to. Thus, CTL 515 does "that the address offset multiplexer 525 the address offset field 629 and that the base multiplexer 5.11 selects a register in ABRC 504 or the output of ABC 502 selects. If there is no RMNCE 519 accordingly the value on name bus 328 is an RMNC. miss signal the consequence.

3.9.3 Example of the operation of the EMNC 517 under Microcode control - Fig. 9

The way in which the RMNC 517 operates under microcode control can be represented by describing how a table name 4-03 is an element of a Area specified, is resolved. NTE 310 specified in computer system 301 for an element of a field three things:

- The address offset of the field (array) compared to a base address.

ORIGINAL INSPECTED

• ο β ··

- The index of the 'field element.

- The size of the silk element.

In the NTEs 310 in the computer system 30i, the base address, the value of the index, and the dimension, respectively can be represented by a name 401. For the present example it is assumed that the base address for the field SDP is that the address offset is 64 that the field index is the first argument used to the procedure containing the table name 403 and that the size of the silk element is 80 '. Since the "fieldindgx, - is an argument, it can be entered in NTE 310 be represented by an immediate name 409 specifying an argument pointer 601 «If the Table name 403 is offered to the HMNC 517 for the first time an RMNC miss occurs and the microcode RMNCE 519 loads with it according to table name 403 Information from NTE 310.

Figure 9 shows the resulting RMNCE 519. For purposes In this example it is assumed that RMNCER 627 (0) contains information from which the address of the index is extracted that RMNCER 627 (1) contains the element size and that RMNCER 627 (2) contains information from which the address of the field can be extracted. RMNCER 627 (3) is not used. Other arrangements are of course possible. In general, however, the information for the index is placed in RMNCER 627 (0), because the index value is needed to find the address of the

Field element to "compute, and therefore from memory

305 must be obtained while the address of the Field itself is just obtained from the information in HMNCER 627 (2).

The ABCF field 621 of RMNCER 627 (O) is set in such a way that that it indicates that ABC 502 provides the base; the ID field 623 contains a value from which the controller 327 can derive the memory location of the microinstruction sequence, which are used to process the EMNCEs 617 for fields. is det; the BC field 625 and the base field 641 contain both the code 001, which indicates that a base is cached in ABCj the address offset field 629 contains the Value 0, and the ADISP field 639 specifies the argument pointer 601 with an address offset of -128 compared to FP. BMNCER 627 (1) only contains the element size, namely 80, in the address offset field 629. The base field 64-1 and the ADISP field 639 are unused. In RMNCER 627 (2), the address offset field 629 contains the value 64 den Address offset of the! Field compared to SDP, and that Base field 641 contains the code 010 which specifies a direct address based on SDP. The ADISP field 639 is not used.

If the table name is 403 according to the example RMNCE 519 appears on name bus 328, enters RMNC hit signal on. In response to the BC field 625 of RMNCER 627 (0) causes CTL 515 the address offset multiplexer 525j the address offset field 629 as its Select input and cause the base multiplexer

ORIGINAL INSPECTED

Select ABC 501 as its input. ABC 502 used the value of ADISP 639 to ABCE 503 in the current ABC frame 607, which is represented by the first argument pointer 601 in the top frame 321 Contains address and outputs the address. The address adder 503 adds those contained in the address offset 629 O'to the address from ABC 502, and therefore the argument pointer 601 for the first argument is Speaking address to descriptor bus 333 is output.

At the same time, the value of the ID field 623 becomes the control 627 is output and the controller 627 begins executing the microinstruction sequence for processing the Field - BMNCEs 519 The microinstruction sequence begins by getting the address obtained from the triggering of BMNCER 627 0 was used to perform a memory read operation. The read operation will be the Return the value of the .field index to the 329 descriptor processor. While waiting for the index value to recur, the microinstruction sequence uses the operation Resolve BMNCER for EMNCER 627 (2) to get the .field address to obtain. In this operation, the base field 641 is output to CTL 5 ^ 5, which responds in such a way that there is the base multiplexer 511 for selecting the SDP master 507 as its input and the address offset multiplexer 525 to select the address offset field 629 from the RMNCER 627 (2). Address adder 513 then adds the value 64 that is in the address offset field 629, at the current value of the. SDP register. 507 and outputs the result to the descriptor bus 333.

The microinstruction sequence stores the field address generated in this way in a register in the descriptor processor 329 and uses the RMNCER read operation to obtain the element size from the address offset field 629 of the RtWCER 627 (1). The RWiTCER read operation simply outputs the contents of RMDTCER 627 (1) to descriptor bus 333 and the microcode sequence manipulates it to obtain the value of address offset field 629. At this point at the latest, the index value has come back from memory 305, and the microinstruction sequence uses components of descriptor processor 329 to calculate the address of the field element by multiplying the index value by the small size and * by adding the result to the J field address. ■

The caching device described consists of a first one Cache, a second cache connected to the first cache, made up of registers for storing data, a Adder, the input signals from a first multiplexer connected to the first cache and from one to the second Cache and the registers connected to the second multiplexer, and from a control device connected to the first Cache, the first multiplexer and the second multiplexer is connected. The first cache gives in response to one Key out a cache entry. The cache entry contains a first address offset value, a base specifier specifying either one of the registers or the second cache, and in the case of entries that specify the second cache specify a second address offset value. The first address offset value is output to the first multiplexer, the base specifier is output to the controller, and the second address offset, if any, is issued to the second cache. The control device

responds to the base specifier by the first multiplexer issuing the Address offset value and causes the second multiplexer to select one of the values specified in contained in the E registers, or by the second Cache in response to the second address offset selects value returned. The adder then adds that value selected by the first multiplexer to the value selected by the second multiplexer and gives aas result.

The invention is also capable of other specific embodiments be realized without departing from the essence and essential characteristics of the invention. Therefore, the present embodiments are intended to be illustrative in all respects only and are not intended to be Cause restriction.

Claims (1)

Claims M.JApparatus for storing ("caching") certain data elements in a cache in a data processing unit which is responsive to certain data elements which contain a first component, the value of which changes in response to a first operation of the data processing unit, and a second component whose value changes as a response to a second operation of the data processing unit,
characterized in that the caching device comprises: (1) A first cache for storing and outputting the first components; (2) a second cache for storing and outputting the second components; and (3) an output combining means connected to the first cache and the second cache and the first component output from the first cache and that output from the second cache second component receives and these two components to form the specific data element combined. Device according to claim 1, characterized in that that the central data processing unit executes call and return operations; that the "particular data items are addresses; that the first component is a base address;" that the first operation is any one of said call and return operations; that the second component is an address offset; and that the second operation by "certain operations the named call and return operations is formed. Device according to claim 1 or 2, characterized in that that the combining means the address offset to the base address for the purpose of generating the Address added. Device according to Claim 2, characterized in that the second cache contains certain addresses their values are only in response to the specific commands from the call and return commands mentioned change; and that the combining device takes the address from one of the specific addresses without using the base address generated. 5 «device according to one of the preceding claims, characterized, that the first cache has a first means of invalidation depending on the first Operations; and that the second cache has a second means for invalidating depending on the second Operations. 6. Device, in particular according to one of the preceding claims, for use in a digital computer sy st em with (1) processing means for performing operations on data in response to commands; (2) a memory device for storing data items of the data and the commands and for Receiving the data elements from the processing device and for delivering the data elements and the commands to the processing device in response to certain signals from the processing device including addresses, the memory locations specify in the storage device, and (3) a message transmission device for transmitting the commands, the specific signals and the data elements between the processing device and the storage device, and.wherein the storage device contains (a) procedures that contain at least the commands, and Cb) a stack to store the "when executing the procedures data elements used by the processing device, the Stack has a frame that every * unfinished execution (execution) is assigned, whereby the framework is associated with the execution of the Procedure for which the processing device is currently executing the instructions include associated top frames, which at least include operations (a) a call operation to suspend the execution in progress, to start another Execution, and to create the frame assigned to the other execution and (b) a return operation to terminate the other execution and resume the execution of the procedure suspended by the call operation beginning the other execution certain addresses are specified by (a) a base address component specifying a base of the addresses, and (b) an address offset component which is an address offset from the Base address specified as specified by the base address component is and * fr The "specific addresses" include frame-based addresses defined by a frame-based component of the basic components and the address offset components used in the Addition to the basic component specify the addresses in the top frame, characterized in that the caching device provided in the processor device for Caching the frame-based addresses includes: (1) register means for storing the frame base component and outputting the Frame base component; (2) a cache to store the address offset components and for outputting the address offset components; and (3) an output combining means connected to the register means and the cache for Receiving the frame base component from the register means and receiving the address offset from the cache and the frame base component and the address offset combined to form the frame-based addresses. 7-. Device according to one of the preceding claims, in particular according to claim 6, characterized in that the device has: (1) a loading device for loading the kegister device in response to each call operation and each return operation, the loader ti * on each invocation operation by loading the frame base component for the top frame corresponding to the "just started" by the call operation Execution in the register device responds, and to each return operation by loading the frame base component for the top frame corresponding to that resumed by the call operation Loads execution into register facility; and (2) means for invalidating the addresses certain call operations and certain return operations for invalidating the cache device. 8. Digits1 computer system with (1) a processing device for executing Operations on data in response to commands, (2) a memory device for storing data items of the data and the commands and for Receiving the data elements from the processing device and for delivering the data elements and the commands to the processing device in response to certain signals from the processing device including addresses, the memory locations specify in the storage device, and (3) a transmission device for transmitting the commands, the specific signals and the data elements between the processing device and the storage device, and where certain commands contain a first name representing a data item; certain addresses are specified by (a) a base address component, which is a Base address of the addresses specified and ("b) an address offset component that specifies an address offset from the base address specified by the base address component is, the storage device contains (a) Procedures that contain at least the commands, and (b) a name table assigned to each individual procedure, which contains a name table entry which is assigned to each first line is the procedure assigned to the commands in the name table is included, with the name table entry for the first name contains a first base specifier specifying one of the base addresses and a Contains address offset specifiers from which to derive the address offset can, which at least include operations (a) a call operation to suspend execution of one of the procedures and to Start another execution, (b) an eeturn operation to terminate the other execution and resume the execution of the procedure, the call operation beginning this other execution was exposed, (, U · ■ »τ. - a plurality of the base addresses is assigned to each execution and the first base specifiers in the name table entries for the first names in the commands in the procedure just executed, the base addresses specify in the plurality of base addresses assigned to the execution, a caching device that accesses the first names by caching the first addresses in the processor means responds, and which responds to one of the first Hamen by issuing the specific Address whose base component is the base address specified by the first base specifier and its address offset is obtained from the address offset specifier in the name table entry for is the address offset derived from the first name and that the caching device comprises: (1) a first cache to receive the one first name and to react to the first name by outputting the address offset, that from the address offset specifier in the name table entry for the name and from a second base specifier specifying the base address component identified by the first base specifier in the name table entry for which a first name is specified is derived; (2) one on the call operations and return operations nice facility for invalidating the first cache only when the call operation the other version for those assigned to a first different name table Procedure begins and when the return operation resumes execution for the procedure associated with a second differing name table; (3) a second cache to receive the second base specifier from the first cache and to the Responding to the second base specifier by returning the base address identified by the second Base specifier is specified ,,, where the second cache contains the plurality of base addresses, that of the currently by the processor facility is assigned to the executed execution; (4) means for indexing certain base addresses from the plurality of base addresses in response to every call command and, every return command, which is executed by the processor device j and (5) means for receiving the base address component from the second cache and the address offset component from the first cache and to combine the base address component and the address offset component to generate the particular address for the data element represented by the first name. 9. Eineachvorrichtung according to one of the preceding Claims, in particular according to claim 8, characterized in that the data elements include pointers specifying the address; that certain pointers are base pointers associated with an execution and their advertising up to Do not change end of execution; 10 '' ■ that the base addresses cached in the second cache comprise the addresses from the base pointers; and that the caching device further comprises means responsive to each call operation, the addresses from the base pointers that correspond to the execution just started by the call operation is assigned to load into the second cache. 10. Device according to one of the preceding claims, in particular according to claim 9, characterized in that that the base pointers associated with an execution specify the addresses of the data elements to be used as Arguments to be used for an execution. 11. Device according to one of the preceding claims, in particular according to claim 8, characterized in that that the storage device comprises: (a) a stack to store the data items that are generated when the Procedures used by the processing facility, the otapel for each unfinished execution one of these associated frames, wherein the frames comprise a top frame, the implementation of the Procedure is assigned for which the processor device is currently executing the instructions, and • j xi *> * (b) a Static Data Area (statJc data area) that is associated with your .Stapel, ur: to further store the data items, the performance of procedures used in the Verarbeitungseinricbtung \ ei; further characterized in that the call operation continues to create the stack frame associated with the execution initiated by the call operation;
that the base addresses include (a) a frame base address specifying an address to which the address offsets are added to get the addresses of the memory locations in the top frame, (b) a static data base address specifying an address to which the address offsets are added to the addresses of the storage locations in the static data area to get, and (c) a procedure base address specifying an address to which the address offsets be added to the addresses of the memory / • s. ■ put in by the processor device to get the currently running procedure, and that the facility for changing the determined Base addresses the procedure base address and the static data base address only as Reaction to certain call operations and certain return operations changes and sets the frame base address to be used in response to each call operation Framework for by the call operation ■ sets execution started, and that it sets the frame base address so that it in response to each return command, the framework for the return command specified resumed execution, 12. Device according to one of the preceding claims, in particular according to one of claims 8, 9 or 11, characterized in that the first cache second "contains specific entries that have a full address and a second Contain base specifier that does not contain any of the base addresses specified; and that the Oache device corresponds to the first name responds to the second specific entries by outputting the unchanged complete address. 13 · Digital computer system, in particular according to one of the preceding claims, characterized in that it comprises: (1) processing means for performing operations on data in response to commands; (2) memory means for storing data items of the data and commands and for Receiving the data elements from the processing device and for supplying the data elements and the instructions to the processing device as Response to specific signals from the processing device, the specific signals being addresses which specify storage locations in the storage device, and (5) a transmission device for transmitting the commands of the "specified signals and the data elements between the processing device and the storage device,"
and where the data elements include pointers specifying the address;
the storage device contains: (a) Procedures comprising at least the commands, and Cb) a stack for storing the data elements, which "are used in the execution of the procedures by the processing facility, wherein the stack has a frame associated with the unfinished execution, wherein the frames comprise a top frame associated with the execution of the procedure for which the processing device is currently executing the instructions, and where certain frames base pointer is the Contain pointers, their values up to the completion of the execution associated with the frame remain unchanged, and that the operations include at least (a) a call operation to suspend the one currently being executed Execution that begins another execution and to accomplish that of the other Execution associated frame and (b) a return operation to terminate the other execution and resume the execution of the procedure, the call operation initiated by the "other execution" suspended was, and that certain instructions include an operand representing one of the base pointers in the topmost frame and contains an address offset when it is added to a particular one Address supplies the address of the base pointer represented by the operand, and that a caching device is provided for caching the base hands, which caching device e responds to each of the operands by returning the address specified by the base pointer represented by the operand and that the caching device comprises: (1) a memory device with a plurality of register devices for storing the addresses, which are specified by the base pointers in the top frame, and for outputting the in a the address contained in the register facilities as Response to an address received in the storage device; (2) an addressing device for receiving the Address offset and to supply the register address to the memory device in response to the air food offset; and (3) eLne device responsive to the call operation for storing each of the base pointers contained in the frame identified by the call operation was created in the frame, and for loading each of those represented by the base pointer Addresses in the register device, which are provided by the addressing device in response to the address offset which specifies the location of the base pointer in the frame. 14. The device according to claim 13 »characterized in that that the register means the addresses specified by the base pointers in a plurality of the determined Frame includes; that the caching device has a means for allocating of each address specified by the base pointer to "has certain frames that contain the contains base pointer representing the address; and that the caching device only provides these through the base pointers outputs addresses represented in the top frame in response to the operands. 15. Device according to claim 13 or 14, characterized in that that the base pointers represent the addresses of the data elements that are used as arguments in the call operation be used that indicate the bisis pointer containing framework creates. 16. Device for storing (caching) data in a cache in a digital computer system, in particular according to one of the preceding claims, characterized in that it comprises: (1) a first cache for outputting first data in response to a first key; (2) a second cache for outputting second data in response to a second key; and (3) a corabinetic device that begins with the first and second cache is connected and the first data from the first cache and the second data from the second Cache essentially simultaneously receives and generates the first data and the second data combined by third data. 17 · Device according to claim 16, characterized in that since 5 the combining device is an adder and that di-3 third data is the idum of the first data and the two dates are .. 18. Apparatus according to claim 16 or 17 _5, characterized in that it comprises: : "::": · j L * ' ^: . ^: -./33 3 k (1) a first invalidation facility for Invalidating the first cache in response to first specific operators of the digital computer system, and (2) a second revocation directive for Invalidating the second cache in response to certain second operations of the digital computing system. 19 device for caching in a digital computer system, in particular according to one of the preceding Claims, characterized in that it comprises: (1) a cache for outputting first data and second data in response to a key; (2) a storage device having a plurality of registers for storage and output third data contains: and (3) a controller connected to the cache and the storage device for selection of the third data in one of the plurality of registers in response to the second dates. 20. Apparatus according to claim 19, characterized in that that it has: (1) a ühgültigmachungseinrichtung invalidation of the first cache in response to ERS _f te certain operations of the digital computer system; and (?) a .charger for charging at least one from the plurality of registers in response to a second particular operation of the digital Computer system. 21. Device according to claim 19j, characterized in that that it has a combining device with of the control device, the cache and the storage device is connected to the first and the receive third data substantially simultaneously with the first data and the third. Data to perform an operation under the control of the control device and a result of this Output operation; and that the control device is the combining device j η controls dependence on the second data. 22. The device according to claim 21, characterized in that the control means is responsive to the second data by causing the combining means performs one of the following operations: adding the first data and the third »Rf. »Μ Λ · ♦ · · - 19th Data for generating fourth data, outputting the unchanged first data, and outputting dex * unchanged third dates. 23. A teaching device in a digital computer system, in particular according to one of the preceding claims, characterized in that it has: (1) a first cache, responsive to a first key, for outputting first data and a second key; (2) a second cache connected to the first cache for outputting second data in response to the second key; and (3) a combining device connected to the first cache and the second cache to essentially simultaneously the first data - and to receive the second data and a Output the result of an operation on the first data and the second data. 24. The device according to claim 23, characterized in that that it has: ... (1_) . a first invalidation facility for -. . _; . · Invalidate the first cache in response to first specific operations of the digital computer system; and (2) a second invalidation facility for. Invalidating the second cache in response to certain second operations of the digital Computer system. 25. Performing according to claim 231, characterized in that That is, the second cache has a plurality of indexes contains addressable register facilities, wherein ^. . each index one register device of the plurality the registry facilities specified; and that the second key contains one of the indices. 26 performing according to claim 23, characterized 'ai-B has a selection means, the second cache which is connected to the first cache, and with an additional source of the second key, the second key uii from the first cache or additional d'ir Select source. ?. '('. Apparatus as claimed in any one of claims 23 to 26, that the combining operation performed by the de-addition of the first data with the second Daben. 28. Apparatus according to claim 27, characterized in that the first cache also provides third data as a response spent on the first key; ' that the combining device also performs the operation of outputting the unchanged first data and the · Executes outputting of the unchanged second data; and that the caching device also includes a control device associated with the first cache and the Combining device is connected to one of the operations depending on the third data to select. 29. caching device in a digital computer system; in particular according to one of the preceding claims, characterized in that it has: (1) a key receiving device for receiving a first key and a second Key from the digital .computing system; (2) a first cache associated with the key receiving device connected and on responsive to the first key to output first data and a second key; and (3) a second cache connected to the key receiving device and to Cem first cache and responsive to the first key and the second key to access the first key to respond by getting the second key from the first cache receives and otherwise receives the second key from the key receiving device and respond to the second key by outputting the second data. 30. The device according to claim 29 »characterized-, that it has: (1) a first invalidation facility to invalidate the first -Gache in response to first particular operations of the digital computing system; (2) a second invalidation facility for Invalidating the second cache in response to certain second operations of the digital Computer system; and (3) a loader for loading at least one of the registers in response to the second determined one Operations. 31. The device according to claim 29, characterized in that that it has a combining device connected to the first cache and the second cache, to receive the first data and the second data substantially simultaneously and the first data U] id to add the second data if the second C.iche the second key from the first cache e.ip catches. 32nd. A teaching device in a digital computer system, in particular according to one of the preceding claims, characterized in that it has: (1) a first responsive to a first key Cache for outputting first data, second data and a second key; (2) a second, on the second key responsive cache connected to the first cache for outputting third dc ben is; (3). storage means for outputting a plurality of fourth data items; (4). a combining device associated with the first Cache, the second cache and the storage device is connected to essentially simultaneously input data including the first data, the third data and the To receive a plurality of fourth data elements, an operation is performed on the input data perform a plurality of operations and output a result of the operation; and _ COPY (5) a control device that works with the first Cache and the combining device is connected to receive the second data and the one executed by the combining device. · · Operation depending on the second Data to determine. 33 · "Device according to claim 32, characterized in that that. the second cache has a plurality of register facilities which can be addressed by an index, the one register device from the plurality of register devices specified; and that the second key comprises the index. 34. Device according to claim 33 »characterized in that that the second cache comprises a selector, which is connected to the first cache and an additional source of the second key to the second Select keys from the first cache or the additional source. 35 Single-teaching device in a digital computer system, in particular according to one of the preceding claims, characterized in that it has: (1) a key receiving device for receiving a first key, a second key, and a third key including the first Data from the digital computer system; (2) a first cache associated with the key receiving device; and on the responsive to the first key to output second data, third data and the second key; (3) a second cache connected to the key receiving device and the first cache and responsive to the first key and the second key to respond to the first key by receiving the second key from the first cache and otherwise the second key from the Receiving key receiving means and responding to the second key by issuing fourth digits; (4) a storage device for storing a plurality of fifth data items; (5) a combining device, which m.i.t the key receiving device, the first cache, the second cache and the storage device is connected to input data including the first data, the second data, the fourth data and the plurality of five-tone data elements receive substantially simultaneously, one of a plurality of operations perform on the input data and output a result of the operation; and (6) a control device that communicates with the key receiving device, the first cache and the combiner is connected to the third parties to receive data and parts of the key. . and that of the combining device as a function of determine the operation performed by the third data and the parts of the keys. 36. Apparatus according to claim 35, characterized in that the operations comprise: '(a) the addition of the first data and a selected one Elements from the majority of the fifth data elements; (t) the addition of the second data and a selected one One of the plurality of fifth data items; (c) outputting the unchanged second data; (c) adding the second data and the fourth data; («·) Outputting the unchanged fourth data, and (.Γ) output of the unchanged selected element from the fifth data elements. 37 · Device according to claim 35 »characterized in that that the combining device contains: (A) an adder with a first input, a second input and one output; (b) a first selection device connected to the first cache, the key input device, the control device and the first input is connected to alternatively the first data and to supply the second data to the adder in dependence on the control means; and (c) a second selection device associated with the second cache, the control device and the second input is connected to alternatively an element from the majority of the fifth Daben- - elements or the fourth data element to the auditor in response to the control device to feed. 38. A teaching device in a digital computer system, the 'on operands including the first Operands including a key and second operands including a first Base value specifier and a first address offset value, characterized by "., that the caching device; having: original jmsfected - - copy 28 (1) means for receiving the operands from the digital computer system; (2) one connected to the operand receiving device Cache for outputting a second base value specifier and a second address offset value in response to the key; (3) a storage device for storing a plurality of base values and for outputting the Majority of the underlyings; (4) a combining means associated with the cache, the storage means and the operand receiving means connected to simultaneous input values. 'including the first The address offset value from the second operands, the second address offset value from the cache, and to receive the plurality of base values from the storage device, one of the values Perform one of a plurality of operations and output a result; and (5) a control device in communication with the operand, receiving device, cache and combining device is connected to cause the combiner to select certain input values and one of the plurality of Operations with the specified input values ■ Execute in response to the first operand and the second base value specifier or in response to the second operand and the first base specifier. 39 · Device according to claim 38, characterized in that that the control device is based on the first operand received by the operand receiving device and is responsive to the second base specifier by causing the combining means a first selected base value from the plurality of base values in response to the second base value specifier and a first operation of combining the first selected base value with. the second address offset value; and that the control means is responsive to the reception of the operands device responds to the second operand received by causing the combining device a second selected base value from the defense number of base values in response to the first Base value specifier and a second operation of combining the second selected Base value with the first address offset value. 40. Apparatus according to claim 39, characterized in that that the cache return complete values in response to certain first operands; that a certain second base value specifier still does not contain one of the plurality of base values specified; that the combining device contains the complete values . , from the. Cache receives; and that the control device on the specific second The base value specifier responds by causing the combiner to generate a third Executes the operation of outputting the unchanged complete value. 41. Apparatus according to claim 39, characterized in that the first operation is the. selected underlying with the second address offset by adding the . the second address offset combined with the selected base value; and that the second operation shifts the selected base value with the first address offset to the left and character completion of the first address offset and by adding the left-shifted and character-supplemented first address offset combined to the selected base value. 42. Device according to one of claims 38 to 41, characterized marked, that the digital computer system performs a call operation and a return operation; and that the calibration device also contains: (1) a memory loader responsive to each call operation and each return operation, for loading the base values into the storage device; and (2) a cache invalidator based on addresses certain call operations and certain return operations to invalidate the cache do· 43. caching device in a digital computer system; that on operands including first operands including a key, second operands including a first base value discriminator and a first address offset value, and third operands including a second base value over-specifier and the first address offset value, characterized in that the caching device having: (1) means for receiving the operands from the digital computing system; (2) a first cache that handles operand reception means connected for outputting values including a third base value specifier, the first address offset value, and a second address offset value in response to the key; GHIGIINAL INSPECTED 32 (3) a second cache connected to the operand receiving means and the first cache is to respond to the first operand by outputting a first base value in response to the first address offset value obtained by the first cache in response to the key has been issued, and in order to address certain third operands, that it has the first base value in response to the first address offset value in the third Outputs operands; (4) a memory device for storing a plurality of second base values and for outputting them the second base value; (50 a combining device which communicates with the operand receiving device, the first cache, the second cache, and the storage device is to simultaneously input values including the first address offset value from the second operands, the second address offset value from the first cache, the first base value from the second cache, and to .receive the second base values from the storage device, to perform one of a plurality of operations with these values, and a Output result; and (6) a control device, the mLt of the operand receiving device, the first cache, and the Combining device ι is to bring about that the combining device the one Operation as a reaction to dej. first base specifier executes, renn the operand receiving means receives a second operand in response to the second base specifier, when the operand receiving means receives one of the third operands, and in response to the third base value specifier, if the operand receiving device receives one of the first operands. Apparatus according to claim 43, characterized in that the control device is activated on the first by the Operand receiving means received operands and to the third base value specifier thereby responds that it causes the combining device a selected base value from the first base value and the plurality of the second base values in Depending on the second basic advertising specifiers and a first operation of combining executes the selected base value with the second address offset value; that the control device is based on the second operand received by the operand receiving device is responsive by causing the korabihi device to pick a second base number from the plurality (i.er selects a second base value in response to the first base value specifier and - a second Operation of combining the selected second base value with the first address offset value . . executes; and let the control device respond to the third operand received by the operand receiving device i by responding, that it causes the combiner selects the first base value and "a third operation of unchanged spending of the first underlying. 45. Apparatus according to claim 44, characterized in that that the first cache return complete values in response to certain first names; that a certain second base value specifier - 'specifies neither the first base value nor a second base value; that the combining device receives the complete values from the cache; and that ä Le control means to the first operand and to the particular underlying second specifier is responsive characterized in that it causes the combining means performs a fourth operation of the outputting of the unmodified full value. 46. Apparatus according to claim 44, characterized in that the first operation uses the selected base value combined with the second address offset by adding the second address offset to the selected base value; and that the second operation executes the selected second base value with the first address offset Left shift and character completion of the first address shift and by addition the left shifted and ζ oak-supplemented first address offset combined to the selected base value. 47. Device according to one of claims 43 to 46, characterized, that the digital computer system is a call operation and executes a return operation; that the caching device further comprises: (1) a memory loader that responds to every single call operation and jec-e individual. Return operation responds to at least one of the plurality of second base values in the Load storage device; (2) a first cache invalidation facility, which responds to certain call operations and certain return operations to the first Invalidate cache; and (?) a second cache invalidation facility, on every single call operation and every responds to a single return operation to invalidate part of the second cache. 4-8. Digital computer system, in particular according to one of the passing claims, with (1) a processing facility for processing data in response to commands; (2) storage means of data items of the data and commands and for receiving the data items from the processing means and for delivering the data items
and commanding the processing device in response to signals received from the processing device, and (5) a transmission device for transmitting the commands, the specific signals, and the data elements between the processing device and the storage device,
and wherein the processor device uses internal addresses S3n to read the memory device, and wherein the addresses contain: (a) a base address component specifying a base address in the memory device, and (b) an address offset component which is an address offset specified in relation to the base address component, and wherein certain instructions have a first representative of a data item in the storage device Names include, and wherein the storage device further includes: (a) Procedures that contain at least the commands and (b) an N; un table assigned to each procedure, where the table of threads contains every first name in the instructions in the table of threads associated procedure contain i:; t, associated name table entry contains, and where the name table entry for the first Naaen contains (I) a first base specifier which is a specified from the majority of the base addresses, and (Ii) an address offset specifier which is' Contains information from which the address . offset from the one base address can be calculated by the base specifier specified v / lrd, 38 that a caching device is provided which is responsive to the first names to the internal addresses caching, and that the caching device comprises: (1) an on-the-fly cache for outputting data obtained from the name table entries are derived, where the derived data include: (a) a second base specifier derived from the first base specifier is, (b) the address offset calculated using the address offset specifier D, a memory device containing a plurality of registers for storing and outputting a plurality of the base addresses; (30 a K-combining device, which with the uache and the memory device is connected to the address offset and in the memory device stored addresses essentially simultaneously and a first operation of the Perform adding a selected stored base address to the address offset; and "" a control device that learns with (Jache and the combining means is connected to select the selected stored basic data and causing the combining means to respond to the first operation second base specifier. 4-9. Device according to Claim 48, characterized in that that every execution of one of the procedures a certain A plurality of the base addresses are assigned; that the digital bucket system is a call operation that suspends execution of a calling operation, executes the determined plurality of the base addresses intended for the execution of a called procedure that was started by the call operation, and execution of the called procedure begins; that the digital computer system carries out a return operation in order to execute the called procedure to terminate the majority of the base addresses assigned to the execution of the calling procedure, determine and resume execution of the calling procedure; that the caching device includes means responsive to the call operation to the stored Set base addresses to the specific number of base addresses that are used to execute the called Procedure started by the call operation has been assigned; and that the caching device includes a device which responds to the return operation to the stored Set base addresses to the specific majority of base addresses that are to be executed assigned to the calling procedure, which is resumed by the return '' operation. 50. Device according to claim 4-9, characterized , that certain first call operations execute The procedure called start with a first compared to that used by the calling procedure Name table uses different name table; that first certain return operations the execution of the calling procedure resume the one The second name table used differs from the name table used by the called procedure ; and that the caching device includes a facility that is responsive to the first particular call command and the responds to the second specific return command to invalidate the cache. 51. Apparatus according to claim 49, characterized in that that the derived data contain complete addresses that are derived from the name bar entries specifying a particular base address and that particular second base specifier specify the complete addresses; that the combining device continues a second operation of receiving the complete. address from the cache and outputting the unchanged complete address; • That the control device continues to respond to the specific second base specifier by causing the combiner to execute the perform second operation; that the first specific call operations begin the execution of the called procedure, the one The first one differs from the specific base address used by the calling procedure uses certain base address; that first certain return operations the execution restart the calling procedure that used one of the called procedure specific base address uses different second specific base address; unc. that the caching device includes means responsive to the first specific call commands and the responds to the first specific return command to invalidate the cache. 52, cache for outputting data in response to a Keys in a digital computer system, in particular according to one of the preceding claims, characterized in that the cache has: (1) means for receiving the key; (2) a plurality of frames, each frame of the plurality of frames being a register device to save the data contains; (3) frame selection means for selecting a first frame from the plurality of frames as a current frame; and (4) a device associated with the key receiving device of the register device and the frame selection means is connected to retrieve the data from the register means in response to issuing the key in the current frame. The cache of claim 52, characterized in that each frame includes a plurality of said register means has en; that the key contains an index which a register facility specified from the plurality of register devices; and that the data output device responds to the frame selection device and the key, that they are in the one register device that specified by the index in the current frame. Apparatus according to Claim 52, characterized in that the frame selection device generates a new current one Selects frames in response to certain operations of the digital computing system. 55 · Device according to claim 54 · »characterized in that that the frame selector is the current frame selects from a sequence of the plurality of frames; and that the new current framework is in the current framework the sequence is immediately adjacent. 56. Apparatus according to claim 52, characterized in that that the frame selection means further selects a second frame from the plurality of frames as a next frame; and
that the cache also contains: (1) means for receiving the data to be stored in the cache and (2) a data writing device which is connected to the data receiving device, the frame selection device and the key receiving device and which is responsive to the frame receiving device and the key in order to convert the data . '' to write in the register facility in the current frame or in the next frame, which is specified by the frame selector. 57. Device according to claim i> 6, characterized in that that the frame selector creates a new one current frame and a new next frame in response to certain operations of the digital Computer system selects. 58 '. Device according to claim 5'Λ characterized , that the frame selection device matches the current frame and select the next frame from a sequence of the plurality of frames; and that the next frame is the frame that follows the current frame in sequence. 59. Apparatus according to claim 57 or 5Ö, characterized , - the digital Reoimer system ate call operations and perform return operations; that the specified operations include the call operations and the return operations; that the frame selector responds to the call-up operation by having the frame, which follows the current frame in sequence, selects as the new current frame; and that the frame selection device on the return operafcion by addressing the frame that precedes the current frame in the sequence, as the new current frame. 60. Device according to one of claims i? 6 "to 5ö,
characterized by that the cache continues to have a facility for
Receiving a first signal that the current one
Frame specified, and a second signal specifying the next frame;
that each frame contains a number of registers; '. that the key contains an index which a register facility specified from the plurality of register devices; that the data output device responds to the frame selection ■ device and the key, that it outputs the data in the one register device specified by the index in the current Frames are included; that the frame selection device with the signal receiving device and is responsive to the first signal by passing the current frame selects and is responsive to the second signal by selecting the next frame; and that the data writing device continues to respond to the index and specified the data in the in the index Writes registers in the frame specified by the frame selector. 61. Caching device in a digital computer system, in particular according to one of the preceding claims, characterized in that it is a stack memory contains, which has: (1) a first plurality of register means for storing data and outputting the stored data Data from one of the register devices in response to an address provided to a register device specifies that the first plurality of registers are divided into a plurality of frames is subdivided in that each frame contains a second plurality of register devices, and that the address, a frame address specifying one frame out of the plurality of frames, and a one Register device from the second plurality of register devices in that by the frame address specified frame specifying register address contains; (2) means for receiving a key in the caching device; (3) an addressing device associated with the key receiving device and the first plurality of ^. Register facilities connected to the address in response to the (key to be delivered, and which includes: (a.) A frame addressing device for delivering a current frame address of a sequence of frame addresses as the frame address in the address, 4? (bj an incrementing device that works on the first Operation of the digital computer system responds to the current frame address in the Change the frame address in the order that follows the current frame address, (c; a decrementer, which is based on a second operation of the digital computer system responds to the current frame address in the Frame address in the order preceding the current frame address , and Cd) a device for supplying a register address, to derive the register address in the address from the key. 6'd. Apparatus according to claim 61, characterized in that the register means in the first plurality of ■ register means further contains validity information which specifies the validity of the stored data and outputs the validity information in response to the address; and that a device is provided which is based on the validity information responds to load the register device addressed as a function of the key, if the validity information indicates that the addressed register device invalid are. 6y> * apparatus according to claim 61, characterized in that the succession of frame addresses is a circular sequence of Eahmenadressen, including the frame addresses of the Bahmen in the plurality of frames of the first frame in said first plurality of register means to the last frame in the first Plurality of register devices _; and in that the frame address for the last frame in the first plurality of register devices precedes the frame address for the first frame in the first plurality of register devices in circular succession. 64. Device according to claim 6, characterized in that that the means for supplying the current frame address is a cyclic counter for counting a sequence of values including as many values as there are frames in the plurality of frames; that the incrementing device increments the cyclic counter; and that the decrementer the cyclic counter decremented. Apparatus according to claim 61, characterized in that ^ that the frame addressing device continues to deliver a next frame address, that of the current frame address follows in the sequence of frame addresses; that the incremental device continues to change the next frame address to the frame address in the sequence that follows the next frame address; that the decrement device continues to change the next frame address to the frame address in the sequence which precedes the next frame address; and
that the Eineach device furthermore has: (1) means for receiving the data to be stored in the caching device and (2) a data writing device based on the Addressing device responds to the data in the register device in aem current Frame or the next frame specified by the addressing means is. 66 · Door direction according to claim 6>, characterized in that etass the facility for supplying the current frame address is a first cyclic counter for supplying a first value of a sequence of values which include as many values as there are frames in the plurality of frames; that the means for supplying the next frame address is a second cyclic counter that supplies a second value of the sequence of values, which immediately follows the first value in the sequence of values; that the incrementer the first cyclic Counter and the second cyclic counter at the same time incremented; and that the decrementing means the first cyclic counter and the second cyclic counter at the same time decremented. 67 · Device according to claim 65, characterized in that that the register means in the first plurality of Register devices continue to have validity information which specifies the validity of the stored data and the validity information in Outputs response to the address; and that the caching device continues to be a facility which is responsive to the validity information to the register means addressed in response to the key to load in the current frame if the validity information indicates that the addressed register device are invalid. 68. Apparatus according to claim 65, characterized in that that the addressing means the next Rahuien address in response to the first operation, the data writing device supplies data in the register device that is specified by the addressing means in response to the first operation will. 69- Device for setting the validity information · For a plurality of first registers, in particular for a computer system and / or a caching device according to one of the preceding claims, characterized in that it comprises: (1) a first read-write memory, in particular Eandom memory, the η first register and a device for receiving a first Has an address that addresses one of the η first registers; ·· '(2) a plurality of m second write-read memories, in particular random storage, for storing the validity information, where each of the second read-write writers contains at least two registers, each the second register in a first memory; the second read / write memory; a first Corresponds to a register whose first address is divisible by m without a remainder, where each of the second register in a second memory of the second read-write memory a first register whose first address has a remainder of 1 when divided by m, and so on up to an m-th memory of the second read-write memory, each : Register of the specific second register in the m-th memory to a first register whose first address when divided by m has a fiest of m - 1, and each .Memory of the second read / write memories, a device for receiving a second Address contains; '(3) an addressing device for the second read / write memories, which is connected to the plurality of second read-write memories to simultaneously a second address to the means for receiving the second address in every other Supply read-write memory; (4-) means for providing validity information associated with the plurality of the second Read / write memory is connected to simultaneously send the validity information to every second Supply read-write memory; and / ■ · an activation device with the number the second read-write memory is connected to simultaneously every second read-write memory to activate the validity information in the second register in every second To store read / write memory that is addressed by the second address. : :: - :. *:::. '* ^: 333457 53 VO. Device for enforcing the validity. 3 information according to claim 69 »characterized in that the device for setting the validity information continues to have (1) a first write-read-write-memory addressing device, which is connected to the device for receiving the first address in order to transfer the first address to the first write-read memory to deliver, (2) a first signal receiving device for Receiving a first tisignal specifying that the validation iniormation in the particular second register must be loaded, which corresponds to the first by the first address corresponds to the addressed register; and {j>) a second signal receiving device for receiving a second signal which specifies that the validity information must be loaded simultaneously into a plurality of the specific second registers; that the second write-read-memory addressing device having: first address transformation means coupled to the first read / write memory means and responsive to the first signal for receiving the first addresses from the first read / write memory addressing means and providing the second addresses which are the same to the integer results (integer result) of the division of the first address by m in response to the first address signal, and (bj a second address generating device, responsive to the second signal to generate the second addresses; and aass the activation device with the first signal receiving device, the second signal receiving device and the first read / write memory addressing means is connected, contains means for alternatively a memory from the plurality to activate read / write memories at the same time, thereby responding to the first signal, that it activates one of the second read / write memories that activates the second register which corresponds to the first register addressed by the address and that it is on the second signal responds in that it simultaneously activates all second read / write memories, _ COPY 55 whereby the device for setting the validity information responds to the first address and the first signal in that they ent- the validity information in the specific second register. 'Speaking of the first register specified by the first address, and that it loads on the second signal reacts by simultaneously determining the validity information in read second register specified by the second address in each of the plurality of the second Read / write memory is loading. 71. Device for putting the validity information according to claim 69 or 70> characterized in that that the first read-write memory 2 ^ first register contains, where j is a positive integer, and that the plurality of second read-write memories 2 contains second read-write memories, where k is one is a positive integer that is less than j. 72. Device for putting the validity information according to claim 69 or '/ 0, characterized in that the first registers are divided into a plurality of frames are divided; and that the second address generating device on cias. second signal responds by never generating the second addresses specifying the particular second registers corresponding to the first registers in a specified frame. Device for setting the validity information according to Claim 70 »characterized in, that the first registers in a plurality of frames. are divided; that the second üignaiempfangseinrichtung a plurality the second receives signals including (a) a frame ilush signal indicating that .The validity information must be loaded into the specific second registers that correspond to the first registers in one of the frames, and (bj a full ulush signal, which indicates that the Validity information is loaded into all the designated second registers muji; that the first read-write-memory addressing device device connected to the second signal receiving device is a device for supplying a frame address Contains a frame from the nebrzahi eggs Frames specified and that they respond to aas frame flush signal responds by providing a single frame address and responding to the full flush signal respond by providing a sequence of frame addresses including the frame address for each frame supplies in the first write-ijese-memory; and daü the second address generating device with aer Bahmenadreii delivery facility is connected and. responds to the frame flush signal by cL & B.- it generates the second addresses using the frame address supplied by the frame address generating device and that it generates the VoIi-Flusti signal by generating the second addresses using the sequence of frame addresses supplied by the frame address generating device will respond. 74-. Computer system and caching device, characterized in that that the Eineachvorrichtung a first Has a cache and a second cache connected to it, 75 ·. Computer system and caching device according to claim 7 ^ » characterized by their design according to one of Claims 1 to 73. 76. Computer system and caching device according to claim or 75 »characterized in that the caching device comprises: a first cache, one with this connected second cache, Eegister. for storing Data, an adder, the input signals from a first multiplexer connected to the first cache and receives from a second multiplexer connected to the second cache and the registers, and a control means connected to the first cache, the first multiplexer and the second multiplexer.