DE3310654A1 - Process for sealing flat hybrid modules - Google Patents

Process for sealing flat hybrid modules

Info

Publication number
DE3310654A1
DE3310654A1 DE3310654A DE3310654A DE3310654A1 DE 3310654 A1 DE3310654 A1 DE 3310654A1 DE 3310654 A DE3310654 A DE 3310654A DE 3310654 A DE3310654 A DE 3310654A DE 3310654 A1 DE3310654 A1 DE 3310654A1
Authority
DE
Germany
Prior art keywords
hybrid
hybrid module
semiconductors
covered
unencapsulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE3310654A
Other languages
German (de)
Inventor
Werner 7125 Kirchheim/Neckar Huter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Standard Elektrik Lorenz AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Elektrik Lorenz AG filed Critical Standard Elektrik Lorenz AG
Priority to DE3310654A priority Critical patent/DE3310654A1/en
Publication of DE3310654A1 publication Critical patent/DE3310654A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention relates to a process for sealing flat hybrid modules (1) containing a series of connecting wires (2) at one long side and unencapsulated semiconductors (chips 3) which are connected to the hybrid circuit by bonding and are covered with plastic (6) before the hybrid module (1) is sealed. A two-component epoxy resin is used to cover the unencapsulated semiconductors (chips 3) and the entire hybrid module (1), together with the covered semiconductor (chip 3) is then completely coated or sealed with a protective layer (7) by immersion in a fluidised bed sintering bath, the connecting wires (2) projecting from the hybrid module (1) being left free. <IMAGE>

Description

W.Huter-1W.Huter-1

Verfahren zum Versiegeln
von flachen Hybridbausteinen.Method of sealing
of flat hybrid modules.

Die Erfindung betrifft ein Verfahren zum Versiegeln von flachen Hybridbausteinen, nach dem Oberbegriff des
Patentanspruchs.The invention relates to a method for sealing flat hybrid modules according to the preamble of
Claim.

Bisher wurden auf Trägerplatten oder Substraten von Hybriden unverkapseIte Halbleiter-Chips nach dem Kontaktieren bzw. Bonden zum Schutz mit einem entsprechend ausgebildeten Keramikdeckel abgedeckt. Anschließend wurde derSo far have been on carrier plates or substrates of hybrids unencapsulated semiconductor chips after contacting or bonding covered with a correspondingly designed ceramic cover for protection. Then the

gesamte Hyoridbaustei η mit einer entsprechenden Schutzschicht überzogen. Dies hatte aber den Nachteil, daß die Abdeckung mit einem Keramikdeckel relativ teuer war und die fertigen mit einer Schutzschicht überzogenen Hybridbausteine durch den aufgebrachten Keramikdeckel relativentire hyorid component η with a corresponding protective layer overdrawn. But this had the disadvantage that the cover with a ceramic lid was relatively expensive and the finished hybrid components covered with a protective layer by the applied ceramic cover relative

dick wurden und ein größeres Gewicht aufwiesen.became fat and weighed heavier.

Aus der Internationalen Elektronischen Rundschau 1971, Nr. 12, Seite 302, ist es weiterhin bekannt, die empfindlichen Teile eines auf einen Hybridschaltkreis gebondeten ungekapselten Halbleiters mit einem dauerelastischen
Silikonpräparat vor dem Vergießen im Becher abzudecken bzw. zu schützen. Dies hat jedoch den Nachteil, daß Silikonpräparate die Aushärtung der zum Vergießen verwendeten Epoxidharze verzögern können.From the International Electronic Rundschau 1971, No. 12, page 302, it is also known to replace the sensitive parts of an unencapsulated semiconductor bonded to a hybrid circuit with a permanently elastic one
To cover or protect the silicone preparation in the beaker before it is poured. However, this has the disadvantage that silicone preparations can delay the hardening of the epoxy resins used for potting.

Die Erfindung hat deshalb die Aufgabe, ein Verfahren zum
Versiegeln von Hybridbausteinen anzugeben, das eine ein-The invention therefore has the task of providing a method for
Sealing of hybrid modules to indicate that a single

-3-ORIGINAL INSPECTED-3-ORIGINAL INSPECTED

W.Huter-1W.Huter-1

fache, kostengünstige und chemisch verträgliche Abdeckung der unverkapseLten HaLbLeiter-Chips einschLießt , die später mit dem gesamten HyDridbausteiη mit einer Schutzschicht gegen UmweLteinfLüsse versehen werden.multiple, inexpensive and chemically compatible coverage which includes unencapsulated semiconductor chips, which later with the entire HyDridbausteiη with a Protective layer against environmental influences.

Diese Aufgabe wird durch die im Anspruch angegebenen VerfahrensmerkmaLe gelöst.This task is achieved by the procedural features specified in the claim solved.

Dadurch ergeben sich die Vorteile, daß mit weniger MateriaLeinsatz ein einfacher MontageabL auf gewährleistet ist. Die Abdeckung des auf dem Hybridbaustein montiertenThis results in the advantages that with less use of material a simple assembly process is guaranteed is. The cover of the mounted on the hybrid module

1Q unverkapseLten HaLb Leiter-Chips ist kostengünstiger aLs die bisher verwendete Ausführung. Die chemische Verträglichkeit zwischen der Abdeckung des ungekapseLten Halbleiter-Chips mit dem im Wirbe Isinterbad verwendeten Pulver ist gewährleistet. Der mit einer Schutzschicht versehene Hybridbaustein weist außerdem ein kleineres Volumen und ein geringeres Gewicht auf.1Q unencapsulated half-conductor chip is cheaper than that the version used so far. The chemical compatibility between the cover of the unencapsulated semiconductor chip with the powder used in the Wirbe Isinterbad is guaranteed. The one provided with a protective layer Hybrid module also has a smaller volume and a lighter weight.

Die Erfindung wird anhand eines Beispiels beschrieben. In der Zeichnung zeigt :The invention is described using an example. In the drawing shows:

Fig. 1 einen Hybridbaustein gemäß der Erfindung mit einem unverkapselten Halbleiter-Chip, in Draufsicht,Fig. 1 shows a hybrid module according to the invention with a unencapsulated semiconductor chip, in plan view,

Fig. 2 einen Hybridbaustein nach Fig. 1 , in Seitenansicht,FIG. 2 shows a hybrid module according to FIG. 1, in side view,

Fig. 3 einen Hybridbaustein nach Fig. 1 mit einer Abdeckung des unverkapselten HaLbLeiter-Chips, in Draufsi cht,3 shows a hybrid module according to FIG. 1 with a cover of the unencapsulated semiconductor chip, in Top view,

Fig. 4 einen Hybridbaustein nach Fig. 3, in Seitenansicht,4 shows a hybrid module according to FIG. 3, in side view,

W.Huter-1W.Huter-1

Fig. 5 einen Hybridbaustein nach Fig. 3 volkommem mit einer Schutzschicht versehen, in Draufsicht,Fig. 5 shows a hybrid module according to FIG. 3 completely with a Protective layer, in plan view,

's Fig. 6 einen Hybridbaustein nach Fig. 5, in Seitenansicht. 'S Fig. 6 is a hybrid module according to Fig. 5, in side view.

In Fig. 1 ist ein Hybridbaustein 1 dargestellt, der auf
einer Längsseite mit einer Reihe von AnschLußdrahten 2 versehen ist, von denen nur drei gezeichnet sind. Auf dem Hybridbaustein 1 ist ein unverkapseLter Halbleiter-Chip 3 montiert, der über Anschlußdrähte 4 ah Anschlußpunkte 5 in dem Hybridschaltkreis beispielsweise gebondet
ist.In Fig. 1, a hybrid module 1 is shown, which on
one long side is provided with a number of connecting wires 2, only three of which are shown. An unencapsulated semiconductor chip 3 is mounted on the hybrid module 1 and is, for example, bonded via connecting wires 4 to connection points 5 in the hybrid circuit
is.

Fig. 2 zeigt die bisher beschrjebene Anordnung in Seitenansicht. Fig. 2 shows the arrangement described so far in a side view.

In Fig. 3 ist der auf dem Hybridbaustein 1 montierte u η verkapselte Halbleiter-Chip 3 nach dem Kontaktieren mitIn FIG. 3, the u η mounted on the hybrid module 1 is encapsulated Semiconductor chip 3 after contacting with

einem flüssigen Kunststoff 6, der aus einem flüssigen Zweikomponenten-Epoxidharζ besteht, abgedeckt und zwar so, wie aus. Fig. 4 hervorgeht, daß nicht nur der, Halbleiter-Chip 3, sondern auch die Anschlußdrähte 4 und die Anschlußpunkte 5 auf dem Hybridbaustein 1 mit dem flüssi-a liquid plastic 6, which consists of a liquid two-component Epoxidharζ, covered and that so how out. Fig. 4 shows that not only the semiconductor chip 3, but also the connecting wires 4 and the Connection points 5 on the hybrid module 1 with the liquid

gen Kunststoff 6 abgedeckt sind. Der flüssige Kunststoff 6 in der auf den Hybridbaustein 1 aufgebrachten Form reagiert unter spezifischen Bedingungen aus, wobei die Temperatur und die Zeit zum Ausreagieren abhängig ist von der Zusammensetzung des verwendeten Kunststoffes 6.gen plastic 6 are covered. The liquid plastic 6 reacts in the form applied to the hybrid module 1 under specific conditions, the temperature and the time to fully react depending on the composition of the plastic used 6.

ORlGINAL INSPECTEDORlGINAL INSPECTED

W.Huter-1W.Huter-1

Anschließend wird der gesamte Hybridbaustein 1, bestehend aus der Trägerplatte , dem auf di ese r ■ mont i ert en Halbleiter-Chip 3, den Anschlußdrähten 2 und den auf dem Hybridbaustein 1 befindlichen, nicht dargestellten Verbindungs Leitungen so mit einer Schutzschicht 7 versehen, daß nur die von dem Hybridbaustein 1 wegstehenden Enden, die zur Weiterverbindung des Hybridbausteines 1 dienen, nicht mit der Schutzschicht 7 abgedeckt ist, wie dies in Fig. 5 in Draufsicht und in Fig. 6 in Seitenansicht dargestellt ist. In den Fig. 5 und 6 sind sowohl die abgedeckten Teile des Halbleiter-Chips 3, der Anschlußdrähte 4 und der Anschlußpunkte 5 als auch die mit der Schutzschicht 7 umhüllten Teile des Hybridbausteins 1 und der Anschlußdrähte 2 sichtbar und vollausgevzogen gezeichnet, um die Lage der genannten Teile in der Abdeckung 6 und in der Umhüllung bzw. der Schutzschicht 7 besser sichtbar zu machen.Subsequently, the entire hybrid module 1, consisting of the carrier plate, the semiconductor chip 3 mounted on these, the connecting wires 2 and the connecting lines (not shown) located on the hybrid module 1 are provided with a protective layer 7 in such a way that only the ends projecting away from the hybrid module 1, which are used to further connect the hybrid module 1, are not covered with the protective layer 7, as shown in FIG. 5 in a top view and in FIG. 6 in a side view. In FIGS. 5 and 6, both the covered parts of the semiconductor chip 3, the lead wires 4 and the terminal points are 5 and the coated with the protective layer 7 parts of the hybrid chip 1 and the leads 2 visible and fully v subjected drawn to the To make the position of the parts mentioned in the cover 6 and in the casing or the protective layer 7 more visible.

Die Schutzschicht 7 kann beispielsweise durch ein ein- oder mehrmaliges Eintauchen des gesamten Hybridbausteins (bis auf die von dem Hybridbaustein 1 wegstehenden Anschlußdrähte 2) in ein Wirbelsinterbad hergestellt werden, wodurch eine völlige Versiegelung des Hybridbausteines 1 erreicht wird.The protective layer 7 can, for example, by an or multiple immersion of the entire hybrid module (except for the connecting wires protruding from the hybrid module 1 2) are made in a fluidized bed sintering bath, thereby a complete sealing of the hybrid module 1 is reached.

ORIGINAL INSPECTEDORIGINAL INSPECTED

- Leerseite-- blank page-

Claims (1)

STANDARD ELEKTRIK LORENZ.
Aktiengesellschaft
Stuttga r tSTANDARD ELECTRICS LORENZ.
Corporation
Stuttgart W.Huter-1W.Huter-1 PatentanspruchClaim Verfahren zum Versiegeln von flachen Hybridbausteinen, mit einer Reihe von Anschlußdrahten auf einer Längsseite und u η gekapselten Halbleitern, die durch Bonden mit dem Hybrid-Method for sealing flat hybrid modules with a number of connecting wires on one long side and u η encapsulated Semiconductors that are bonded to the hybrid schaltkreis verbunden sind und vor dem Versiegelndes Hybridbausteins mit Kunststoff abgedeckt werden,
dadurch gekennzeichnet,are connected to the circuit and covered with plastic before the hybrid module is sealed,
characterized, daß zur Abdeckung für die ungekapseIten Halbleiter (Chips 3) ein Zweikomponenten-Epoxidharz verwendet wird und daß a η -that to cover the unencapsulated semiconductors (chips 3) a two-component epoxy resin is used and that a η - schließend der gesamte' Hybridbaustein (1) mit den abgedeckten Halbleitern (Chip 3) durch Tauchen in ein WirbeIsinterbad unter Freilassung der von dem Hybridbaustein (1) wegstehenden E-nden der Anschlußdrähte (2) vollständig versiegelt (Schicht 7) w i rd .then the entire 'hybrid module (1) with the covered Semiconductors (chip 3) by immersing them in a fluidizing bath leaving those protruding from the hybrid module (1) free The connection wires (2) are completely sealed (Layer 7) w i rd. ZT/P 1, Kre/-, Ü3.03.1983ZT / P 1, Kre / -, Ü3.03.1983 GOPYGOPY
DE3310654A 1983-03-24 1983-03-24 Process for sealing flat hybrid modules Withdrawn DE3310654A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE3310654A DE3310654A1 (en) 1983-03-24 1983-03-24 Process for sealing flat hybrid modules

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3310654A DE3310654A1 (en) 1983-03-24 1983-03-24 Process for sealing flat hybrid modules

Publications (1)

Publication Number Publication Date
DE3310654A1 true DE3310654A1 (en) 1984-09-27

Family

ID=6194474

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3310654A Withdrawn DE3310654A1 (en) 1983-03-24 1983-03-24 Process for sealing flat hybrid modules

Country Status (1)

Country Link
DE (1) DE3310654A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3415446A1 (en) * 1983-04-25 1984-10-25 Mitsubishi Denki K.K., Tokio/Tokyo MOLDED RESIN SEMICONDUCTOR DEVICE
WO1986003055A1 (en) * 1984-11-17 1986-05-22 Messerschmitt-Bölkow-Blohm Gmbh Process for encapsulating micro-electronic semi-conductor and layer-type circuits
DE10014304A1 (en) * 2000-03-23 2001-10-04 Infineon Technologies Ag Production of semiconductor component uses two stage filling step to seal contact pads

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3415446A1 (en) * 1983-04-25 1984-10-25 Mitsubishi Denki K.K., Tokio/Tokyo MOLDED RESIN SEMICONDUCTOR DEVICE
WO1986003055A1 (en) * 1984-11-17 1986-05-22 Messerschmitt-Bölkow-Blohm Gmbh Process for encapsulating micro-electronic semi-conductor and layer-type circuits
DE10014304A1 (en) * 2000-03-23 2001-10-04 Infineon Technologies Ag Production of semiconductor component uses two stage filling step to seal contact pads
US6429537B2 (en) 2000-03-23 2002-08-06 Infineon Technologies Ag Semiconductor component with method for manufacturing
DE10014304B4 (en) * 2000-03-23 2007-08-02 Infineon Technologies Ag Semiconductor component and method for its production

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