DE3307480A1 - Frequency synthesiser - Google Patents

Abstract

The patent application relates to a frequency synthesiser which can generate a multiplicity of crystal-stabilised frequencies which are a predefined distance apart from one another (channel spacing), and which synthesiser can preferably be used as a transmitter oscillator or an oscillator for heterodyne frequencies in a radio receiver. Its main application concerns its use in portable radio sets, where minimum space requirement and minimum power consumption are crucial. The frequency synthesiser is characterised by the use of a commercially available integrated circuit which contains all the essential parts of a frequency synthesiser, such as - a reference frequency oscillator - a reference frequency divider - a programmable divider - a phase comparator, where the data to control the output frequency must be entered digitally as data words, each comprising 4 bits, and in each case 8 data words must be entered in series. This could hitherto be achieved only by assigning a microprocessor, including a data multiplexer and a data memory, to perform this task. The present frequency synthesiser needs neither a microprocessor nor a data multiplexer, but merely two binary counters and a programmable semiconductor memory (EPROM). To save power, the data are retrieved from the semiconductor memory only when required. Original abstract incomplete.

Description

Fr @ quenzsynthesizer

1. Introduction The invention relates to a frequency synthesizer of any kind Design, but provided with an integrated circuit (IS) as a synthesizer controller component, which has a data bus input and, for example, 4- @ it data words as serial Control signals required.

An example is the IS MC 145146 from Motorola, the all essential components of a frequency synthesizer, namely - reference frequency oscillator -Reference frequency divider - Programmable divider - Phase comparator - Internal Contains registers and memory.

It is required to control the division ratios of the reference frequency divider and programmable divider data in the form of 8 words of 4-bit each serially must be supplied.

In regular cases this can only be achieved by the fact that this Task a microprocessor plus connected data storage plus the corresponding Input stage takes over.

This solution is space consuming and costly due to the roasting the required software.

2. It is the object of the invention to specify a frequency synthesizer. which is necessary for the synthesizer-controller-Baustain required here Provides serial data with the simplest means and the least amount of space.

3. Solution The problem is solved with the claims in dan Funds resolved.

4. Description With reference to Fig. 1, let (1) be voltage controlled Oscillator or VCO, (2) any prescaler, (3) a synthesizer controller module, which contains the following assemblies: - reference frequency oscillator - programmable Reference frequency divider - programmable divider for useful signal - phase comparator - internal registers and memories (3) also has 4 data inputs D0 to D3, which accept the 8 data words of 4 bits each, also via 3 address inputs B0 to B2, which assign the incoming data word to an internal register / memory and finally via a data acquisition pulse input (strobe).

The 8 words of 4 bits each contain all the information required are, the division ratio of the reference frequency divider and the division ratio of the programmable divider and thus the output frequency via the Rogel loop of the VOO.

The frequency synthesizer also contains a semiconductor memory (4) in the form of an EPROM, two binary counters (5) and (6) and three EXOR gates (8), (9) and (10) and finally a monoflop (7).

Two BCD switches (11) and (12) are an example of the input medium available for entering the frequency channel numbers 00 to 99.

The sequence of events is as follows; Binary counter ob (5) and (6) each have two counter inputs CP and CP, one each as a "clock" input and the other can be used as a "clock-enable" input. If CP is used as "clock-enable" is used, a "low" will make the counter ready for counting and a "high" the counter lock.

As an initial situation, it is assumed that binary counter (6) is on and has a "high" at output 03 and thus blocks the binary counter (5) via input CP.

If now - one of the two BCD coding switches (11) or (12) for the purpose Channel change activated or - by switching to "Send" a switching voltage Usend created.

so the EXOR gates (9), (10) or (8) recognize a change in level at their inputs, one input of the EXOR gate receiving the signal directly and the other input of the EXOR gate receives the signal delayed via an RC element and thus a "high" output signal for the duration of the delay # = R.C. will.

This "high" resets binary counters (5) and (6) and leaves after the falling edge both counters are ready to count.

Output O3 of the binary counter (6) is now also "low" and switches Via R1 the switching transistor (13), which supplies the memory (4) with voltage.

The reference frequency comes from the reference frequency oscillator in (3) to the input CP of the binary counter (5) and is divided by 16 up to output 03.

Binary counter (5) therefore only functions as a frequency divider, un the relatively high reference frequency to a more favorable one for the read-in process implement lower frequency.

The first "high" at output O3 of (5) also reaches the second Binary counter (6) also to the memory transfer input in (3) and let IS (3) die Take over the first four bits (word "A"), which characterize the following conditions are: Word "A" = address combination A0 to A7 of memory (4) & A8, A9, A10 from (4) & B0, B1, B2 from (3) The permanently 16 split frequency frequency reaches the binary counter (6) via the input CP and now also leaves it counting.

After the first counting cycle, output 00 is from (6) to "highn. In the club with dom simultaneous memory transfer pulse to O3 from (5) is now Word "B" read in according to the following conditions: Word "B" = address combination A0 to A7 of memory (4) / & A8 (A9, A10) of (4) & B0 & (B1, B2) of (3) The process continues analogously up to the eighth word "H": word "H" r address combination Ao bia A7 of memory (4) & A8, A9, A10 of (4) & B @, B @, B @ of (3) When this counter status is reached, a "high" appears at output 05 of the binding counter (6), blocks the switching transistor (13) and switches the memory (4).

At the same time, the "high" at input CP from binary @ counter (5) this counter is locked so that it does not receive any further input signals from (3) processed.

The status only changes again when - another channel is dialed in - switching voltage Usend is applied or - the device is switched off and on again will.

In the penultimate case, EXOR gate (8) recognizes a change in level, such as described above, creates an output impulse and initiates the next Counting process or loading process via the reset inputs of binary counters (5) and (6), whereby the additional data bit A11 at (4) creates a completely different data record "Send" is read out.

The same process happens when the send button is released, i.e. Usend collapses and EXOR gate (8) also detects a change.

Mono @ lop (7) initiates the reading process shortly after switching on the Device using the reset inputs of the binary counters (5) and (6).

In summary, there are the following advantages: - Avoidance of a Microprocessor indole. Creation of the software for generating the serial data, thus energy and cost-saving design with the smallest space requirement, - least Power consumption also because the semiconductor memory only changes in status, wio e.g. Kanaiweoheel. Switching from "Send" to "Receive" or vice versa for switched on for a few milliseconds.

A timing diagram is attached as FIG.

- L e r s e i t e -

Claims (3)

Claims 1. Frequency synthesizer of any type, but provided with a synthesizer controller component, the internal programmable reference frequency divider and contains programmable dividers for the working frequency, their division ratios can be controlled via serial input digital data (data bus) that are stored in the synthesizer controller Block can be buffered by means of internal registers / memories, d a d u r c h e k e n n n z e i c h n e t that the serial data is directly from a programmable semiconductor memory (4) are taken over, which his address command directly from suitable -BCD coding switches (11) and (12) on the one hand and the serial Read command on the other hand from an arrangement of binary counters (5), (6) receives the only trigger a read-in cycle if necessary. 2. Frequency synthesizer according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the power supply of the Semiconductor memory (4) switched on by means of holding transistor (13) and after completion of the read-in process8 is switched off again by means of the switching transistor (13). 3. Frequency synthesizer according to claim 1, d a d u r c h g e k e n n notices that EXOR gates (8), (9) and (10) for every possible change the address combination on the semiconductor memory (4) trigger a new read-in process.