DE3303762A1 - STORAGE - Google Patents

Description

Description memory

The present invention relates to a memory with several in a common semiconductor body formed storage cells, each of which has a charge storage device with one attached to it has coupled first electrode and a transistor connected to the charge storage device, which controls the flow of charge in and out of the charge storage device, the transistor has a localized first region of a first conductivity type and a gate electrode overlying a second Zone of an opposite conduction type lies.

MOS memories are designed as read / write memories (MOS-RAMs) with ever larger storage capacity. 64K memory is already being used in reasonable quantities, and limited quantities of 256K memories are made. the US Pat. No. 4,112,575 shows a memory with memory cells using single-level conductors, each with an N-channel MOS transistor contain separate drain and source zones and a capacitor connected to the source. There are

also described memories in which double-level ladder, i. i.e., two-level ladder, in Memory cells are used, each with a single drain / source zone and one of these through the channel of the transistor contain separate capacitor. The terms "single level" and "double level" (English: single level or dual level) characterize such arrangements in which the ladder is made at the same time a common conductor layer can be etched or such arrangements in which conductors independently from different Conductor layers are made, usually at different "levels" or in different distances with respect to the semiconductor substrate. The single level ladder storage cell is limited in size by the required minimum spacing between adjacent conductors. the Double-level ladder memory cell may have a smaller structure than the single-level ladder memory cell. In order to ensure the correct operation of the double conductor embodiment, it is desirable to extending the substrate portion of the capacitor so that it extends over the top plate of the capacitor extends and is partially covered by the gate electrode. This means an additional and undesirable capacitive loading of the gate, the changes in the charge stored in the capacitor (the logical

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Information) can cause if the potential of the gate (the word line) to access the memory cell is changed.

It is desirable to be a single transistor capacitor MOS memory cell to have available that is more compact than single-conductor single-transistor capacitor storage cells, and which has lower gate load capacitance and less memory charge losses than the single transistor capacitor memory cell with double conductors.

The invention takes this problem into account in a memory of the type mentioned above in that the transistor a third localized semiconductor zone of the first conductivity type, which is arranged in such a way is that the second semiconductor zone separates the first and the third semiconductor zone that the first electrode Part of a conductor lying on a first level is that the gate electrode is part of a conductor on a second Level conductor, and that the conductors lying on the first and on the second level are independent are formed and have different distances from the semiconductor body. .

In the following, exemplary embodiments of the invention are explained in more detail with reference to the drawing. Show it:

Figure 1 is a schematic sketch of a. Array of memory cells,

FIG. 2 shows a plan view of an embodiment of memory cells according to the invention corresponding to the basic circuit diagram of the memory cells shown in FIG. 1,

FIG. 3 shows a first cross-sectional view of the memory cells according to FIG. 2, and

FIG. 4 shows a second cross-sectional view of the memory cells according to FIG. 2.

The present invention is directed to a semiconductor memory cell and to fields of such cells with a semiconductor body on which a first insulating layer is formed and having a first conductor on a portion of the first insulating layer. The combination The semiconductor body / insulating layer / conductor forms a charge storage device. A control device connected to the charge storage device controls the flow of charge into and out of the charge storage device. The control device has a localized first and a localized second input / output semiconductor zone, separated from each other by sections

the mass of the semiconductor body are separated; the control device also has a second (Control) conductor which, in response to the control signals supplied to it, controls the flow of charge through the control device controls. The first and second conductors are separated from each other essentially by the second input / Output zone separated and connected to a ladder on a first or a second level. The conductors lying on the first level and those on the second level have different conductors than the semiconductor body Distances.

In a preferred embodiment, the memory cell has an epitaxial layer over a semiconductor substrate on, wherein the control device is an N-channel insulated gate field effect transistor, the separate Has drain and source zones. On the electrode plate of the capacitor is a on a first level lying polysilicon conductor connected. There are separate sections on the gate electrode and the drain zone second level polysilicon conductors connected. The source zone can be as small as it is possible in the context of reasonable manufacturing, because the distance between the polysilicon connection located on the first level and the gate electrode and the second level polysilicon connection to the capacitor electrode typically

is smaller than a source zone of minimal size. This reduces the dimensions of the memory cell and thereby those of the memory cell arrays and the PIAMs in which the arrays are used.

FIG. 1 shows an NxM field 10 with rows and columns of substantially identical memory cells 12. Each cell contains a MOS transistor 14 with a source connection 16, a drain terminal 18 and a gate terminal 20, and one coupled to the drain terminal 18 equivalent capacitor comprising a first capacitor 22a and a second capacitor 22b. In a preferred embodiment, the Field 10 made on a semiconductor substrate. The first electrodes of the capacitors 22a and 22b are coupled to terminal 18. The second electrode of FIG. 22a is coupled to the semiconductor substrate, which is typically held at a potential VSub. The second electrode of 22b is at potential Vx connected. The gate terminals 20 of the transistors of a given row of transistors 14 are connected to one common N word lines WLO, WL1 ... WLN connected. The source connections 16 of the transistors of a given column of transistors 14 are connected to a common line of M bit lines BLO, BL1 ... BLM connected. To the word and / or bit lines

are not shown here addressing refresh and read circuits connected to the memory cells 12 and to be able to read the information stored in them. The way a Memory cell 12 in such a field is inherent known and should therefore not be explained in more detail here. .

The designation of the connection 16 as source and the connection 18 as drain is correct if from the terminal 16 positive current flows through the transistor 14 and from the terminal 18 ^ If reversed of this current is · the terminal 18. the source, while terminal 16 is the drain. The terms can therefore be used interchangeably.

FIGS. 2, 3 and 4 show the structure of an embodiment of a section from that shown in FIG Memory field 10. The section contains a memory cell 12 which is connected to word line WL1 and the bit line BL1 is connected. Figure 2 shows a transparent view from above; Figure 3 shows a first cross-sectional view along the dashed line A-A in FIG. 2; and Figure 4 shows a second Cross-sectional view taken along dashed line B-B in Figure 2. For illustrative purposes, the various doped zones in Figures 2, 3 and

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formed in accordance with N-channel memory cells 12. Another type of dopant could be used, to create a P-channel memory cell. Changes these zones can be created by ion implantation and / or diffusion and / or a combination of these both techniques can be made.

In a preferred embodiment, the memory cell array 10 is made by using a p-type Epitaxial layer 26 having a major surface 28 is formed over a (p +) conductive substrate 30. The substrate 30 would be less heavily doped if an epitaxial layer were not used. That Memory array 10 is basically formed in epitaxial layer 26. The epitaxial layer 26 could can be omitted in order to form the memory array 10 directly in the substrate 30. Field oxide 32 and one Channel stop zones 34 serve as a boundary for each storage cell 12. A portion of a storage zone 36 is in contact with a portion of the field oxide 32 and the channel stopper zone 34. The zone 36 has an upper portion 36a and a lower portion 36b. The portion 36a of the zone 36 is typically ion-implanted with a donor dopant (n-line) and is relatively close to the

Surface 28. Section 36b of zone 36 becomes typically implanted with acceptor dopant (p-line) and is essentially below the Section 36a. Each zone 36b of a memory cell 12 has a relatively low-resistance connection to all other zones 36b of all memory cells 12 of the memory field 10. The Zono ^ 36b of all memory cells 12 of the memory field 10 are also electrically connected to one another via the p-type epitaxial layer 26 and the (p +) - conductive substrate 30 connected. Zone 36 is part of that shown in FIG Capacitor 22a; the zone 36 represents a plate of the capacitor, with the substrate 30 the other plate represents. A section of a first level conductor (Poly I) contacted an electrode (conductor) 52 extending from the storage area 36 through a dielectric Layer 54 (this is typically made of silicon dioxide) is separated. The electrode 52 provides a Plate of the capacitor 22b, while the zone 36a is the other plate of this capacitor. the Zone 36a makes contact with an (n +) - conductive source zone

The transistor 14 shown in Figure 1 is formed by an (n +) - conductive drain zone 40, an (n +) - conductive Source zone 38 and a gate electrode 46.

The (n +) -conducting drain zone 40 is separated from the source zone 38 by portions 42 of the ground of the epitaxial layer 26. These portions 42 of layer 26 are selectively inverted to form a channel that electrically connects drain region 40 to the source region. In a preferred embodiment, ions are implanted into the sections 42 of the epitaxial layer 26 in order to adjust the threshold voltage of the MOS transistor. A gate insulating layer 44 overlies portions of surface 28. A gate electrode (conductor) 46 overlies that portion of gate oxide region 44 that overlies portions 42 of epitaxial layer 26 and is on a portion of a second level conductor (Poly II) attached. A drain electrode (a conductor) 48 contacts the surface 28 such as an (n +) conductive zone 50 which is physically and electrically connected to the drain zone 40. The drain electrode 48 is connected to a portion of the second level conductor (poly II). The zone 50 is followed by an (n +) - conductive drain zone 50a, which is in electrical contact with the zone 50. The zone 50a is the drain of an adjacent transistor of a further memory cell, which is also connected to the bit line BL1.

The electrodes 46 and 48 are typically grounded by ion implantation and subsequent heat treatment separate sections of an undoped polysilicon layer are formed around these sections to make ladders. The oxide layer 44 prevents portions 42 of the epitaxial layer 26 from being doped when the implanted polysilicon of zone 46 is heat treated. There under the electrode 48 does not have such an oxide layer, some of them get into the electrode 48 ions implanted into the epitaxial layer 26 during the heat treatment and form the (n +) ~ conductive zone 50,

One typically made of phosphor glass (P-glass) dielectric layer 60 covers exposed portions of surface 28, dielectric layers, electrical conductors and / or electrodes. A passivation layer typically made of silicon nitride 62 covers layer 60.

The cross-sectional view shown in Figure 4 shows the semiconductor body and all semiconductor layers, dielectric layers, conductor layers made of polysilicon, metallic layers and passivation

layers of the storage field 10. Starting from the top, In the structure shown, passivation layer 62 (typically silicon nitride) is over a metallic level layer WL1, which typically consists of aluminum. This in turn lies over a dielectric layer 60 (made of P-glass), which in turn is over one on top of a second Level polysilicon conductor layer (poly II to form the conductors (electrodes) 46 and 48 in Fig. 3). The poly II overlies a dielectric (second gate oxide) layer 58 (part of this forms the layer 44 shown in FIG. 3, which in turn is above a second, on an intermediate level located dielectric layer 56 is. Layer 56 overlies a first polysilicon conductor layer (Poly I is used to form the conductor (the electrode) 52 according to FIG. 3), which over a dielectric (first gate oxide) layer 64 (a part of which forms that shown in FIG. 3) Layer 54). Layer 64 overlies a dielectric (field oxide) layer 32, which in turn overlying a (p +) conductive channel stop region 34 overlying a portion of the top of the epitaxial layer 26 is formed overlying the (p +) - conductive semiconductor substrate 30.

FIG. 2 shows a transparent top view of a section of the field 10. The zones 50, 50a, 40, 42, 38 and 36 all form a section the surface 28 (see Fig. 3). WL1 extends down and contacts a portion of the conductor (electrode) 46. The electrode 52 of FIG Figure 3 is connected to the conductor (poly I) located on a first level, that of the surface 28 is separated by portions of dielectric layers 54 and 32.

As mentioned above, the electrode is on the conductor located on the second level (Poly II), while the electrode 52 is connected to the conductor located on the first level (Poly I) is connected. This makes it possible to produce the source zone 38 with a significantly smaller area than it would be possible if the adjacent gate and capacitor electrodes were both on first Level ladder would be. This is because most of the semiconductor design rules for the smallest possible distance between adjacent conductors of the same level a larger one Provide value as required for the smallest possible source zone 38. So the area size becomes of the memory cell 12 and thereby also the area of the entire memory field 10 is reduced. Be specific on different

Levels of ladder independently of one another at different times, and not at the same time manufactured. The level including conductor 46 is established when conductor 52 is masked. The gap between conductors 46 and 52 can be made extremely small without the risk of contact consists. It can be much smaller than a gap created by etching a single conductor will. The conductors 46 and 52 are then used as a mask during the implantation of the zone 38, the small gap defining a small-area zone 38.

In some memory arrays that have double level conductors (see US Pat. No. 4,112,575), the (p +) - is conductive Channel stopper zone from the two zones implanted in the substrate under the capacitor field plate separated. A problem associated with such a structure is that the memory cell will hit Alpha particles (radiation) to a build-up of positive charge in the (p +) - conductive zones (like zone 36b) due to the accumulation of holes, resulting in a downsizing the p + / p- barrier height (zone 36b / epitaxial layer 26) leads to a reduction in the Storage cell allowed stored positive charge.

This means a loss of stored logical information and sets the limit values for operation. The interconnection of all-1icher Zones J56b through heavily doped (relatively low-resistance) channel stopper zones 34 reduce the average build-up of positive charge within zone 36b of each memory cell 12 and reduced thus the loss of stored information. This results in memory fields 10 relating to Alpha particles are less sensitive. This sets the general interference limits for the operation is improved and the area requirement for the storage field is reduced, since the storage capacitors can be made smaller than in those components in which the zones 36b do not have low-resistance paths are interconnected.

Using the memory field shown in FIG. 1 and memory cells with the basic structure shown in FIGS. 2, 3 and 4, a 64K N-channel RAM was constructed. The memory turned out to be functional. The size of a memory cell was 25 × 9.5 μm . The use of only single level conductors would have increased the size of the memory cell by ² to 27 × 9.5. So there is an 8 % ± ge saving of the memory cell area,

without having to accept a significant loss of performance or a worsening of the interference limits. The memory cells occupy about 60 % of the area of the entire RAM. As a result, there is an area reduction of about 4.8 % in terms of the entire chip size of the RAM. In the fabricated embodiment of the 64K RAM, the transistors were formed using a self-alignment process, the (p +) conductive substrate was 250 µm thick and had an impurity concentration of 10 impurities / cm. The self-alignment process mentioned leads to essentially fixed channel lengths in the transistors and therefore contributes to a reduction in response time fluctuations. The p-type epitaxial layer is 10 µm thick and has an impurity concentration of

2 × 10 imperfections / cm. The (n +) - conductive source zone is 3 / in wide, 2 μm long and 0.5 μm thick, and

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it has an impurity concentration of 2 impurities / cm. The (n +) - conductive drain zone is

3 µm wide, 4 µm long and 0.5 µm thick and possesses

20 a dopant concentration of 2 × 10 defects / cm. The upper portion (36a) of the capacitor of the epitaxial layer has a thickness of 0.5 _/ ura, while the lower portion (36b) has a thickness of 1.0 to has.

The surface area of the epitaxial layer of the zone 36 is 151.5> un, the dopant concentration of the (n +) - conductive zone 36a is 2 χ impurities / cm ^, and the dopant concentration of the (p +) - conductive zone 36b is 3 χ 10 impurities / cm . The channel zone 42 is 3 .um wide. The gate dielectric 44 is silicon dioxide having a thickness of 0.05 p and a width of 2 to. The dielectric layer 54 is silicon dioxide 0.04 µm thick. The electrode conductors 46, 48 and 52 are all made of polysilicon. The dielectric layer 32 is made of silicon dioxide with a thickness of 1.0 µm. The inter-level dielectric layer 56 is made of silicon dioxide and is 0.30 µm thick. The dielectric layer 60 is made of P-glass and is 1.0 µm thick. The word lines are made of 1.0 µm thick aluminum. The passivation layer 62 consists of 1.0 µm thick silicon nitride.

Of course, the embodiment described above can still be used within the scope of the invention be modified. For example, the N-channel MOS transistor could be replaced by a P-channel MOS transistor with an insulated gate

Insulated gate, an N- or P-channel junction field effect transistor, an NPN or PNP bipolar transistor, a gate-controlled diode switch
or various other components. With a slight change in the layout, the polysilicon conductors could be replaced by metallic conductors or other conductors. In addition, the gate electrode could be connected to a first level conductor and the top capacitor electrode could be connected to a second level conductor. Furthermore, the source, gate and upper capacitor electrodes could be connected to conductors located on the first, second or first level or to conductors located on the second, first or second level.

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Claims (8)

BLUMBACH · WESER ^ BERGEN- KRAMER ZWIRNER '. HOFFMANN PATENT LAWYERS IN MUNICH AND WIESBADEN Patentconsult Radeckestrasse 43 8000 Munich 60 Tc ¹ -'sr, (08?) 883603/883604 Telex 05-212313 Telegromrne Patonlconsuli Palentconsult Sonnenberger Strasse 43 6200 Wiesbaden Telelon (06121) 562943/561998 Telex 04-186237 Telegrams WESTERIi ELECTRIC COMPANY CHENEY 7 Incorporated New York N. Y. Claims ( Iw memory, with a plurality of memory cells (12) formed in a common semiconductor body (30, 26), each of which has a charge storage device (22a, 22b) with a first electrode (52) coupled to it and a transistor (14 , 40, 42, 46) which controls the flow of charge in and out of the charge storage device, the transistor having a localized first region (40) of a first conductivity type and a gate electrode (46) over a second region of an opposite Line type, Munich: R. Kramor Dipl.-Ing. . W. Weser Dipl.-Phys. Dt roi. nat. · E. llodmann Dipl.-Ing Wiesbaden: P.G. Blumbach Dipl.-Ing. · P. Bergen Pro ».Dr. jur.Dipl.-Ing, ΙόΙ.-Λϊ, i <-Anw. until 1979 · G. Zwirncr Dipl.-Ing. Oipi.-W.-lng. characterized, that the transistor has a third localized semiconductor zone (38) of the first conductivity type, which is arranged such that the second semiconductor zone, the first and the third semiconductor zone separates that the first electrode is part of a conductor (52) lying on a first level, that the gate electrode is part of a conductor (46) lying on a second level, and that the on the first and second level conductors are formed independently and different Have distances from the semiconductor body. 2. Memory according to claim 1,
characterized, that sections (36b) of the semiconductor body below the second conductor with a suitable dopant are doped that the capacity of the charge storage device is increased. 3. Memory according to claim 1,
characterized, that a third conductor (48) to the first zone and to a section separated from the second conductor of the conductor (46) lying on the second level is connected. 4. Memory according to claim 3,
characterized by it . _t that the first, second, and third conductors, as well as those on the first and those on the second Level conductors are all made of polysilicon. 5. Memory according to claim 4,
characterized, that the transistor is an N-channel field effect transistor with insulated gate is. 6. Memory according to claim 4,
characterized, that the conductor lying on the first level is removed from the semiconductor body by a first insulator (54) that the conductor lying on the second level is separated from the semiconductor body by a second Insulator (44) is separated, and that the conductors lying on the first and on the second level through a third isolator (60) are separated from each other. 7 «memory according to claim 6,
characterized, that the located first zone is an input / output zone (40). lo / ll 8. Memory according to claim 7, characterized in that the charge storage device has a localized third and a localized fourth zone (36a, 36b) of opposite conductivity type in the semiconductor body having.