DE3246607A1 - Method for generating a serial digital data signal - Google Patents

Abstract

In a method for generating a serial digital data signal (D') from signal states existing in parallel, no conventional parallel/serial converters need to be used and the serial data signal (D') formed can be rapidly changed by storing the signal states in addressed storage spaces of a data memory (14) and calling up the signal states from the storage spaces with the aid of addresses generated clock pulse by clock pulse from the data memory. <IMAGE>

Description

"Procedure for creating a serial digital data signal"

The invention relates to a method for creating a serial digital data signal from signal states that exist in parallel.

To create a serial digital data signal from existing parallel Signal states that are logically "1" or logically O "are usually parallel-to-serial converters used.

These essentially consist of shift registers into which the parallel Signal states are entered, and then at the output by clocks of a clock signal the parallel input signal according to the linear sequence of the memory locations pending one after the other. The disadvantage of this parallel-to-serial converter is there in that a high cost of components is required and beyond that the terminals already rigidly define the sequence of the serial data signal, so that changes required quickly are not easily possible.

In contrast, the invention is based on the object of a method to create a serial digital data signal from existing parallel Specify signal states that require little component effort is and that too the data signal that is created can be influenced quickly and easily, d. H.

can be changed.

This object is achieved according to the invention in that the signal states are stored in addressed memory locations of a data memory and that the signal states from the memory locations with the help of clock-generated addresses can be retrieved from the data store.

Since the signal states are stored in addressed memory locations the order can be changed by changing the contents of the memory of the signal states and thus a change in the serial data signal.

This change can be within one pulse interval of the clock signal take place, so that a serial data signal at the output of the data memory uninterrupted be available.

In a preferred embodiment, those produced by the meter arrive Addresses via a multiplex circuit to the data memory, whereby on separate Inputs of the multiplex circuit can be given other addresses with Can be selected using a dialing signal and sent to the data memory. This makes it easy to switch between read and write operation of the Realize memory, with either the addresses produced by the counter for reading the serial signals stored in the memory can be used or with the help of Signal states stored in the memory from externally supplied addresses changed can be changed, whereby the serial data signal read from the counter is changed will.

The method according to the invention can preferably be used in one system use where a serial input data signal according to a specific program should be changed and output again serially. For changing the data signal must this vorr in the form of parallel existing signal states lie. The signal states that exist in parallel are therefore preferably eliminated a serial data signal generated by the serial data signal on a Processor stage is directed that the processor stage is controlled with the clock signal is, and that the processor stage the current signal state of the serial data signal Abt by the clock signal protrudes and an assignment of the clock signal number within makes the specified number of clock pulses for the current signal state. The assignment of current signal states made in the processor stage a specific clock pulse can be transferred to the memory without further ado will.

The number of the specific clock pulse can therefore be identical to the Be the address of the memory location in the memory.

As both in the decomposition of the serial data signal and in its formation by the method according to the invention uses the same clock signals there is no synchronization problem as there is in conventional use of series-parallel converters for the formation of the parallel existing signal states and parallel-to-serial converters for merging the serial data signal occur after processing.

The decomposition of a serial signal into this existing parallel Signal states with the help of a processor stage, for which a commercially available Microprocessor is suitable, takes place in an extremely simple manner in that the Processor stage at the rate of the clock pulses, which synchronizes with the data signals are switched so that each bit of the data signal from the processor stage recognized and a specific number, namely the number of the relevant clock pulse within the data word. This way the serial signal can processed immediately within the processor stage without a series-parallel conversion with a conventional one Series-to-parallel converters can be made got to.

The clock signal preferably arrives at an interrupt input the processor level and thus takes the assignment of the clock signal number to the current one Signal state before. For the method according to the invention, the usual interrupt input, which is actually intended for program interruptions, is advantageously used for purposes other than those intended in order to acquire the serial data signal clockwise and the assignment to the corresponding measure number.

The serial data signal is also at the output when it changes of the data memory available uninterruptedly when.

the change of the memory contents in the time interval between two addresses generated cyclically.

A particularly suitable field of application for the present invention is an electronic organ, in which the tone selection with the help of the keys is parallel via key switches and shift registers serving as parallel-to-serial converters encoded a serial data signal and fed to a tone generator which produces or switches through the required tones according to the pressed key. In such an electronic organ, it is desirable according to by the keys selected tones a suitable change or addition of the tones to make, for example for an automatic accompaniment, for the expressed Root notes, chords or tone sequences are created. Such changes can be made in a microprocessor, which is programmed accordingly, easily made will. With the method according to the invention, it is possible to make these changes without make previous series-parallel conversions. It is also possible to change the Signal in a simple manner with the help of the counter back to a serial data signal put together, which in the generator for the purpose of generation or

Release of the required tones can be processed.

In an alternative embodiment, the memory content can be changed with the help of a microprocessor even without an interposed multiplex circuit make. To do this, it is only necessary to wait until the counter has the address of a the signal state to be changed. This is done immediately by the microprocessor the restoring in the memory made by this briefly from read is switched to "write" and the signal state pending at the data input is written to the address concerned.

Then the microprocessor immediately switches back to "read", see above that the read out serial data signal already contains the changed signal state. It is essential for this that the re-storage, i.e. the writing of the new signal state, is made in a relatively short time compared to the writing time. The advantage of this Modification procedure is that no multiplex circuit is required, so that the circuit complexity is reduced.

The invention is illustrated below with reference to one shown in the drawing Exemplary embodiment will be explained in more detail. The figures show: FIG. 1 a basic circuit diagram an electronic organ to which the method according to the invention is applied; finds FIG. 2 shows a pulse diagram to illustrate the structure of the serial signals FIG. 3 shows the basic structure of the serial output from FIG. 1, FIG. 4 a modified circuit for serial output with four input signals Combined simultaneously with the same program to form four serial output data signals will.

Figure 5 shows an alternative embodiment of the basic structure the serial output from Figure 1 In Figure 1, keys 1 are an electronic Organ indicated.

By pressing the keys, key switches are assigned to keys 1 2 operated, with the help of which on the inputs 3 of parallel-to-serial converters 4 a Ground potential is applied when the associated key 1 has been pressed. These The change in potential is stored in the parallel-series converters 4.

The parallel-to-serial converters 4 are designed as shift registers, are routed to the clock signals T1 and T2. The Signal states generated by the key switch 2 in the parallel-to-series converters 4 read out at output 5 and compiled into a serial data signal D.

This serial data signal D is applied to the input of a microprocessor 6, to which the same clock signals T1 and T2 are fed. The clock signal T1 becomes on the interrupt input of the micro-processor 6, whereby this is stopped and the current signal state of the serial data signal D registered at its input and assigned to a clock pulse number. How it works of the microprocessor 6 is illustrated with reference to FIG.

Duration the length of one The clock signal T1 consists of 65 clock pulses, form their / data word. The beginning of each data word is through a takeover cycle T2 marked. The serial data signal D is activated by pressing the corresponding Keys 1 of the keyboard created.

In the embodiment shown in Figure 2, for example the first and fifth keys have been pressed, so that the first and fifth Clock pulse a digital signal '1 "connects, while the remaining clock pulses are digital '0'.

The microprocessor 6 is programmed, for example, so that it off the serial data signal D should make the serial data signal D ', the opposite the input data signal D is changed, in the illustrated embodiment in that instead of the fifth clock pulse, the fourth clock pulse with an "1" signal and in addition the eighth clock pulse is moved with a "1" signal. From the pressed A modified triad has thus been formed.

This function can be exercised by the microprocessor 6 that his Interrupt input the clock signal T1 is fed. The microprocessor 6 recognizes thereby1 which signal state of the serial data signal D at the associated clock pulse with the pulse number 1 to 65 is present at its input. That way, realizes the microprocessor reads the content of the serial data signal D without this being a Series-parallel conversion would be required. After processing that in the micro-processor 6 serial data signal D decomposed into its signal state into a decomposed data signal D 'according to the programming of the micro-processor 6 becomes the decomposed data signal passed into a serial output unit 7. In the serial output unit 7th the individual signal states are combined to form a serial data signal D ', that a generator 8 of.

Organ is fed. In the generator 8 are those in the organ required tones are continuously available and are accordingly dme serial Data signal D 'switched through to a sound shaping stage 9. Part of the tone generator is a clock generator that generates the clock signals T1 and T2. The tone generator 8 consists essentially of divider chains in which the corresponding Tones divided down from twelve tones of the highest octave fed to the generator will. The notes of the highest octave (c sharp5 ... c6) are used in a top octave synthesizer 10 generated by frequency division from a very high frequency generator frequency.

The tones released from the generator 8 are in a tone shaping stage 9 and fed to an output amplifier 10, which has a loudspeaker 11 controls through which the tones can be heard.

The serial output unit 7 is shown in more detail in FIG.

It consists of a counter 12 to which the clock signal T1 is fed and the corresponding to the clock signal a coordinated output signal on, for example six output lines A to F are generated. The takeover clock T2 serves as a reset signal for the counter 12. The output signal of the counter is passed through a multiplex circuit 13 to the six inputs AO to A5 of a memory in which the individual signal states are stored.

Changing the individual signal states that make up the serial data signal D 'is determined by switching a selection signal Sel to the memory 14 and at the multiplex circuit. The multiplexer 13 has six inputs A0 to A5 via which the addressing can be entered for reading into the multiplexer. At the Appearance of the selection signal Sel is not the address generated by the counter 12, but the address of the - address signal present at inputs A1 to Å6 on the exits Q1 to Q6 of the multiplex circuit 13 passed. The compilation of the stored in the memory is now in a corresponding manner serial data output signal 8 D 'changed by adding to the one corresponding to the address The storage space of the signals corresponds to that at the input DO of the memory 14 pending data signal is changed. This change happens between two clock pulses for the counter 12, so that the reading from the memory 14 with the help of the counter 12 is not disturbed by the change and is therefore continuous at the output of memory 14 a serial data signal D 'is present.

In contrast to FIG. 3, FIG. 4 only shows that the controlled by the counter 12 and the multiplexer 13 output for several serial Data signals can be done simultaneously with the same program. Figure 4 shows the Output of four data signals DO'to D3 '.

Figure 5 shows an alternative embodiment to Figure 3, in the multiplex circuit that is used to change the data stored in the data memory 14 Signal has been omitted. The change of the stored in the memory 14 Data signal is possible in this embodiment in that the change microprocessor initiating the data memory 14 when calling up the appropriate address switches over by the counter 12 from "read" to "write" for a short period of time. The signal on data input D0 is transferred to the called address space enrolled. Then the data memory 14 is switched back to "read", whereby switching from "read" to "write" and back in a relative to Clock time of the counter 12 has been made very short-term. After switching back of the data memory 14 to "read" by the microprocessor is therefore by the counter 12 the unchanged address is still called. The data memory 14 writes consequently under the called address already the changed Signal state. With this method there is therefore no need to use the multiplex circuit 13 from Figure 3.

L e r s e i t e

Claims (7)

Claims: Method for creating a serial digital Data signal (D ') from signal states that exist in parallel, d a d u r c h g e it is not possible to state that the signal states are in the addressed memory locations a data memory (14) are stored and that the signal states from the Storage locations with the help of clock-generated addresses from the data memory can be accessed. 2. The method according to claim 1, characterized in that the storing the signal states with the aid of an address clocked with a clock signal (T1, T2) for the data memory (14) generating, counter (12> takes place. 3. The method according to claim 2, characterized in that the from Counter (12) produced addresses via a multiplex circuit (13) on the data memory (14) arrive that other addresses are given to the multiplex circuit (13) can be selected with the help of a selection signal (Sel) and transferred to the data memory (14) to change the memory contents. 4. The method according to claim 3, characterized in that the change of the memory content in the time interval between two addresses generated cyclically. 5. The method according to any one of claims 1 to 4, characterized in that that the parallel existing switching states from a serial digital data signal (D) have been generated in that the serial data signal (D) is sent to a processor stage (6) is directed that the processor stage (6) is controlled with the clock signal (T1, T2) and that the processor stage (6) the current signal state of the serial data signal (D) controlled by the clock signal (T1, T2) queries and an assignment of the clock signal number (1 ... "65) within the specified number of clock pulses (T1) for the current one Signal state. 6. The method according to claim 5, characterized in that the clock signal (T1) is routed to an interrupt input of the processor stage (6) and thus assigns the clock signal number ("1" ... "65") to the current signal status. 7. The method according to claim 1, characterized in that the change of the stored signal, it is waited until the correct address is retrieved and that the restoring takes place within a short time relative to the readout time is made.