DE3238227A1 - Input and output processor for a telecommunication system - Google Patents

Abstract

To relieve the main processor of a processing unit, the data transfers between it and its environment (peripherals, communication network) are exclusively carried out via input and output processors. The CPU used for this is a commercially available I/O processor 5 which, although it is designed for fast data transfer, must, as coprocessor ("slave"), be usually controlled by a higher-level "master" processor. This large hardware expenditure is avoided by a starting circuit 7 which supplies the hardware signals SEL, CA required for initialisation. During the initialisation, the coprocessor reads the required program blocks out of a nonaddressable memory (ROM) and the system then switches to a RAM memory for normal operation. Application for controlling telecommunication systems, for example videotex computer centres, teleaction and office communication systems. <IMAGE>

Description

Input and output computer for a telecommunications system

The invention relates to an input and output computer for a telecommunications system, in which messages are exchanged between different processing units.

Multi-computer systems are increasingly used in telecommunications for control purposes used. Examples are the partially central level of screen text centers (see e.g.

DE-OS 29 14 665), the node computers in telecontrol technology and office communication systems called. So-called coprocessors are known which act as input and output processors trained and able to transfer large amounts of data quickly (e.g. Intel 8089 processor). But you are dependent and need a so-called The host or master processor that controls them. In particular, the host processor must initialize the coprocessor, i.e.

an initial entry or "bootstrap" must be performed before the coprocessor is able to start operating. For use a coprocessor as input and output computer is therefore a high Circuit effort necessary. This is especially true when there is a loose coupling between the various Processing units of a multi-computer system is desired to the effect limit of individual errors.

The invention is based on the object of an independently working To create high-performance input and output computers.

According to the invention, this object is achieved with an input and output computer of the type mentioned in that it has one for the dependent Sending and receiving messages trained coprocessor, which is responsible for the Signals required for initialization are supplied by a start circuit, a test value memory connected to the coprocessor only during initialization and a switching device, which then accesses the read / write memory is switched.

Advantageous further developments of the invention are set out in the subclaims marked.

An embodiment of the invention is described below with reference to the Drawing explained. The figures show: FIG. 1 a telecommunication system in which several Input and output computers are used, in a schematic representation; figure 2 shows a part of an input and output computer according to the invention, as a block diagram shown; FIG. 3 the remaining part of the input and output computer according to the invention according to Figure 2, shown as a block diagram; Figure 4 the software concept of the and output computer according to Figures 2 and 3; Figure 5 shows a starting circuit of the and output computer according to Figures 2 and 3; Figure 6 shows the time course of various signals occurring in the starting circuit according to FIG. 5; FIG. 7 shows a memory switchover of the input and output computer according to the invention, and FIG. 8 details of the start circuit according to Figure 5.

The telecommunication system shown in FIG. 1 contains several loose ones Main computer HR coupled to one another, which preferably consist of microcomputers, and which are used to control a periphery 2, which are only shown schematically in the drawing is indicated. This periphery can e.g.

Terminal devices, mass storage devices, transducers, external networks such as contain data networks, etc. Measurement signals coming from the periphery are used evaluated and output control signals to them. The telecommunications system 1 can also be used advantageously in telecontrol technology.

If a telecommunications system, as shown in Figure 1, contains several main computers HR, these are interconnected by an interprocessor communication network IKN tied together. This network IKN can contain a circuit switch, or but have a multiple port memory.

To relieve the main HR of input and output activities, input and output computers I / O-R are used as a communication element between serve the respective main computer HR and its environment, e.g. the interprocessor communication network IKN or the periphery 2. An HR main computer therefore has no direct connection to its environment, all data transmission goes through an input and output computer. Form a main computer with one or two assigned input and output computers a processing unit VE.

The input and output computer I / O-R contains as CPU, i.e.

as a central computing and control unit (Fig. 2), a commercially available one Coprocessor 5 - also known as a slave processor - e.g. the Intel type 8089. The coprocessor 5 receives the required clock of 5 MHz from a clock generator 6th

A starting circuit 7, which will be explained in detail further below is, provides the coprocessor 5 with the preparation of the company required signals. A decoding circuit 8, as can be seen from the drawing with other parts of the input and output computer, including the coprocessor 5, is connected, provides the input signals for the start circuit 7.

In order to be able to use slow memory modules, there is a wait state generator 9 is provided, with which the operating speed of the CPU can be increased by inserting up to can be adapted to the access time of the memory modules to three waiting cycles A first timer 11 has freely programmable delay times from 6.5 to 426 Ms on, a second timer 12 from 6.5 ps to 58 years. A USART module 13 with a downstream line driver and receiver 14 represents a serial interface for connecting a maintenance device, e.g. a TTY telex.

The individual modules of the input and output computer are separated by a internal bus 15 connected to each other. A bus controller 17 sets the status signals the CPU 5 into control signals for the input and output computer I / O-R. The input program is in one or two EPROM modules 18, i.e. erasable and programmable permanent memories, filed. The circuit components of the input and output computer are also connected to one another by the signal lines shown in the drawing.

A local bus 16 contains drivers 20 (Figure 2) and 21 (Figure 3). It is used to connect the modules of the input / output computer to one another. It is 96-pin.

The input and output computer is connected via a communication bus 24 intermediate drivers 22 connected to the associated main computer. A message memory 25, which is designed as an 8-kbyte RAM module, is used the exchange of messages between the input and output computer and the main computer. It is monitored by an access control circuit 26 and both the input and output computer via the local bus 16 as well as the main computer HR access via communication bus 24.

A first signaling register 28 and a second signaling register 29 are used for the rapid exchange of signals between the input and output computer and the main computer. The transfer of blocks of data or messages between them takes place by exchanging signaling bits in the handshaking process, whereby the Data blocks or messages written in the message memory 25 and from be read out from him.

A RAM module 30 serves as local memory for the input and output computers. A so-called shadow ROM memory 31 covers about half of the memory area of the RAM memory 30 (2: 4 kByte). The shadow ROM memory is used during initialization read out, during operation it is switched off and takes its place the RAM memory 30.

A control circuit 32 connected to the local bus 16 is used either to control the connected peripheral devices 2 or they is designed as an interface circuit to the network IKN.

The coprocessor 5 has two processing channels which are independent of one another that can process programs and also perform fast memory accesses. Conventionally, it is subordinate to a master processor, all of whose CPU its actions, including the initialization, can be controlled. The coprocessor goes into the inactive state after receiving a "reset" pulse. The initialization runs as follows: The (master) CPU sets one through the initialization specified memory cell, called "busy flag", to 255. Then the CPU delivers one Impulse to a "Channel Attention" connection CA of the coprocessor. This impulse one clock pulse may occur at the earliest after the "reset" pulse has ended. At the same time, the level at a "Select" connection SEL determines whether the coprocessor should work as a "master" or as a "slave". After that, the coprocessor needs at least 150 clock pulses for internal processing. At the end of this processing, it sets he set the busy flag to 0. The CPU, which continuously monitors this busy flag, recognizes that it is deleted, i.e.

that the coprocessor is now ready for normal operation. Normal operation means that the CPU can start and stop the coprocessor with CA signals. Closer Information on the job to be executed is in a special memory cell, the so-called Channel Control Word CCW. In the case of a CA impulse, definitely now the SEL connection, whether processing channel 1 or processing channel 2 is addressed will. Further details can be found in the data books of the input and output coprocessors can be removed.

From Figure 4, the principle of the software of the inventive input and output computer. Since the coprocessor is supposed to work independently, i.e. If there is no master computer to supply it with control signals, the workflow from the coprocessor itself or from special hard-wired circuitry being controlled. The sequence control does not provide any during operation Difficulty because, for example, processing channel 1 starts processing channel 2 can (Figure 4). However, the initialization cannot be carried out in this way special measures are necessary for this.

After the "reset" pulse, the starting circuit shown in FIG. 5 delivers 7 the required signal pulses, with the timing conditions shown in FIG.

The first CA pulse starts the internal processing of the coprocessor 5; the signal SEL is at logic zero, i.e. the coprocessor 5 is working as "master". The second CA pulse then starts a program in the processing channel 1.

The so-called communication blocks, i.e. those to be processed for the workflow Memory contents must be stored in read-only or ROM memory during initialization 31 stand. For the rest However, it is necessary to work that a channel control block CB is in the read / write or RAM memory 30, since this Block contains CB values that must be changeable, such as a channel control word, which provides information about what to do in a channel after a CA pulse.

To solve this problem lie on a certain address range the RAM memory 30 and the ROM memory 31 in parallel (see also FIG. 7). While the initialization is only read from the ROM memory and into the RAM memory only registered, so that the coprocessor uses the same addresses builds a new channel control block. This is necessary because one acts as a channel pointer or channel pointer designated internal register, which on the channel control block CB shows, is only loaded once during the initialization and not later can be changed.

After the new channel control block has been set up in RAM memory 30, can be switched off completely by a command of the ROM memory 31, so that now only the RAM memory is in this address area. via one of the coprocessor The coprocessor 5 can process the self-generated CA pulse CSCA in the channel 2 start and stop from channel 1.

The starting circuit 7 contains a switching mechanism 34, which is based on in detail of Figure 8 will be explained, a D flip-flop 35 and a multiplexer 36, the through the from the drawing visible signal lines with each other, with the coprocessor 5 and with the circuit components still to be explained with reference to FIG are connected. For the inputs and outputs of the blocks and for the the same designations are used for these signals. That already The mentioned Channel Attention CA corresponds to the start signal and also to one Connection to the coprocessor 5. CS (Chip Select) is a chip selection signal. CSCA is the start signal generated by the coprocessor itself. CSBoOt is one from the coprocessor generated pulse to switch from initialization to normal operation. EXT1 is a - not shown in the drawing - connection to coprocessor 5, which can be used to cancel processing. OE (Out Enable) is a through-connection sign for the output buffers in stores. Reset is the aforementioned reset signal and a corresponding port on coprocessor 5. R is an output from the coprocessor Read signal and h a write output signal from him.

The switching pulse Cm boot is the clock input of the D flip-flop 35 fed. The selection signal SEL is output at its Q output, as mentioned above is applied to the corresponding input of the coprocessor 5 and also to the control input of the multiplexer 36 is fed to either the output signal CA of the switching mechanism 34 or the signal CSCA to the CA connection of the coprocessor 5.

The selection signal SEL also arrives at the control input of a demultiplexer 37 (Figure 7), and thus determines whether the read signal R the ROM memory 31 or the RAM memory 30 activated, through its OE input.

The signals OE and W are only effective if the relevant module is controlled via the block selection signal CS.

In the lower part of Figure 7 it is graphically shown which Part of the address space when reading and writing depending on the status of the signal SEL is accessed.

The ones required for initialization and memory switching Signals CA and SEL are with the timing conditions shown in Figure 6 in the Starting circuit 7 generated. Their switching mechanism 34 (FIG. 8) contains a counter chain 38, which consists of two 4-bit binary counters 39 and 40 and a flip-flop 4.1, as well as several logical links, as shown, are wired and one Form decoder 42 which decodes the output signals of binary counters 39 and 4-0 and generates the control signal CA accordingly.

The flip-flop 35 receives the signal ## Boot and gives the output signal SEL, which switches on the ROM memory 31 during the initialization phase and then, as already explained, switches to RAM memory 30.

The binary counters are clocked with a so-called peripheral clock PCLK, which has half the frequency of the processor clock.

Claims (3)

Claims input and output computer for a telecommunications system, in which messages are exchanged between different processing units, d a d u r c h g e -k e n n n z e i c h n e t that he has: one for the dependent Sending and receiving messages trained coprocessor (5), which is responsible for the initialization required signals (SEL, CA) by a start circuit (7) delivered, one only during the initialization with the coprocessor (5) connected read-only memory (31) and a switching device (34, 35) through which a switch is then made to the read / write memory (30). 2. Input and output computer according to claim 1, characterized in that that the read only memory (31) and the write / read memory (30) on one part of the address area are connected in parallel. 3. Input and output computer according to claim 1 or 2, characterized in that that the starting circuit (7) has: a counter chain (38), one of logic elements existing decoding circuit (42) in which a start signal (CA) is generated, and a D flip-flop (35) in which a memory switching signal (SEL) is generated.