DE3237552C2 - - Google Patents

Description

The invention relates to a decoder for implementation a PCM-coded input signal into a pulse density modulated Output signal, as well as the application of this decoder in a digital-analog Converter.

Such a decoder is known from DE-OS 26 05 724. This decoder can be used, for example, for a digital-analog Converter on the receiving side of a PCM message transmission systems can be used. In this known decoder the PCM-coded input signal is fed to an interpolator, which appears to be the sampling frequency of the PCM-encoded input signal bar increased. The output signal of the interpolator is in one Quantizers rounded to a number of the most significant bits and fed to a digitally controllable clock converter provides a pulse density modulated signal at its output. Out this pulse density modulated signal can have a low pass analog signal are formed.

A decoder is also known from DE-OS 27 53 616 the input of which is arranged a subtractor which the difference between the respective PCM-coded input signal and the previous output signal from the decoder forms, this difference signal a digital integrator is supplied, the difference signals through a successive Addition to a total value at one speed speed added, which is determined by a clock signal. The Total value is then fed to a threshold detector the output of which forms the output of the decoder and whose Output signal either a high positive digital or can have a high negative digital value. Here too can in turn the output signal of the threshold detector and thus the decoder into an analog signal via a low-pass filter being transformed.

The invention has for its object a decoder to create a minimum of components required.

This task is carried out in the characterizing part of the Features specified claim 1 solved, or with regard to the use of this decoder in a digital-to-analog converter by the features in Claim 11 solved.

Advantageous refinements and developments of the invention result from the subclaims.

The decoder according to the invention requires a minimum Components and is therefore for the production in the form of a integrated circuit. To be a digital-analog Implementation of a digital input signal from the decoder enable the decoder a suitable filter downstream. When used for digital-analog An interpolator would be connected upstream of the decoder would be and the resulting digital-to-analog converter would only need a minimum of analog components.

Exemplary embodiments of the invention are described below of the drawings explained in more detail.

The drawing shows:

Fig. 1a, the application of the pulse density modulation to an analog input signal,

FIG. 1b, the application of the pulse density modulation on a digital input signal,

FIG. 2a is a known from US-PS 39 55 191 acquired part of a modulator for converting an analog signal into a pulse density modulated signal,

Fig. 2b is a partial modification of the digital Fig. 2a,

Fig. 3 is a decoder for digital signals, which is derived from the pulse density modulator of Fig. 2 abge,

Fig. 4 shows a modification of the digital signals into pulse density modulated signals De-converting the encoder of Fig. 3,

Fig. 5 shows a modification of the decoder of FIG. 4,

Fig. 6 shows a modification of the decoder of FIG. 5,

Fig. 7 shows a modification of the decoder of Fig. 6 with a minimum number of adders and multipliers and

Fig. 8 shows a further decoder arrangement with the minimum number of components.

The function of an ideal digital-to-analog converter exists in converting a digital number into a voltage or a current to implement, which is proportional to this number. At night Directional transmission systems make the digital numbers sampling values of a continuous signal represented in regular  Sampling intervals are detected. In this case the ideal digital-to-analog converter a continuous one generate analog output signal, which by pulling gives a smooth curve through the samples and that no components above half the sampling frequency holds. The aforementioned DE-OS 26 05 724 describes one Digital-to-analog converter with a modulator for implementation of the digital input signal into a pulse density modulated Signal that uses a clock converter. The same already mentioned US-PS 39 55 191 relates to a Analog-to-digital converter with a pulse density modulator that analog samples in a pulse density modulated signal implements.

The embodiments of the digital-to-analog converter, which are described in detail below are based on a fully digital pulse density modulator and put linear PCM samples into a binary pulse density modulated Data stream of the sigma-delta type. The modulator is his Essentially a converter or decoder, but not a demo dulator. Demodulation is simple using a simple RC filter or a more complicated one Filters, if this is to eliminate the high-frequency Mo dulation components is necessary.

There is a difference between implementing one Analog signal into a pulse density modulated signal and the Conversion of a digital signal into a pulse density modulated Signal. This difference does not apply to the Pulse density modulation itself, but rather on the means to increase the sampling frequency of the linear PCM-encoded Input signal to the sampling frequency of the digital pulse density modulated  Signal. Unlike a continuous one The digital data require an analog signal Interpolator in any form. According to his com complexity, the interpolator can have an additional quality cause loss of the output signal.

In Fig. 1a and b, the implementation of an analog and a digital input signal in pulse density modulation is shown and compared schematically. In Fig. 1a, an analog signal is input to a pulse density modulator 1 for analog signals, and the modulator operated at a clock frequency f _c supplies a binary data stream of the sigma-delta type, which is modulated at a clock frequency, to its output. This output signal is fed to a conversion filter in the form of a digital filter 2 , which is also operated at the clock frequency f _c and outputs linearly coded PCM words with M bits at an intermediate sampling frequency f _{s at the} output.

In Fig. 1b, a linear PCM-coded input signal in the form of M-bit words at a sampling frequency f _{s is} input to an interpolator 3 , which is operated at the clock frequency f _c be. The output signal of the interpolator 3 , which contains M-bit words with the pulse density modulation sampling frequency, is applied to a pulse density modulator 4 for digital signals, which is operated with the clock frequency f _c . The output signal of the pulse density modulator 4 is a binary signal of the sigma-delta type modulated with the clock frequency. This signal can be demodulated into an analog signal by means of an RC filter, not shown.

Fig. 2 shows part of a pulse density modulator for ana log signals, which is taken from Fig. 8 of US-PS 39 55 191. It contains an operational amplifier A and a flip-flop B together with an additional flip-flop B 'and a dashed path, which represents a possible feedback loop.

Fig. 2b shows a conventional, essentially digital modification of Fig. 2a with two adders 5 and 6 , a multiplier 7 and a flip-flop B ''. The values of R ₁ , R ₂ , C ₁ and C ₂ are not the same as in Fig. 8 of U.S. Patent 3,955,191.

3 shows a decoder for digital signals, which is derived from the arrangement according to FIG. 2b . It consists of adders 8, 9 and 10 , an X-bit memory register 11 , a Y-bit memory register 12 , and a digital comparator with read-write memory 13 and six multipliers 21 to 26 , the constants K ₁ to K ₆ of which are obtained from the corresponding simulation formula set out below. The memory registers 11 and 12 and the comparator 13 have a delay time of Z ^-1 , namely a clock period T = 1 / f _c . The comparator 13 provides an output ± P, the sign of which depends on whether V ₁ ³ at the beginning of a clock pulse at time T, 2T, 3T etc. is negative or positive.

The expressions V ₀ ¹ and V ₀ ³ stand for the undelayed numbers stored in the memory registers 11 and 12 and V ₁ ¹ and V ₁ ³ for the numbers resulting at the beginning of a clock pulse. At this time, the comparator 13 takes the logical value 1 or the logical value 0 according to the polarity of V ₁ ³ , taking the value 0 when V ₁ ^{3 is} positive. The output signal is therefore a binary data stream, which represents the digital input signal as a pulse density modulated one-bit signal, which can be demodulated into an analog signal by a simple RC filter, not shown.

The simulation formulas for Figure 2b are the following:

and V = V ₁ ¹ ₀ ¹ · K ₁ + δ (1 - K ₁₎ (2)

where K ₁ = e ^{-T / C₁R₁} , K ₂ = e ^{-T / C₂R₂} , δ = P + E.

If K = 1 / (1 - R ₂ C ₂ / R ₁ C ₁ ) is set, then from equation (1):

V ₁ ³ = V ₀ ³ · K ₂ + V ₀ ¹ · K (K ₁ - K ₂₎ μδ μ + · (1 - K ₂₎ - μ · K · δ (K ₁ - K ₂₎ + P ₀ ( 1 - K ₂ ) (3)

With (K ₁ - K ₂ ) = K ₄ , equation (3) becomes:

V ₁ ³ = V ₀ ³ · K ₂ + V ₀ ¹ · K · K ₄ · μ + μ · δ [1 - K ₂ - K · K ₄ ] + P ₀ (1 - K ₂ ).

With μ · K · K ₄ = K ₆ , μ [1 - K ₂ - K · K ₄ ] = K ₅ ,
(1 - K ₁ ) = K ₄ and (1 - K ₂ ) = K ₃

V ³ = V _{1 0} ³ · K ₂ + V ₀ ¹ · K ₆ + δ · K ₅ + K P _{0 3} (4)

and V ₁ ¹ = V ₀ ¹K ₁ + δK ₄ (5)

which corresponds to the arrangement of the components in Fig. 3.

There are numerous ways of realizing the completely digital basic circuit according to FIG. 3 by a different arrangement of the different circuit paths and by cross-multiplication or division of the different multiplication constants. Examples of this are shown in FIGS. 4 to 8.

With K ₆ (1-K ₁ ) = K ₈ , equation (2) becomes V ₁ ¹ = V ₀ ¹ · K ₁ + δ · K ₈ / K ₆ , and thus by comparison with equation (5): K results ₄ = K ₈ / K ₆ or K ₈ K = ₄ · K. ₆ This means that when the multiplier in FIG. 3 is removed with the value K ₄ , as shown in FIG. 4, ie if K _{4 is made} equal to 1, the multiplier K ₆ from FIG. 3 must be replaced by a multiplier 28 in FIG. 4 with the value K ₈ , namely K ₆ (1-K ₁ ), so that V ₁ ³ remains unchanged.

The arrangement according to FIG. 5 has arisen from FIG. 3 in that the value of K _{6 has been made} equal to 1, as a result of which the multiplier with the value K ₄ can be replaced by a multiplier K ₈ , which, like the multipliers with the values K ₅ and K _{3 is divided} by the value of K ₅ , in FIG. 5 the path which previously contained the multiplier with the value K ₅ becomes a direct connection.

The arrangement according to FIG. 6 is a modification of the arrangement according to FIG. 5, in which an input signal of the adder 10 is tapped before the adder 8 instead of after it and consequently the multiplier with the value K ₃ in FIG. 3 has the value (1+ K ₃ / K ₅ ).

FIG. 6 can be modified into the form shown in FIG. 7, which has a smaller number of adders, in that the adders 8 and 9 are effectively replaced by an adder 4 . Thus, the digital basic version according to FIG. 3, three adders and six multipliers contains converted into a version with two adders and four multipliers.

As can be seen, the circuit according to FIG. 7 contains two separate filters F and G which work in parallel and which have a coupling to one another which contains a multiplier with a value K ₈ / K ₅ .

In the decoder according to FIG. 7, a digital input signal E is therefore input into a simple recursive filter G, the output of which is connected to the digital comparator 13 . A signal P, which has one of two fixed values corresponding to the output signal of the comparator 13 , is also input into the filter G. The input signal E is also input to a second recursive filter F, and a fixed portion of its output signal reaches the filter G. A signal Q, which has one of two fixed values corresponding to the output signal of the comparator 13 , is fed to the input of the second recursive filter F. . The output signal of the comparator 13 is a pulse density modulated binary signal which can be demodulated into an analog signal by means of an RC filter.

Yet another arrangement of the components, which also converts an input signal into a pulse-density-modulated binary signal, is shown in FIG. 8. It also consists of only two adders 9 and 10 and four multipliers 15, 16, 21, 22 , that is to say from a minimal number of components, and is therefore particularly suitable for production in the form of an integrated circuit. The values of the multipliers 15 and 16 are chosen so that they fulfill the same simulation formulas given above. At the decoder of FIG. 8, a digital input signal E is a simple recursive filter F ', respectively, and a fixed proportion of whose output is a second simple recursive filter G' is supplied. A signal P ', which is a fixed portion of one of two fixed values of a signal Q' corresponding to the output signal of the comparator 13 , is also input into the filter G ', whereas the signal Q' is input into the filter F '. The output signal of the comparator 13 is a pulse density modulated binary signal as described above in connection with FIG. 7.

It should be noted that the number P (or P '), which is a fixed number with two possible values according to the output signal of the comparator, can be integer, fractional, or both. It can be symmetrically positive or negative, or asymmetrically positive or negative, or it can have only one polarity. The constants K ₁ and K _{2 of} the multipliers 21 and 22 will only be positive fractions, whereas the other constants K _{3 can be} negative and positive, integer or fractional or somehow combined. For storing in registers 11 and 12 of the X-bit and Y-bit words, more than one bit will be provided, where X can also be Y.

Claims (11)

1. Decoder for converting a PCM-coded input signal into a pulse density modulated output signal, characterized in that it contains a first (F) and a second (G) recursive filter, at least the first filter (F) with the input (E) of the Decoder is connected, that the output of the first recursive filter (F) is connected to an input of the second recursive filter (G), that the output of the second recursive filter (G) is connected to a digital comparator ( 13 ) emitting the pulse-density-modulated output signal that the digital comparator ( 13 ) depending on its pulse density modulated output signal one of two predetermined signal values (P ₀ ) and part of it at the input of the first recursive filter (F) and another part (P ') thereof at the input of the second outputs recursive filter (G) ( Fig. 3- Fig. 8). 2. Decoder according to claim 1, characterized in that each recursive filter (F, G) has a respective memory register ( 11, 12 ) which is in a loop with a respective multiplier ( 21, 22 ) and a respective adder ( 9, 10 ) is arranged, a further input of the respective adder ( 9, 10 ) forming the respective filter input and the output of the memory register ( 11 ) assigned to the first recursive filter forming the filter output of the first recursive filter and the input of the second recursive filter Storage register ( 12 ) forms the filter output of the second recursive filter. 3. Decoder according to claim 1 or 2, characterized in that a third multiplier ( 26, 28 , K ₈ / K ₅ , 15 ) is connected between the output of the first recursive filter (F) and the input of the second recursive filter (G) ( Fig. 3, Fig. 4, Fig. 7, Fig. 8). 4. Decoder according to claim 3 and claim 2, characterized in that the predetermined signal value (Q, Q ') directly to an input of an adder ( 14, 9 ) which forms the input of the first recursive filter (F), and via one fourth multiplier ( 16 ) arrives at an input of the adder ( 10 ), which forms the input of the second recursive filter (G) ( FIG. 7, FIG. 8). 5. Decoder according to claim 2 or according to claims 3 and 2, characterized in that a third adder ( 8 ) between the input (E) and the adder ( 9 ) is connected, which forms the input of the first recursive filter (F) ( Fig. 3- Fig. 6). 6. Decoder according to claim 5, characterized in that the predetermined signal value (P ₀ ) directly to the third adder ( 8 ) and via a fifth multiplier ( 23 ) to an input of the adder ( 10 ) which receives the input of the second recursive Filters (G) forms ( Fig. 3- Fig. 6). 7. Decoder according to claim 6, characterized in that the output of the third adder is connected via a line to an input of the adder ( 10 ) which forms the input of the second recursive filter (G) ( Fig. 5). 8. Decoder according to claim 7, characterized in that a sixth multiplier ( 25 ) is connected in the line ( Fig. 3, Fig. 4). 9. Decoder according to claim 5, characterized in that the input (E) is connected directly to an input of the adder ( 10 ) which forms the input of the second recursive filter (G) ( Fig. 6). 10. Decoder according to one of claims 2-9, characterized in that the memory registers ( 11, 12 ) are operated in combination with an interpolator with a clock of a first clock frequency, the interpolator ( 23 ) consisting of a linear pulse code modulated signal at an intermediate -Sampling frequency multiplied by the PCM rate forms the input signal of the decoder in the form of M-bit words at the sampling frequency of the pulse density modulation, so that a binary pulse density modulated signal of the sigma-delta type appears at the decoder output, the bit rate of which is equal to the first clock frequency . 11. Digital-to-analog converter with a decoder after one the preceding claims, characterized in that the digital Comparator of the decoder connected another filter is that the pulse density modulated output signal in a analog output signal demodulated.