DE3235662A1 - Decoder circuit for selection lines of semiconductor memories - Google Patents

Abstract

The invention relates to a decoder circuit which comprises a number of NOR decoder gates (G1). The latter can be selected via address lines (L1 ... L2n). The object is to attain a reduction in power consumption compared with conventional circuits of this type. This is achieved according to the invention by inserting a switching transistor (TS1) in the branch (2) of each NOR decoder gate (G1) to which the supply voltage is applied, which transistor is activated via an address line (L4) which is not used to activate the other switching transistors (T1 ... Tn) of the same gate (G1). No shunt current therefore occurs on around half of all unselected gates. The field of application includes integrated MOS logic circuits. <IMAGE>

Description

AKTIENGESELLSCHAFT Our mark

Berlin and Munich YPA 82 P 18 5 8

Decoder circuit for selection lines of semiconductor memories

The invention relates to a decoder circuit for Select lines from semiconductor memory! according to the generic term of claim 1.

It is based on the task of a decoder circuit of this type, which in static operation has a lower power consumption than conventional decoders, without the circuit complexity having to be increased significantly. According to the invention, this is achieved through training the decoder circuit according to the characterizing part of claim 1 achieved.

The advantage that can be achieved with the invention is, in particular, that the power consumption in static operation reduced by simple circuit measures to almost half of the values occurring with known decoders at the same time a very even capacitive load on the address lines used for control is guaranteed.

Claims 2 to 4 are directed to preferred configurations and developments of the invention.

The invention is explained in more detail below with reference to a preferred exemplary embodiment shown in the drawing.
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Two HOR gates G-1 and G2 of a decoder circuit 1 are shown, which has a total of 2 ⁿ such NOR gates.

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One can be selected from 2 ⁿ decoder outputs A1 to A2 ⁿ , depending on η address bits x0 to x (n-1), which can each assume the values 0 or 1. In addition to these address bits, the negated address bits xü to x (n-1) are derived via inverters (not shown) and, together with the non-negated address bits, are applied to a total of 2n inputs E1, E2, E3 ... E2n, which are connected to 2n address lines L1, L2, 13 ... L2n are connected. The decoder output selected as a function of the address bits present is then in each case at a high potential, while the other outputs are switched to low potential. Via the selected decoder output, e.g. A1, in the illustrated embodiment, a connected word line, e.g. WL1, of a memory matrix SP is assigned a voltage in a manner known per se, through which all memory elements whose selection transistors are connected to this word line are selected or selected. In total there are 2 ^]

Drawing indicated.

the. There are a total of 2 ⁿ word lines WL1 to WL2 ²¹ in FIG

The NOR gate G1 consists of the series connection of a first branch 2 with a parallel connection of η second branch 31 to 3n. The branch 2, the connected to the Ye rs orgung s voltage Y- ^ via a connection 4 is, contains the switching path of a first switching transistor TS1, while each of the second current branches 31 to 3n has a second switching transistor T1 to Tn. The second switching transistors are with their drain connections are connected to an output line LA1, while their source connections are at reference potential. Your gate connections are each on one of the two address lines that belong to an address bit, d. H. either on the line «In with the negated or with the non-negated address bit in the drawing, for example, the gate of TI is connected to line L1 and is therefore applied with xO,

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the gate you T2 with 13 etc. The gate of IS1 is also connected to an address line, although only one that is not connected to the gate of one of the second switching transistors 11 to Tn of this HOR gate comes into question. In the case shown, the gate of TS1 is connected to the address line 14.

The first current branch 2 has a resistance which is greater than the resistance of one of the second current branches 31 to 3n when its switching transistor conducts. Replaces if the block 4 indicated by dashed lines is first short-circuited, the resistance condition mentioned becomes observed in that the switching transistor IS1 with a sufficiently high resistance is provided, e.g. with a long and narrow canal area between the Source and drain areas. If, on the other hand, the switching path of TS1 is of low resistance, then it is expedient

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a block 4 shown load element is provided, which consists of a field effect transistor LI, the gate with is connected to its source terminal.

The other! OR gates G2 etc. are corresponding to the gate G1 formed, with each other assignments of the Gate connections of the second switching transistors to the individual address lines L1 to L2n are made.

In order to select a certain gate, for example G1, all of its second switching transistors, for example 11 to In, must be blocked via the connected address lines. To select G1, the address bits x0 to x (ni) each have the value 0, while the address bits xQ ~ to x (n-1 ) each have the value 1 accordingly. Since the line L4 is assigned a 1, IS1 is in the conductive state. It follows from this that the output line LA1 is connected approximately to the supply voltage Y- ^. This is fed in via A1 word line WL1. With the rest, ie not; selected NOR gates G2 and so on

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in each case at least one of the second switching transistors conductive, so that their output lines LA2 etc. are at ground potential lie.

The first switching transistors, e.g. TS1 from G-1 and TS12 γόη G2, are now with regard to their control so on the total existing address lines 11 to L2n divided, that as many first switching transistors as possible are connected to each of the latter. So that will achieved that about half of all unselected HOR gates have the gate connections of their first switching transistors are on address lines that are currently assigned an O, so that they block. With these MOR-G atters no cross current occurs in the unselected state. Cross currents only flow when they are not selected NQR gates, their first and second switching transistors are switched on. But since in each case the gate terminal of the first switching transistor only may be connected to address lines that are not connected to one of the gate connections of the second Switching transistors of the same EOR gate are connected, only the required NOR gate is selected.

4 claims
1 figure

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Claims (4)

₂ ρ 1 8 5 8 OE Claims (ΐ., decoder circuit for selection lines of semiconductor memories, consisting of an Ansah! iron lOR decoder gates, the address lines to which address bits and the negated addresses Mts "are applied can be controlled are, the gate outputs with the selection lines "are wired, characterized that the NOR decoder gates (G1) each from a series connection of a first current branch (2) connected to the supply voltage and the parallel connection a number of second current branches (31 ... 3n) "corresponding to the number of addresses Mts" exist, that the first branch (2) contains a first switching transistor (£ S1) and has a resistor, while in a second switching transistor (11 ... Un) is arranged in each of the second current branches (31 ... 3n), and that · the gate connection of the first switching transistor ((ESI) is connected to one of the address lines (L1 ... L2n), with those This excludes address lines which are connected to the gate connections of the assigned second switching transistors (31 ... 3n) of the same HOR gate (G-1) are connected, and that the first switching transistors (IS1, TS12 etc.) with respect to their control is divided over a plurality of the address lines (L1 ... L2n) that are considered are. 2. Decoder circuit according to claim 1, characterized characterized in that each of the address lines (li1 ... L2n) to control an equally large number of the first switching transistors (TS1, TS12 etc.) is used. 3. Decoder circuit according to claim 1 or 2, characterized characterized in that the resistance of the first Branch (2) of a NOR gate (G-1) from the resistor the source-drain path of the first switching transistor (TS1) is available. 82 P 1 8 5 8 OE 4. Decoder circuit according to claim 1 or 2, characterized in that the resistor of the first branch (2) of a UOR gate (G-1) consists of a load element (LiD) » BATH ORIGINAL