DE3234607A1 - Method and circuit arrangement for detecting a selected image information area - Google Patents

Abstract

The invention relates to a method and a circuit arrangement which is provided with a controllable information-oriented frame dissection of a television or semiconductor sensor frame of any standard and considerably shortens the digital frame processing and pattern recognition with regard to the necessary computing time. Using the method and the circuit developed for it, information-carrying locations in the frame are selectively processed. These locations are already detected during the frame writing phase. Utilising the frame synchronising pulses existing in all standards, the circuit developed generates an n-fold reference frequency with the aid of a frequency synthesis circuit (PLL). The phase-locked higher frequency generated is used for quantising the frame content via a programmable selection logic. The quantising time within the line or frame content (gate function), that is to say the position and duration of quantisation, can be determined via a further control arrangement (geometry latch). Using these two functions, a selective frame scan, and thus an object-matched pattern recognition, can be carried out via an evaluation by program means. <IMAGE>

Description

DESCRIPTION

The invention relates to an arrangement for controlling a selection logic for the acquisition of a selected image information content from an electronic Image signal. Arrangements of this type are important subsystems for the digital Image processing and pattern recognition. The image processing and pattern recognition are used television cameras since their early days and, more recently, semiconductor matrix cameras as well as recording systems. To process black and white images with up to 256 shades of gray, you need a very large image memory. If you follow from a television picture 625 lines and 833 pixels per line (same resolution in row and column direction) 8 bit video information results in a total amount of image information of around 4 million bits. If you wanted this amount of data with an 8 bit microprocessor transport into an image memory (move command approx. 2us.) so approx. 1s. consumed. Since a response time of If less than 0.5 s is required, the image processing time must be without major loss of information be shortened.

The information reduction necessary to shorten the processing time is carried out with known devices, e.g. P 30 38 195.4-53, by means of programming Information reduction by converting the rasterized and digitized image area into a A plurality of blocks is divided and the image of each block is processed. The number of blocks is varied to compress the data.

Another form of simplification is direct information reduction (German patent application P 2513 655.4), which has only a few lines to be specified in advance evaluates the television picture.

The invention is based on the object of a sampling strategy realize that when scanning image information in simple places hardly Time consuming, but working with the maximum resolution in complex places can. To implement this process, a circuit arrangement was developed, the first via the image information supplied by an image recording system Cartesian grid of size (N x M), where N and M are freely selectable (others Formats), and secondly a working matrix with the variable size n in any Position can be displayed as a projection in the rasterized x, y image plane.

The circuit arrangement also contains a control unit that over a recursive query procedure controls the rasterization of the image information and the Working image matrix positioned in information-bearing image areas.

This object is achieved according to the invention by the following circuit arrangement solved: First of all, the line image supplied by the imager (television semiconductor camera) is and image sync signal processed (level converter) and an internal sync signal derived in the pulse separation stage (Fref). This signal is used as the reference signal a frequency synthesis circuit, here a PLL (phase-locked loop). The way it works, the PLL is a servo system that controls the phase of a VCO (voltage controlled oscillator) tracks the phase of the input signal. In the present When used, the VCO oscillates at a frequency that is higher by a factor of N, whereby through a programmable divider derived the comparison signal for the PLL comparator will. After the PLL has locked, the VCO can use a quantization frequency that is higher by a factor of N can be removed. For scanning the analog line content, the N is higher Frame rate fed to a fast A / D converter. The number of quantization steps, which break down the content of the line results in the fineness of the grid that is in the image field is projected and thus determines the area of existence of all surfaces.

To shorten the computation time, the first analysis is reduced the maximum quantization value specified by the VCO frequency (finest image rasterization). The reduction takes place through a programmable data selector, its divider signals control a transparent latch. The transparent latch leaves, depending on the programming of the data selector only every 2nd or 3rd ... etc. quantized and digitized Pass the video value for writing in the gray value memory.

The additional control of the data selector via a geometry latch (programmable preset counter) enables position-oriented control of the transparent latch, i.e.

only after reaching a predetermined number of quantization pulses (Start position) the geometry latch enables and disables the transparent mode again after a certain number of pulses (working range).

In the implemented system development, a work screen matrix was used of 128 * 128 grid elements selected, other formats can be generated. The recursive Search algorithm determines the location with relevant object information in that in a first analysis phase the number of quantized and digitized video pulses each line content in the image field is reduced to 128 picture elements. With the in The geometry latch becomes the geometry latch programmed and depending on the minimum and maximum x, y components of the image area to be analyzed, the grid size (data selector) is programmed in such a way that that the working image matrix is integrated into it. With one implemented according to this process Circuit arrangement is possible, large image matrices with little computational effort edit at maximum resolution.

The sequence of selective information rasterization is shown in Figure 1.

Figure 2 is the block diagram of the structure according to the invention.

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Claims (5)

Method and circuit arrangement for detecting a selected one Bildinformalionsl) oreiche, PATENT CLAIMS 0. Device for controlling a selection logic for information-oriented rasterization of an electronic image signal (television or semiconductor array image information), which are used for fast execution of pattern recognition Operations makes a decisive contribution. 2. The arrangement according to claim 1 is characterized in that the Synchronization characters of a BAS signal (picture, blanking and synchronizing signal) any international standard by means of frequency synthesis e.g. PL (phase-locked loop) into a Output frequency can be implemented which is greater than that by any factor N given reference frequency F ref. is. The factor N is determined from the number of lines M the transmitted image information and the image format used. The number of the samples N within a line, which are used to form a dot matrix (N * X and M * Y) points and an equal resolution in row and column directions required can be programmed (partial counter). That from German television The 4/3 format with 625 lines used in accordance with the CCIR standard, for example, requires quantization in 833 samples per line duration. Form the synchronization characters separated in the pulse separation stage the frequency standard, i.e. the reference value for the generated higher output frequency (Sample N), the stability of which is just as great as that of the frequency standard. There are thus fixed geometric relationships in which individual positions adres «ierhar are. The fading out of individual positions within the generated X, Y point grid (Teilerz ie ler) is done by controlling a transparent latch via a programmable one Data selector. The data selector reduces the data from the A / D converter with the sampling rate N. digitized image information of the individual pixel positions on a given, Maximum number (available storage space in the gray value memory) of points (working image matrix). 3. By a second arrangement, which is characterized in that the programmable data selector is coupled to a geometry latch that controls the Starting position and the number of points (gate function) determined can be a position-oriented Control of the transparent latch can be carried out. Through the two functions can quantized and digitized video information in terms of position and grid spacing can be variably controlled. For the synchronous writing of the video data in the gray value memory the control signals must be fed to the central control unit. 4. The addition of the arrangement according to claim 2, is characterized in that that a digitally programmable PLL is used for frequency synthesis to To generate a locally variable grid spacing. That’s a locally limited compression or expansion of a projected image object is possible. 5. The arrangement of claims 1-4 is expanded in that a central control unit communicates with a computer that uses a recursive query procedure in the form of a program. The recursive query procedure controls the size of the image grid depending on the object size to be analyzed and positioned the working image matrix.