DE3231457A1 - Process for the production of structures for integrated semiconductor circuits by reactive ion etching - Google Patents

Abstract

The process of the invention uses as the mask (2) negative lacquer structures (2) produced by electron-beam writing, and, before the reactive ion etching of the structures (1,4) which, for example, serve as conductor patterns, an additional dry etching process is carried out for a short time in an oxygen atmosphere at low pressure and in the same parallel plate reactor in order to produce steep lacquer flanks (2). This provides the possibility of shortening the conductor structures (1,4) anisotropically, i.e. without undercutting. The process is applied in the metallisation of integrated circuits by electron-beam writing. <IMAGE>

Description

Method for generating structures for integrated

Semiconductor circuits by reactive ion etching.

The present patent application relates to a method for generating of structures, in particular serving as conductor tracks, in integrated semiconductor circuits containing substrates by reactive ion etching using electron beam write generated negative resist structures as a mask.

An application of electron beam writing in semiconductor technology is the so-called individual wiring. This type of wiring can be there it is better suited for automation, with electron beam writing faster and easier than with conventional photolithography, which is relatively complex Mask manufacturing process requires to be performed.

The lacquer structures for the wiring level are produced with the help of a so-called negative resist, which is more sensitive to electron beams Lacquer, for example from the group of polyvinyl alcohol derivatives, its mode of action is based on the fact that the exposure initiates a polymerization process, by which the paint is made resistant to the solvents in these areas.

More details on negative resist technology for metallization of integrated circuits by electron beam writing are from Siemens Research and Development Report Vol. 11 (1982) No. 4 from a Essay by E. Hieke on pages 174 to 179.

This article shows, among other things, that for structuring of integrated circuits as part of the individual wiring using the Electron beam writing high resist thicknesses in the range between 1 and 2 in order to overcome are required by levels of levels below. Negative resists in area 2 2 a sensitivity below 10 pC / cm2 (= RCoulomb / cm2) usually have an inadequate Contrast and also disturbing ones arise due to the backscattered electrons Runners at the foot of the lacquer webs that have to be removed (trimmed) so that a strictly anisotropic etching of the underlying conductor track pattern can take place.

The object of the present invention is to provide a method by which these disturbing runners are eliminated without the width and The height of the lacquer ridges can be changed significantly as a result of material loss.

From the IEEE Trans. On Elektron Devices, Vol. ED-28, No. 11, 1981, is on pages 1323-1331 from an article by Hirata et al, a dry etching process can be seen in which the trimming of the lacquer ridge runs (foot trimming) thereby takes place that first a plasma etching in a parallel plate reactor in which the Substrates are arranged on the cathode covered with a carbon plate, in an oxygen atmosphere at a pressure of 53 Pa and an RF power of 0.3 Watt and then the substrates in a tunnel reactor in a CF4 plasma easily overetched. A disadvantage of this process sequence is that the etching process is not strictly anisotropic.

The invention solves the problem posed in a travel of the type mentioned in a better and simpler way and is thereby characterized in that after developing the generated by electron beam exposure Lacquer structures and before reactive ion etching to create the desired structures an additional dry etching process in an oxygen atmosphere in the same parallel plate reactor at a pressure of less than 10 Pa and an HF power density of 0.1 to 0.5 Watt / cm is performed in less than 50 seconds, the one containing the structures Substrate is on the covered with a quartz plate HF-conducting electrode.

According to a particularly favorable embodiment according to the teaching of the invention, the RF power density is set to 2 watts / cm2 (f = 13.56 MHz), the pressure set to 5 Pa and the etching time to at least 20 to a maximum of 50 seconds and the electrode potential is kept in the range of -400 V.

Resists are preferred as electron beam-sensitive negative resists from one of the groups: polyvinyl carbazoles and glycidyl acrylates and bisazides (= NR 23, Siemens-resist) or polyglycidyl methacrylate-Co-3-chlorostyrene (= GMC-resist by Bell).

The method according to the teaching of the invention makes it possible given to obtain lacquer structures whose flanks or base points allow a To connect the dry etching process for the production of an interconnect pattern in the same reactor, in which a strictly anisotropic etching can be carried out.

Figures 1 and 2 in the drawing are intended to illustrate this. In this case, FIG. 1 shows, in a sectional view, an arrangement in which the disruptive runners have not yet been resolved, while Figure 2 is a according to the invention Process treated arrangement represents.

With the reference numeral 1, the substrate is, for example, aluminum interconnect material and 2 denotes the paint structure. The arrow 3 in Figure 1 marks the lacquer ridge tails.

The lines 4 drawn in dashed lines in FIG. 2 are intended to be anisotropic Indicate etched aluminum conductive path material.

As can be seen from the sectional view shown in Figure 2, there are steep flanks, whereby the bust size is retained. The paint thickness (2) is only marginally reduced.

3 claims 2 figures Blank page

Claims (3)

Claims 9 method for producing, in particular, as conductor tracks serving structures in substrates containing integrated semiconductor circuits by reactive ion etching using write by electron beam generated negative resist structures as a mask, d u r c h e -k e n n n z e i c h n e t that after the development of the resist structures produced by electron beam exposure (2) and before reactive ion etching to create the desired structures (1) an additional dry etching process in an oxygen atmosphere in the same parallel plate reactor at a pressure of less than 10 Pa and an RF power density of 0.1 to 0.5 watt / cm2 performed in less than 50 seconds, the one containing the structures The substrate (1) lies on the HF-conducting electrode covered with a quartz plate. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the RF power density to 2 0.3 / watt / cm, the pressure to 5 Pa and the Etching time set to a minimum of 20 to a maximum of 50 seconds and the electrode potential is kept in the range of - 400 V. 3. The method according to claim 1 and / or 2, g e k e n n -z e i c h n e t d u r c h the use of electron beam sensitive negative resists (2) from one of the groups: polyvinyl carbazoles and glycidyl acrylates and bisazides (NR 23, Siemens-resist), or polyglycidyl methacrylate-Co-3-chlorostyrene (GMC-resist- from Bell).